19  * Pin flags/attributes
22 /* TODO: replace hard coded pin attribute values with defines provided
34 #define SOC_GPIO_OPENDRAIN_POS          (2)
42 #define SOC_GPIO_IN_FILTER_DEGLITCH     (2 << SOC_GPIO_IN_FILTER_POS)
54 #define SOC_GPIO_INT_TRIG_DOUBLE_EDGE   (2 << SOC_GPIO_INT_TRIG_POS)
62 /** Connect pin to peripheral A. */
64 /** Connect pin to peripheral B. */
66 /** Connect pin to peripheral C. */
67 #define SOC_GPIO_FUNC_C                 (2 << SOC_GPIO_FUNC_POS)
68 /** Connect pin to peripheral D. */
70 /** Connect pin to peripheral E. */
72 /** Connect pin to peripheral F. */
74 /** Connect pin to peripheral G. */
76 /** Connect pin to peripheral H. */
78 /** Configure pin as input. */
80 /** Configure pin as output and set it initial value to 0. */
82 /** Configure pin as output and set it initial value to 1. */
86 	uint32_t mask;     /** pin(s) bit mask */
93 	uint32_t flags;    /** pin flags/attributes */
97  * @brief Configure GPIO pin(s).
101  * - configure pin(s) as input with debounce filter enabled.
102  * - connect pin(s) to a peripheral B and enable pull-up.
103  * - configure pin(s) as open drain output.
108  * a user wants. A pin will function correctly without clock enabled
110  * In some cases, e.g. when a pin is configured as an output with
111  * a pull-up and user wants to read pin's input value it is necessary
114  * @param pin  pin's configuration data such as pin mask, pin attributes, etc.
116 void soc_gpio_configure(const struct soc_gpio_pin *pin);
119  * @brief Configure a list of GPIO pin(s).
125  * @param pins an array where each item contains pin's configuration data.
126  * @param size size of the pin list.
132  * @brief Set pin(s) high.
134  * Set pin(s) defined in the mask parameter to high. The pin(s) have to be
136  * is part of pin struct is ignored.
138  * @param pin  pointer to a pin instance describing one or more pins.
140 static inline void soc_gpio_set(const struct soc_gpio_pin *pin)  in soc_gpio_set()  argument
143 	pin->regs->OVRS = pin->mask;  in soc_gpio_set()
145 	pin->regs->PIO_SODR = pin->mask;  in soc_gpio_set()
150  * @brief Set pin(s) low.
152  * Set pin(s) defined in the mask field to low. The pin(s) have to be
154  * is part of pin struct is ignored.
156  * @param pin  pointer to a pin instance describing one or more pins.
158 static inline void soc_gpio_clear(const struct soc_gpio_pin *pin)  in soc_gpio_clear()  argument
161 	pin->regs->OVRC = pin->mask;  in soc_gpio_clear()
163 	pin->regs->PIO_CODR = pin->mask;  in soc_gpio_clear()
168  * @brief Get pin(s) value.
170  * Get value of the pin(s) defined in the mask field.
172  * @param pin  pointer to a pin instance describing one or more pins.
173  * @return pin(s) value. To assess value of a specific pin the pin's bit
176 static inline uint32_t soc_gpio_get(const struct soc_gpio_pin *pin)  in soc_gpio_get()  argument
179 	return pin->regs->PVR & pin->mask;  in soc_gpio_get()
181 	return pin->regs->PIO_PDSR & pin->mask;  in soc_gpio_get()
189  * than 1/2 programmable divided slow clock period tdiv_slck, while a pulse with
191  * between 1/2 selected clock cycle and one tdiv_slck clock cycle, the pulse may
195  * tdiv_slck = ((div + 1) x 2) x tslck
198  * Setting the length of the debounce window is only meaningful if the pin is
199  * configured as input and the debounce pin option is enabled.
201  * @param pin  pointer to a pin instance describing one or more pins.
202  * @param div  slow clock divider, valid values: from 0 to 2^14 - 1
204 static inline void soc_gpio_debounce_length_set(const struct soc_gpio_pin *pin,  in soc_gpio_debounce_length_set()  argument
209 		pin->regs->STERS = pin->mask;  in soc_gpio_debounce_length_set()
211 		pin->regs->STERC = pin->mask;  in soc_gpio_debounce_length_set()
214 	pin->regs->PIO_SCDR = PIO_SCDR_DIV(div);  in soc_gpio_debounce_length_set()