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Searched defs:val (Results 1 – 25 of 905) sorted by relevance

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/Zephyr-latest/include/zephyr/sys/
Dbyteorder.h219 #define sys_le16_to_cpu(val) (val) argument
220 #define sys_cpu_to_le16(val) (val) argument
221 #define sys_le24_to_cpu(val) (val) argument
222 #define sys_cpu_to_le24(val) (val) argument
223 #define sys_le32_to_cpu(val) (val) argument
224 #define sys_cpu_to_le32(val) (val) argument
225 #define sys_le40_to_cpu(val) (val) argument
226 #define sys_cpu_to_le40(val) (val) argument
227 #define sys_le48_to_cpu(val) (val) argument
228 #define sys_cpu_to_le48(val) (val) argument
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/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32h5_clock.h76 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
97 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR1_REG) argument
98 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 3, CCIPR1_REG) argument
99 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 6, CCIPR1_REG) argument
100 #define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 9, CCIPR1_REG) argument
101 #define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR1_REG) argument
102 #define USART6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 15, CCIPR1_REG) argument
103 #define USART7_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 18, CCIPR1_REG) argument
104 #define USART8_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 21, CCIPR1_REG) argument
105 #define USART9_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 24, CCIPR1_REG) argument
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Dstm32u5_clock.h77 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
96 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR1_REG) argument
97 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR1_REG) argument
98 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR1_REG) argument
99 #define UART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR1_REG) argument
100 #define UART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR1_REG) argument
101 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR1_REG) argument
102 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR1_REG) argument
103 #define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR1_REG) argument
104 #define SPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR1_REG) argument
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Dstm32f410_clock.h15 #define CKDFSDM2A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 14, DCKCFGR_REG) argument
16 #define CKDFSDM1A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, DCKCFGR_REG) argument
17 #define SAI1A_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR_REG) argument
18 #define SAI1B_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR_REG) argument
19 #define I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 25, DCKCFGR_REG) argument
20 #define I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 27, DCKCFGR_REG) argument
21 #define CKDFSDM_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, DCKCFGR_REG) argument
24 #define I2CFMP1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG) argument
25 #define CK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG) argument
26 #define SDIO_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG) argument
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Dstm32l4_clock.h62 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
80 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) argument
81 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) argument
82 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG) argument
83 #define UART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG) argument
84 #define UART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG) argument
85 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) argument
86 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) argument
87 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG) argument
88 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) argument
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Dstm32f3_clock.h56 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
71 #define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG) argument
72 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG) argument
73 #define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR_REG) argument
75 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG) argument
76 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG) argument
77 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 5, CFGR3_REG) argument
78 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG) argument
79 #define TIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 8, CFGR3_REG) argument
80 #define TIM8_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 9, CFGR3_REG) argument
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Dstm32f7_clock.h66 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
80 #define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG) argument
81 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG) argument
82 #define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG) argument
83 #define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG) argument
84 #define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG) argument
94 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) argument
102 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, DCKCFGR2_REG) argument
103 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, DCKCFGR2_REG) argument
104 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, DCKCFGR2_REG) argument
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Dstm32h7_clock.h83 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
103 #define FMC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG) argument
104 #define QSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG) argument
105 #define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 8, D1CCIPR_REG) argument
106 #define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 16, D1CCIPR_REG) argument
107 #define CKPER_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG) argument
109 #define OSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG) argument
111 #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP1R_REG) argument
112 #define SAI23_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 6, D2CCIP1R_REG) argument
113 #define SPI123_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, D2CCIP1R_REG) argument
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Dstm32g0_clock.h60 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
75 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) argument
76 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) argument
77 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG) argument
78 #define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CCIPR_REG) argument
79 #define LPUART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG) argument
80 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) argument
81 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) argument
82 #define I2C2_I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG) argument
83 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) argument
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Dstm32g4_clock.h64 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
79 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) argument
80 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) argument
81 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG) argument
82 #define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG) argument
83 #define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG) argument
84 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) argument
85 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) argument
86 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG) argument
87 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) argument
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Dstm32f427_clock.h14 #define CKDFSDM2A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 14, DCKCFGR_REG) argument
15 #define CKDFSDM1A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, DCKCFGR_REG) argument
16 #define SAI1A_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR_REG) argument
17 #define SAI1B_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR_REG) argument
18 #define CLK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR_REG) argument
19 #define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR_REG) argument
20 #define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 29, DCKCFGR_REG) argument
Dstm32h7rs_clock.h79 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
102 #define FMC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG) argument
103 #define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 2, D1CCIPR_REG) argument
104 #define XSPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG) argument
105 #define XSPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, D1CCIPR_REG) argument
106 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, D1CCIPR_REG) argument
107 #define CKPER_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG) argument
110 #define USART234578_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIPR_REG) argument
111 #define SPI23_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 4, D2CCIPR_REG) argument
112 #define I2C23_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, D2CCIPR_REG) argument
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Dstm32u0_clock.h61 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
75 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) argument
76 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) argument
77 #define LPUART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG) argument
78 #define LPUART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG) argument
79 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) argument
80 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) argument
81 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) argument
82 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) argument
83 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG) argument
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Dstm32wl_clock.h63 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
77 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) argument
78 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) argument
79 #define SPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG) argument
80 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) argument
81 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) argument
82 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG) argument
83 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) argument
84 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) argument
85 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG) argument
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Dstm32wb_clock.h63 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
80 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) argument
81 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) argument
82 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) argument
83 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) argument
84 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) argument
85 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG) argument
86 #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG) argument
87 #define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG) argument
88 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG) argument
[all …]
Dstm32wba_clock.h71 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
86 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR1_REG) argument
87 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR1_REG) argument
88 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR1_REG) argument
89 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR1_REG) argument
90 #define SPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR1_REG) argument
91 #define SYSTICK_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR1_REG) argument
92 #define TIMIC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, CCIPR1_REG) argument
94 #define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG) argument
96 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR3_REG) argument
[all …]
Dstm32f0_clock.h55 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
70 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG) argument
71 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG) argument
72 #define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG) argument
73 #define USB_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 7, CFGR3_REG) argument
74 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG) argument
75 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG) argument
77 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) argument
80 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG) argument
81 #define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG) argument
Dstm32l0_clock.h56 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
70 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) argument
71 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) argument
72 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) argument
73 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) argument
74 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) argument
75 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) argument
76 #define HSI48_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 26, CCIPR_REG) argument
78 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CSR_REG) argument
Dstm32c0_clock.h54 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
71 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) argument
72 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) argument
73 #define I2C2_I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG) argument
74 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG) argument
76 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CSR1_REG) argument
79 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG) argument
80 #define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG) argument
81 #define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x7, 16, CFGR1_REG) argument
82 #define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 20, CFGR1_REG) argument
/Zephyr-latest/lib/net_buf/
Dbuf_simple.c76 uint8_t *net_buf_simple_add_u8(struct net_buf_simple *buf, uint8_t val) in net_buf_simple_add_u8()
88 void net_buf_simple_add_le16(struct net_buf_simple *buf, uint16_t val) in net_buf_simple_add_le16()
95 void net_buf_simple_add_be16(struct net_buf_simple *buf, uint16_t val) in net_buf_simple_add_be16()
102 void net_buf_simple_add_le24(struct net_buf_simple *buf, uint32_t val) in net_buf_simple_add_le24()
109 void net_buf_simple_add_be24(struct net_buf_simple *buf, uint32_t val) in net_buf_simple_add_be24()
116 void net_buf_simple_add_le32(struct net_buf_simple *buf, uint32_t val) in net_buf_simple_add_le32()
123 void net_buf_simple_add_be32(struct net_buf_simple *buf, uint32_t val) in net_buf_simple_add_be32()
130 void net_buf_simple_add_le40(struct net_buf_simple *buf, uint64_t val) in net_buf_simple_add_le40()
137 void net_buf_simple_add_be40(struct net_buf_simple *buf, uint64_t val) in net_buf_simple_add_be40()
144 void net_buf_simple_add_le48(struct net_buf_simple *buf, uint64_t val) in net_buf_simple_add_le48()
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/dma/
Dgd32_dma.h13 #define GD32_DMA_CH_CFG_DIRECTION(val) ((val & 0x3) << 6) argument
19 #define GD32_DMA_CH_CFG_PERIPH_ADDR_INC(val) ((val & 0x1) << 9) argument
24 #define GD32_DMA_CH_CFG_MEMORY_ADDR_INC(val) ((val & 0x1) << 10) argument
29 #define GD32_DMA_CH_CFG_PERIPH_WIDTH(val) ((val & 0x3) << 11) argument
35 #define GD32_DMA_CH_CFG_MEMORY_WIDTH(val) ((val & 0x3) << 13) argument
41 #define GD32_DMA_CH_CFG_PERIPH_INC_FIXED(val) ((val & 0x1) << 15) argument
44 #define GD32_DMA_CH_CFG_PRIORITY(val) ((val & 0x3) << 16) argument
Dstm32_dma.h14 #define STM32_DMA_CH_CFG_MODE(val) ((val & 0x1) << 5) argument
19 #define STM32_DMA_CH_CFG_DIRECTION(val) ((val & 0x3) << 6) argument
26 #define STM32_DMA_CH_CFG_PERIPH_ADDR_INC(val) ((val & 0x1) << 9) argument
31 #define STM32_DMA_CH_CFG_MEM_ADDR_INC(val) ((val & 0x1) << 10) argument
36 #define STM32_DMA_CH_CFG_PERIPH_WIDTH(val) ((val & 0x3) << 11) argument
42 #define STM32_DMA_CH_CFG_MEM_WIDTH(val) ((val & 0x3) << 13) argument
48 #define STM32_DMA_CH_CFG_PERIPH_INC_FIXED(val) ((val & 0x1) << 15) argument
53 #define STM32_DMA_CH_CFG_PRIORITY(val) ((val & 0x3) << 16) argument
/Zephyr-latest/tests/kernel/common/src/
Dbyteorder.c79 uint64_t val = 0xf0e1d2c3b4a59687, tmp; in ZTEST() local
98 uint64_t val = 0xf0e1d2c3b4a59687; in ZTEST() local
118 uint64_t val = 0xf0e1d2c3b4, tmp; in ZTEST() local
135 uint64_t val = 0xf0e1d2c3b4; in ZTEST() local
152 uint64_t val = 0xf0e1d2c3b4a5, tmp; in ZTEST() local
171 uint64_t val = 0xf0e1d2c3b4a5; in ZTEST() local
190 uint32_t val = 0xf0e1d2c3, tmp; in ZTEST() local
209 uint64_t val = 0xf0e1d2c3; in ZTEST() local
229 uint32_t val = 0xf0e1d2, tmp; in ZTEST() local
248 uint64_t val = 0xf0e1d2; in ZTEST() local
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/Zephyr-latest/subsys/shell/
Dshell_ops.h58 static inline bool z_flag_insert_mode_set(const struct shell *sh, bool val) in z_flag_insert_mode_set()
71 static inline bool z_flag_use_colors_set(const struct shell *sh, bool val) in z_flag_use_colors_set()
84 static inline bool z_flag_use_vt100_set(const struct shell *sh, bool val) in z_flag_use_vt100_set()
97 static inline bool z_flag_echo_set(const struct shell *sh, bool val) in z_flag_echo_set()
110 static inline bool z_flag_obscure_set(const struct shell *sh, bool val) in z_flag_obscure_set()
123 static inline bool z_flag_processing_set(const struct shell *sh, bool val) in z_flag_processing_set()
136 static inline bool z_flag_tx_rdy_set(const struct shell *sh, bool val) in z_flag_tx_rdy_set()
149 static inline bool z_flag_mode_delete_set(const struct shell *sh, bool val) in z_flag_mode_delete_set()
162 static inline bool z_flag_history_exit_set(const struct shell *sh, bool val) in z_flag_history_exit_set()
175 static inline bool z_flag_cmd_ctx_set(const struct shell *sh, bool val) in z_flag_cmd_ctx_set()
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/Zephyr-latest/subsys/bluetooth/mesh/
Dheartbeat.h7 static inline uint16_t bt_mesh_hb_pwr2(uint8_t val) in bt_mesh_hb_pwr2()
18 static inline uint8_t bt_mesh_hb_log(uint32_t val) in bt_mesh_hb_log()

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