Home
last modified time | relevance | path

Searched refs:IMX_GPC_BASE (Results 1 – 10 of 10) sorted by relevance

/trusted-firmware-a-latest/plat/imx/imx8m/imx8mm/
Dgpc.c140 mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
143 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
146 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) { in imx_gpc_pm_domain_enable()
163 mmio_clrbits_32(IMX_GPC_BASE + GPU2D_PGC, 0x1); in imx_gpc_pm_domain_enable()
165 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU2D_PWR_REQ); in imx_gpc_pm_domain_enable()
168 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & GPU2D_PWR_REQ) { in imx_gpc_pm_domain_enable()
175 mmio_clrbits_32(IMX_GPC_BASE + GPU3D_PGC, 0x1); in imx_gpc_pm_domain_enable()
177 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU3D_PWR_REQ); in imx_gpc_pm_domain_enable()
180 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & GPU3D_PWR_REQ) { in imx_gpc_pm_domain_enable()
211 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
[all …]
/trusted-firmware-a-latest/plat/imx/imx8m/imx8mn/
Dgpc.c78 mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
81 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
84 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) { in imx_gpc_pm_domain_enable()
100 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
103 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { in imx_gpc_pm_domain_enable()
118 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
121 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { in imx_gpc_pm_domain_enable()
129 mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
132 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
135 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) { in imx_gpc_pm_domain_enable()
[all …]
/trusted-firmware-a-latest/plat/imx/imx8m/
Dgpc_common.c56 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); in imx_set_cpu_pwr_off()
61 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_off()
69 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); in imx_set_cpu_pwr_on()
76 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_on()
78 mmio_setbits_32(IMX_GPC_BASE + CPU_PGC_UP_TRG, (1 << core_id)); in imx_set_cpu_pwr_on()
81 while ((mmio_read_32(IMX_GPC_BASE + CPU_PGC_UP_TRG) & (1 << core_id)) != 0) in imx_set_cpu_pwr_on()
85 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_on()
96 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
99 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
102 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
[all …]
/trusted-firmware-a-latest/plat/imx/imx8m/imx8mq/
Dgpc.c37 IMX_GPC_BASE + IMR1_CORE0_A53,
38 IMX_GPC_BASE + IMR1_CORE1_A53,
39 IMX_GPC_BASE + IMR1_CORE2_A53,
40 IMX_GPC_BASE + IMR1_CORE3_A53,
41 IMX_GPC_BASE + IMR1_CORE0_M4,
222 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_pwr_off()
228 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_off()
238 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
241 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
244 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
[all …]
/trusted-firmware-a-latest/plat/imx/imx8m/imx8mp/
Dgpc.c205 mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
208 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
211 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) in imx_gpc_pm_domain_enable()
236 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
239 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) in imx_gpc_pm_domain_enable()
261 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
264 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) in imx_gpc_pm_domain_enable()
269 mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
280 mmio_write_32(IMX_GPC_BASE + PU_PGC_DN_TRG, VPU_G1_PWR_REQ | in imx_gpc_pm_domain_enable()
283 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & (VPU_G1_PWR_REQ | in imx_gpc_pm_domain_enable()
[all …]
/trusted-firmware-a-latest/plat/imx/imx8m/ddr/
Ddram_retention.c104 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, DDRMIX_ADB400_SYNC); in dram_enter_retention()
105 while (mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & DDRMIX_ADB400_ACK) in dram_enter_retention()
107 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, DDRMIX_ADB400_SYNC); in dram_enter_retention()
116 mmio_setbits_32(IMX_GPC_BASE + DDRMIX_PGC, 1); in dram_enter_retention()
117 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, DDRMIX_PWR_REQ); in dram_enter_retention()
142 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, DDRMIX_PWR_REQ); in dram_exit_retention()
/trusted-firmware-a-latest/plat/imx/imx8m/imx8mq/include/
Dplatform_def.h74 #define IMX_GPC_BASE U(0x303a0000) macro
/trusted-firmware-a-latest/plat/imx/imx8m/imx8mm/include/
Dplatform_def.h100 #define IMX_GPC_BASE U(0x303a0000) macro
/trusted-firmware-a-latest/plat/imx/imx8m/imx8mn/include/
Dplatform_def.h83 #define IMX_GPC_BASE U(0x303a0000) macro
/trusted-firmware-a-latest/plat/imx/imx8m/imx8mp/include/
Dplatform_def.h102 #define IMX_GPC_BASE U(0x303a0000) macro