Lines Matching refs:IMX_GPC_BASE
140 mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
143 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
146 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) { in imx_gpc_pm_domain_enable()
163 mmio_clrbits_32(IMX_GPC_BASE + GPU2D_PGC, 0x1); in imx_gpc_pm_domain_enable()
165 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU2D_PWR_REQ); in imx_gpc_pm_domain_enable()
168 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & GPU2D_PWR_REQ) { in imx_gpc_pm_domain_enable()
175 mmio_clrbits_32(IMX_GPC_BASE + GPU3D_PGC, 0x1); in imx_gpc_pm_domain_enable()
177 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU3D_PWR_REQ); in imx_gpc_pm_domain_enable()
180 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & GPU3D_PWR_REQ) { in imx_gpc_pm_domain_enable()
211 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
214 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { in imx_gpc_pm_domain_enable()
221 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU2D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
224 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU2D_ADB400_ACK)) { in imx_gpc_pm_domain_enable()
229 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU3D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
232 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU3D_ADB400_ACK)) { in imx_gpc_pm_domain_enable()
245 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU2D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
248 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU2D_ADB400_ACK)) { in imx_gpc_pm_domain_enable()
252 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU3D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
255 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU3D_ADB400_ACK)) { in imx_gpc_pm_domain_enable()
263 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
266 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { in imx_gpc_pm_domain_enable()
273 mmio_setbits_32(IMX_GPC_BASE + GPU2D_PGC, 0x1); in imx_gpc_pm_domain_enable()
275 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU2D_PWR_REQ); in imx_gpc_pm_domain_enable()
278 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & GPU2D_PWR_REQ) { in imx_gpc_pm_domain_enable()
283 mmio_setbits_32(IMX_GPC_BASE + GPU3D_PGC, 0x1); in imx_gpc_pm_domain_enable()
285 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU3D_PWR_REQ); in imx_gpc_pm_domain_enable()
288 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & GPU3D_PWR_REQ) { in imx_gpc_pm_domain_enable()
296 mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); in imx_gpc_pm_domain_enable()
299 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable()
302 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) { in imx_gpc_pm_domain_enable()
316 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); in imx_gpc_init()
317 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); in imx_gpc_init()
318 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0); in imx_gpc_init()
319 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); in imx_gpc_init()
320 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); in imx_gpc_init()
323 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); in imx_gpc_init()
328 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); in imx_gpc_init()
331 mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING | in imx_gpc_init()
335 mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xffff); in imx_gpc_init()
344 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x81); in imx_gpc_init()
345 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x81); in imx_gpc_init()
346 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x81); in imx_gpc_init()
347 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x81); in imx_gpc_init()
348 mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x81); in imx_gpc_init()
349 mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, in imx_gpc_init()
353 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, in imx_gpc_init()
357 val = mmio_read_32(IMX_GPC_BASE + SLPCR); in imx_gpc_init()
366 mmio_write_32(IMX_GPC_BASE + SLPCR, val); in imx_gpc_init()