78 			mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);  in imx_gpc_pm_domain_enable()
81 			mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req);  in imx_gpc_pm_domain_enable()
84 			while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) {  in imx_gpc_pm_domain_enable()
100 			mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync);  in imx_gpc_pm_domain_enable()
103 			while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) {  in imx_gpc_pm_domain_enable()
118 			mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync);  in imx_gpc_pm_domain_enable()
121 			while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) {  in imx_gpc_pm_domain_enable()
129 			mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);  in imx_gpc_pm_domain_enable()
132 			mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req);  in imx_gpc_pm_domain_enable()
135 			while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) {  in imx_gpc_pm_domain_enable()
149 		mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0);  in imx_gpc_init()
150 		mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0);  in imx_gpc_init()
151 		mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0);  in imx_gpc_init()
152 		mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0);  in imx_gpc_init()
153 		mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0);  in imx_gpc_init()
156 	val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);  in imx_gpc_init()
161 	mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);  in imx_gpc_init()
164 	mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING |  in imx_gpc_init()
168 	mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xffff);  in imx_gpc_init()
177 	mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x401);  in imx_gpc_init()
178 	mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x401);  in imx_gpc_init()
179 	mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x401);  in imx_gpc_init()
180 	mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x401);  in imx_gpc_init()
181 	mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x401);  in imx_gpc_init()
182 	mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,  in imx_gpc_init()
186 	mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53,  in imx_gpc_init()
190 	val = mmio_read_32(IMX_GPC_BASE + SLPCR);  in imx_gpc_init()
199 	mmio_write_32(IMX_GPC_BASE + SLPCR, val);  in imx_gpc_init()