205 		mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);  in imx_gpc_pm_domain_enable()
208 		mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req);  in imx_gpc_pm_domain_enable()
211 		while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req)  in imx_gpc_pm_domain_enable()
236 			mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync);  in imx_gpc_pm_domain_enable()
239 			while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack))  in imx_gpc_pm_domain_enable()
261 			mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync);  in imx_gpc_pm_domain_enable()
264 			while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack))  in imx_gpc_pm_domain_enable()
269 		mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);  in imx_gpc_pm_domain_enable()
280 			mmio_write_32(IMX_GPC_BASE + PU_PGC_DN_TRG, VPU_G1_PWR_REQ |  in imx_gpc_pm_domain_enable()
283 			while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & (VPU_G1_PWR_REQ |  in imx_gpc_pm_domain_enable()
289 		mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req);  in imx_gpc_pm_domain_enable()
292 		while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req)  in imx_gpc_pm_domain_enable()
316 		mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0);  in imx_gpc_init()
317 		mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0);  in imx_gpc_init()
318 		mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0);  in imx_gpc_init()
319 		mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0);  in imx_gpc_init()
320 		mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0);  in imx_gpc_init()
323 	val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);  in imx_gpc_init()
328 	mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);  in imx_gpc_init()
331 	mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING |  in imx_gpc_init()
335 	mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0x3fffff);  in imx_gpc_init()
344 	mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x401);  in imx_gpc_init()
345 	mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x401);  in imx_gpc_init()
346 	mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x401);  in imx_gpc_init()
347 	mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x401);  in imx_gpc_init()
348 	mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x401);  in imx_gpc_init()
349 	mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,  in imx_gpc_init()
353 	mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53,  in imx_gpc_init()
357 	val = mmio_read_32(IMX_GPC_BASE + SLPCR);  in imx_gpc_init()
367 	mmio_write_32(IMX_GPC_BASE + SLPCR, val);  in imx_gpc_init()