37 	IMX_GPC_BASE + IMR1_CORE0_A53,
38 	IMX_GPC_BASE + IMR1_CORE1_A53,
39 	IMX_GPC_BASE + IMR1_CORE2_A53,
40 	IMX_GPC_BASE + IMR1_CORE3_A53,
41 	IMX_GPC_BASE + IMR1_CORE0_M4,
222 	mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |  in imx_set_cpu_pwr_off()
228 	mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);  in imx_set_cpu_pwr_off()
238 		mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |  in imx_set_cpu_lpm()
241 		mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);  in imx_set_cpu_lpm()
244 		mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |  in imx_set_cpu_lpm()
247 		mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);  in imx_set_cpu_lpm()
257 		mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), SLT_PLAT_PDN);  in imx_pup_pdn_slot_config()
259 		mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(1), SLT_PLAT_PUP);  in imx_pup_pdn_slot_config()
261 		mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(2), SLT_COREx_PUP(last_core));  in imx_pup_pdn_slot_config()
263 		mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF,  in imx_pup_pdn_slot_config()
266 		mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), 0xFFFFFFFF);  in imx_pup_pdn_slot_config()
267 		mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(1), 0xFFFFFFFF);  in imx_pup_pdn_slot_config()
268 		mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(2), 0xFFFFFFFF);  in imx_pup_pdn_slot_config()
269 		mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF,  in imx_pup_pdn_slot_config()
279 		val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);  in imx_set_cluster_powerdown()
282 		mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);  in imx_set_cluster_powerdown()
285 		mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_STOP);  in imx_set_cluster_powerdown()
288 		val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD);  in imx_set_cluster_powerdown()
293 		mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val);  in imx_set_cluster_powerdown()
298 		mmio_setbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1);  in imx_set_cluster_powerdown()
301 		mmio_clrbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1);  in imx_set_cluster_powerdown()
306 		val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);  in imx_set_cluster_powerdown()
309 		mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);  in imx_set_cluster_powerdown()
312 		mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_MASK);  in imx_set_cluster_powerdown()
315 		val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD);  in imx_set_cluster_powerdown()
319 		mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val);  in imx_set_cluster_powerdown()
408 	val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);  in imx_gpc_init()
412 	mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);  in imx_gpc_init()
415 	mmio_setbits_32(IMX_GPC_BASE + LPCR_M4, DSM_MODE_MASK);  in imx_gpc_init()
418 	mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xfffd);  in imx_gpc_init()
421 	mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,  in imx_gpc_init()
425 	mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_DUMMY_PUP_ACK |  in imx_gpc_init()
429 	mmio_clrbits_32(IMX_GPC_BASE + SLPCR, DSM_MODE_MASK);  in imx_gpc_init()