Searched refs:BIT (Results 1 – 25 of 318) sorted by relevance
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27 #define CCM_CCGR_SETTING0_DOM_CLK_RUN BIT(0)28 #define CCM_CCGR_SETTING0_DOM_CLK_RUN_WAIT BIT(1)29 #define CCM_CCGR_SETTING0_DOM_CLK_ALWAYS (BIT(1) | BIT(0))31 #define CCM_CCGR_SETTING1_DOM_CLK_RUN BIT(4)32 #define CCM_CCGR_SETTING1_DOM_CLK_RUN_WAIT BIT(5)33 #define CCM_CCGR_SETTING1_DOM_CLK_ALWAYS (BIT(5) | BIT(4))35 #define CCM_CCGR_SETTING2_DOM_CLK_RUN BIT(8)36 #define CCM_CCGR_SETTING2_DOM_CLK_RUN_WAIT BIT(9)37 #define CCM_CCGR_SETTING2_DOM_CLK_ALWAYS (BIT(9) | BIT(8))39 #define CCM_CCGR_SETTING3_DOM_CLK_RUN BIT(12)[all …]
26 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_ALT1_SD3_CD_B BIT(0)97 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT1_I2C1_SCL BIT(0)98 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT2_PMIC_READY BIT(1)99 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT3_ECSPI1_SS1 (BIT(1) | BIT(0))100 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT4_ENET2_1588_EVENT0_IN BIT(3)101 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT5_GPIO4_IO0 (BIT(2) | BIT(0))102 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT6_ENET1_MDIO (BIT(2) | BIT(1))103 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_SION BIT(3)107 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT1_I2C1_SDA BIT(0)108 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT2_SAI3_MCLK BIT(1)[all …]
238 #define RCC_TZCR_TZEN BIT(0)239 #define RCC_TZCR_MCKPROT BIT(1)242 #define RCC_OCENSETR_HSION BIT(0)243 #define RCC_OCENSETR_HSIKERON BIT(1)244 #define RCC_OCENSETR_CSION BIT(4)245 #define RCC_OCENSETR_CSIKERON BIT(5)246 #define RCC_OCENSETR_DIGBYP BIT(7)247 #define RCC_OCENSETR_HSEON BIT(8)248 #define RCC_OCENSETR_HSEKERON BIT(9)249 #define RCC_OCENSETR_HSEBYP BIT(10)[all …]
215 #define RCC_SECCFGR_HSISEC BIT(0)216 #define RCC_SECCFGR_CSISEC BIT(1)217 #define RCC_SECCFGR_HSESEC BIT(2)218 #define RCC_SECCFGR_LSISEC BIT(3)219 #define RCC_SECCFGR_LSESEC BIT(4)220 #define RCC_SECCFGR_PLL12SEC BIT(8)221 #define RCC_SECCFGR_PLL3SEC BIT(9)222 #define RCC_SECCFGR_PLL4SEC BIT(10)223 #define RCC_SECCFGR_MPUSEC BIT(11)224 #define RCC_SECCFGR_AXISEC BIT(12)[all …]
26 #define USART_CR1_UE BIT(0)27 #define USART_CR1_UESM BIT(1)28 #define USART_CR1_RE BIT(2)29 #define USART_CR1_TE BIT(3)30 #define USART_CR1_IDLEIE BIT(4)31 #define USART_CR1_RXNEIE BIT(5)32 #define USART_CR1_TCIE BIT(6)33 #define USART_CR1_TXEIE BIT(7)34 #define USART_CR1_PEIE BIT(8)35 #define USART_CR1_PS BIT(9)[all …]
731 #define RCC_R0CIDCFGR_CFEN BIT(0)732 #define RCC_R0CIDCFGR_SEM_EN BIT(1)739 #define RCC_R0SEMCR_SEM_MUTEX BIT(0)744 #define RCC_R1CIDCFGR_CFEN BIT(0)745 #define RCC_R1CIDCFGR_SEM_EN BIT(1)752 #define RCC_R1SEMCR_SEM_MUTEX BIT(0)757 #define RCC_R2CIDCFGR_CFEN BIT(0)758 #define RCC_R2CIDCFGR_SEM_EN BIT(1)765 #define RCC_R2SEMCR_SEM_MUTEX BIT(0)770 #define RCC_R3CIDCFGR_CFEN BIT(0)[all …]
15 #define I2C_CR1_PE BIT(0)16 #define I2C_CR1_TXIE BIT(1)17 #define I2C_CR1_RXIE BIT(2)18 #define I2C_CR1_ADDRIE BIT(3)19 #define I2C_CR1_NACKIE BIT(4)20 #define I2C_CR1_STOPIE BIT(5)21 #define I2C_CR1_TCIE BIT(6)22 #define I2C_CR1_ERRIE BIT(7)24 #define I2C_CR1_ANFOFF BIT(12)25 #define I2C_CR1_SWRST BIT(13)[all …]
12 #define IMX_UART_RXD_CHARRDY BIT(15)13 #define IMX_UART_RXD_ERR BIT(14)14 #define IMX_UART_RXD_OVERRUN BIT(13)15 #define IMX_UART_RXD_FRMERR BIT(12)16 #define IMX_UART_RXD_BRK BIT(11)17 #define IMX_UART_RXD_PRERR BIT(10)22 #define IMX_UART_CR1_ADEN BIT(15)23 #define IMX_UART_CR1_ADBR BIT(14)24 #define IMX_UART_CR1_TRDYEN BIT(13)25 #define IMX_UART_CR1_IDEN BIT(12)[all …]
16 #define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21)17 #define GPSR0_DU_EXVSYNC_DU_VSYNC BIT(20)18 #define GPSR0_DU_EXHSYNC_DU_HSYNC BIT(19)19 #define GPSR0_DU_DOTCLKOUT BIT(18)20 #define GPSR0_DU_DB7 BIT(17)21 #define GPSR0_DU_DB6 BIT(16)22 #define GPSR0_DU_DB5 BIT(15)23 #define GPSR0_DU_DB4 BIT(14)24 #define GPSR0_DU_DB3 BIT(13)25 #define GPSR0_DU_DB2 BIT(12)[all …]
39 #define MASK_DSM_TRIGGER_A53 BIT(31)40 #define IRQ_SRC_A53_WUP BIT(30)42 #define IRQ_SRC_C1 BIT(29)43 #define IRQ_SRC_C0 BIT(28)44 #define IRQ_SRC_C3 BIT(23)45 #define IRQ_SRC_C2 BIT(22)46 #define CPU_CLOCK_ON_LPM BIT(14)47 #define A53_CLK_ON_LPM BIT(14)48 #define MASTER0_LPM_HSK BIT(6)49 #define MASTER1_LPM_HSK BIT(7)[all …]
37 #define MASK_DSM_TRIGGER_A53 BIT(31)38 #define IRQ_SRC_A53_WUP BIT(30)40 #define IRQ_SRC_C1 BIT(29)41 #define IRQ_SRC_C0 BIT(28)42 #define IRQ_SRC_C3 BIT(23)43 #define IRQ_SRC_C2 BIT(22)44 #define CPU_CLOCK_ON_LPM BIT(14)45 #define A53_CLK_ON_LPM BIT(14)46 #define MASTER0_LPM_HSK BIT(6)47 #define MASTER1_LPM_HSK BIT(7)[all …]
23 #define DRDU2_U2PLL_LOCK BIT(6U)24 #define DRDU2_U2PLL_RESETB BIT(5U)27 #define DRDU2_U2PLL_SUSPEND_EN BIT(0U)30 #define DRDU2_U2IDDQ BIT(30U)31 #define DRDU2_U2SOFT_RST_N BIT(29U)32 #define DRDU2_U2PHY_ON_FLAG BIT(22U)35 #define DRDU2_U2PHY_RESETB BIT(5U)36 #define DRDU2_U2PHY_ISO BIT(4U)37 #define DRDU2_U2AFE_BG_PWRDWNB BIT(3U)38 #define DRDU2_U2AFE_PLL_PWRDWNB BIT(2U)[all …]
34 #define XFERTYPE_DPSEL BIT(21)35 #define XFERTYPE_CICEN BIT(20)36 #define XFERTYPE_CCCEN BIT(19)37 #define XFERTYPE_RSPTYP_136 BIT(16)38 #define XFERTYPE_RSPTYP_48 BIT(17)39 #define XFERTYPE_RSPTYP_48_BUSY (BIT(16) | BIT(17))42 #define PSTATE_DAT0 BIT(24)43 #define PSTATE_DLA BIT(2)44 #define PSTATE_CDIHB BIT(1)45 #define PSTATE_CIHB BIT(0)[all …]
17 #define FLAGOUTCLR0_F2SDRAM0_ENABLE (BIT(8))18 #define FLAGOUTSETCLR_F2SDRAM0_ENABLE (BIT(1))19 #define FLAGOUTSETCLR_F2SDRAM1_ENABLE (BIT(4))20 #define FLAGOUTSETCLR_F2SDRAM2_ENABLE (BIT(7))22 #define FLAGOUTSETCLR_F2SDRAM0_IDLEREQ (BIT(0))23 #define FLAGOUTSETCLR_F2SDRAM1_IDLEREQ (BIT(3))24 #define FLAGOUTSETCLR_F2SDRAM2_IDLEREQ (BIT(6))25 #define FLAGINSTATUS_F2SDRAM0_IDLEACK (BIT(1))26 #define FLAGINSTATUS_F2SDRAM1_IDLEACK (BIT(5))27 #define FLAGINSTATUS_F2SDRAM2_IDLEACK (BIT(9))[all …]
23 #define MP2_CPU0_STANDBYWFE BIT(4)24 #define MP2_CPU1_STANDBYWFE BIT(5)30 #define sw_spark_en BIT(0)31 #define sw_no_wait_for_q_channel BIT(1)32 #define sw_fsm_override BIT(2)33 #define sw_logic_pre1_pdb BIT(3)34 #define sw_logic_pre2_pdb BIT(4)35 #define sw_logic_pdb BIT(5)36 #define sw_iso BIT(6)38 #define sw_sram_isointb BIT(13)[all …]
11 #define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK BIT(17)12 #define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(15) | BIT(16) | BIT(17) | \13 BIT(18) | BIT(21))14 #define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK (BIT(15) | BIT(16) | BIT(17) | BIT(18))15 #define MP_CPUSYS_TOP_ADB_DCM_REG0_ON BIT(17)16 #define MP_CPUSYS_TOP_ADB_DCM_REG1_ON (BIT(15) | BIT(16) | BIT(17) | \17 BIT(18) | BIT(21))18 #define MP_CPUSYS_TOP_ADB_DCM_REG2_ON (BIT(15) | BIT(16) | BIT(17) | BIT(18))70 #define MP_CPUSYS_TOP_APB_DCM_REG0_MASK BIT(5)71 #define MP_CPUSYS_TOP_APB_DCM_REG1_MASK BIT(8)[all …]
11 #define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK (BIT(16) | \12 BIT(17) | \13 BIT(18) | \14 BIT(21))15 #define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(16) | \16 BIT(17) | \17 BIT(18))18 #define MP_CPUSYS_TOP_ADB_DCM_REG0_ON (BIT(16) | \19 BIT(17) | \20 BIT(18) | \[all …]
59 val = (BIT(IOPAD_CTRL6_SDIO0_DATA7_SRC_R) | in emmc_soft_reset()60 BIT(IOPAD_CTRL6_SDIO0_DATA7_HYS_R) | in emmc_soft_reset()61 BIT(IOPAD_CTRL6_SDIO0_DATA7_DRIVE_R) | in emmc_soft_reset()62 BIT(IOPAD_CTRL6_SDIO0_DATA6_SRC_R) | in emmc_soft_reset()63 BIT(IOPAD_CTRL6_SDIO0_DATA6_HYS_R) | in emmc_soft_reset()64 BIT(IOPAD_CTRL6_SDIO0_DATA6_DRIVE_R)); in emmc_soft_reset()68 val = (BIT(IOPAD_CTRL5_SDIO0_DATA3_SRC_R) | in emmc_soft_reset()69 BIT(IOPAD_CTRL5_SDIO0_DATA3_HYS_R) | in emmc_soft_reset()70 BIT(IOPAD_CTRL5_SDIO0_DATA3_DRIVE_R) | in emmc_soft_reset()71 BIT(IOPAD_CTRL5_SDIO0_DATA4_SRC_R) | in emmc_soft_reset()[all …]
17 #define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT BIT(0)19 #define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT BIT(4)21 #define COMPHY_SELECTOR_USB3_PHY_SEL_BIT BIT(8)46 #define PU_IVREF_BIT BIT(15)47 #define PU_PLL_BIT BIT(14)48 #define PU_RX_BIT BIT(13)49 #define PU_TX_BIT BIT(12)50 #define PU_TX_INTP_BIT BIT(11)51 #define PU_DFE_BIT BIT(10)52 #define RESET_DTL_RX_BIT BIT(9)[all …]
14 #define GPSR0_SDA4 BIT(17)15 #define GPSR0_SCL4 BIT(16)16 #define GPSR0_D15 BIT(15)17 #define GPSR0_D14 BIT(14)18 #define GPSR0_D13 BIT(13)19 #define GPSR0_D12 BIT(12)20 #define GPSR0_D11 BIT(11)21 #define GPSR0_D10 BIT(10)22 #define GPSR0_D9 BIT(9)23 #define GPSR0_D8 BIT(8)[all …]
17 #define GPSR0_SDA4 BIT(17)18 #define GPSR0_SCL4 BIT(16)19 #define GPSR0_D15 BIT(15)20 #define GPSR0_D14 BIT(14)21 #define GPSR0_D13 BIT(13)22 #define GPSR0_D12 BIT(12)23 #define GPSR0_D11 BIT(11)24 #define GPSR0_D10 BIT(10)25 #define GPSR0_D9 BIT(9)26 #define GPSR0_D8 BIT(8)[all …]
