Lines Matching refs:BIT
11 #define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK (BIT(16) | \
12 BIT(17) | \
13 BIT(18) | \
14 BIT(21))
15 #define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(16) | \
16 BIT(17) | \
17 BIT(18))
18 #define MP_CPUSYS_TOP_ADB_DCM_REG0_ON (BIT(16) | \
19 BIT(17) | \
20 BIT(18) | \
21 BIT(21))
22 #define MP_CPUSYS_TOP_ADB_DCM_REG1_ON (BIT(16) | \
23 BIT(17) | \
24 BIT(18))
68 #define MP_CPUSYS_TOP_APB_DCM_REG0_MASK (BIT(5))
69 #define MP_CPUSYS_TOP_APB_DCM_REG1_MASK (BIT(8))
70 #define MP_CPUSYS_TOP_APB_DCM_REG2_MASK (BIT(16))
71 #define MP_CPUSYS_TOP_APB_DCM_REG0_ON (BIT(5))
72 #define MP_CPUSYS_TOP_APB_DCM_REG1_ON (BIT(8))
73 #define MP_CPUSYS_TOP_APB_DCM_REG2_ON (BIT(16))
122 #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK (BIT(11) | \
123 BIT(24) | \
124 BIT(25))
125 #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON (BIT(11) | \
126 BIT(24) | \
127 BIT(25))
158 #define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK (BIT(0))
159 #define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON (BIT(0))
188 #define MP_CPUSYS_TOP_CPUBIU_DBG_CG_REG0_MASK (BIT(0))
190 #define MP_CPUSYS_TOP_CPUBIU_DBG_CG_REG0_OFF (BIT(0))
248 #define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK (BIT(11) | \
249 BIT(24) | \
250 BIT(25))
251 #define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON (BIT(11) | \
252 BIT(24) | \
253 BIT(25))
284 #define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK (BIT(11) | \
285 BIT(24) | \
286 BIT(25))
287 #define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON (BIT(11) | \
288 BIT(24) | \
289 BIT(25))
320 #define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK (BIT(4))
321 #define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON (BIT(4))
350 #define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK (BIT(31))
351 #define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON (BIT(31))
380 #define MP_CPUSYS_TOP_MISC_DCM_REG0_MASK (BIT(0) | \
381 BIT(1) | \
382 BIT(2) | \
383 BIT(3) | \
384 BIT(4))
385 #define MP_CPUSYS_TOP_MISC_DCM_REG0_ON (BIT(0) | \
386 BIT(1) | \
387 BIT(2) | \
388 BIT(3) | \
389 BIT(4))
422 #define MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK (BIT(0) | \
423 BIT(1) | \
424 BIT(2) | \
425 BIT(3))
426 #define MP_CPUSYS_TOP_MP0_QDCM_REG0_ON (BIT(0) | \
427 BIT(1) | \
428 BIT(2) | \
429 BIT(3))
461 #define CPCCFG_REG_EMI_WFIFO_REG0_MASK (BIT(0) | BIT(2))
462 #define CPCCFG_REG_EMI_WFIFO_REG0_ON (BIT(0) | BIT(2))