Lines Matching refs:BIT
23 #define DRDU2_U2PLL_LOCK BIT(6U)
24 #define DRDU2_U2PLL_RESETB BIT(5U)
27 #define DRDU2_U2PLL_SUSPEND_EN BIT(0U)
30 #define DRDU2_U2IDDQ BIT(30U)
31 #define DRDU2_U2SOFT_RST_N BIT(29U)
32 #define DRDU2_U2PHY_ON_FLAG BIT(22U)
35 #define DRDU2_U2PHY_RESETB BIT(5U)
36 #define DRDU2_U2PHY_ISO BIT(4U)
37 #define DRDU2_U2AFE_BG_PWRDWNB BIT(3U)
38 #define DRDU2_U2AFE_PLL_PWRDWNB BIT(2U)
39 #define DRDU2_U2AFE_LDO_PWRDWNB BIT(1U)
40 #define DRDU2_U2CTRL_CORERDY BIT(0U)
43 #define DRDU2_FORCE_HOST_MODE BIT(5U)
44 #define DRDU2_FORCE_DEVICE_MODE BIT(4U)
49 #define DRDU2_U2PHY_DFE_SWITCH_PWROKIN_I BIT(2U)
50 #define DRDU2_U2PHY_DFE_SWITCH_PWRONIN_I BIT(1U)
53 #define DRDU2_BDC_AXI_SOFT_RST_N BIT(0U)
60 #define USB3H_U2PLL_LOCK BIT(6U)
61 #define USB3H_U2PLL_RESETB BIT(5U)
69 #define USB3H_U2PHY_IDDQ BIT(29U)
70 #define USB3H_U2PHY_RESETB BIT(5U)
71 #define USB3H_U2PHY_ISO BIT(4U)
72 #define USB3H_U2AFE_BG_PWRDWNB BIT(3U)
73 #define USB3H_U2AFE_PLL_PWRDWNB BIT(2U)
74 #define USB3H_U2AFE_LDO_PWRDWNB BIT(1U)
75 #define USB3H_U2CTRL_CORERDY BIT(0U)
78 #define USB3H_U3SOFT_RST_N BIT(30U)
79 #define USB3H_U3MDIO_RESETB_I BIT(29U)
80 #define USB3H_U3POR_RESET_I BIT(28U)
83 #define USB3H_U3PHY_RESETB BIT(1U)
88 #define USB3H_U3PLL_SS_LOCK BIT(3U)
89 #define USB3H_U3PLL_SEQ_START BIT(2U)
90 #define USB3H_U3SSPLL_SUSPEND_EN BIT(1U)
91 #define USB3H_U3PLL_RESETB BIT(0U)
95 #define USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWROKIN BIT(11U)
96 #define USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWRONIN BIT(10U)
99 #define USB3H_XHC_AXI_SOFT_RST_N BIT(1U)
102 #define USB3H_DISABLE_USB30_P0 BIT(2U)
103 #define USB3H_DISABLE_EUSB_P1 BIT(1U)
104 #define USB3H_DISABLE_EUSB_P0 BIT(0U)
112 #define DRDU3_U2PLL_LOCK BIT(6U)
113 #define DRDU3_U2PLL_RESETB BIT(5U)
118 #define DRDU3_U2PHY_IDDQ BIT(29U)
119 #define DRDU3_U2PHY_ON_FLAG BIT(22U)
122 #define DRDU3_U2PHY_RESETB BIT(5U)
123 #define DRDU3_U2PHY_ISO BIT(4U)
124 #define DRDU3_U2AFE_BG_PWRDWNB BIT(3U)
125 #define DRDU3_U2AFE_PLL_PWRDWNB BIT(2U)
126 #define DRDU3_U2AFE_LDO_PWRDWNB BIT(1U)
127 #define DRDU3_U2CTRL_CORERDY BIT(0U)
130 #define DRDU3_U3XHC_SOFT_RST_N BIT(31U)
131 #define DRDU3_U3BDC_SOFT_RST_N BIT(30U)
132 #define DRDU3_U3MDIO_RESETB_I BIT(29U)
133 #define DRDU3_U3POR_RESET_I BIT(28U)
136 #define DRDU3_U3PHY_RESETB BIT(1U)
141 #define DRDU3_U3PLL_SS_LOCK BIT(3U)
142 #define DRDU3_U3PLL_SEQ_START BIT(2U)
143 #define DRDU3_U3SSPLL_SUSPEND_EN BIT(1U)
144 #define DRDU3_U3PLL_RESETB BIT(0U)
153 #define DRDU3_U2PHY_DFE_SWITCH_PWROKIN BIT(12U)
154 #define DRDU3_U2PHY_DFE_SWITCH_PWRONIN BIT(11U)
158 #define DRDU3_XHC_AXI_SOFT_RST_N BIT(1U)
159 #define DRDU3_BDC_AXI_SOFT_RST_N BIT(0U)
162 #define DRDU3_DISABLE_USB30_P0 BIT(2U)
163 #define DRDU3_DISABLE_EUSB_P1 BIT(1U)
164 #define DRDU3_DISABLE_EUSB_P0 BIT(0U)
211 #define AXI_DBG_CTRL_SSPHY_DRD_MODE_DISABLE BIT(12U)
214 #define USB3H_DBG_CTRL_SSPHY_DRD_MODE_DISABLE BIT(7U)