Searched refs:B1 (Results 1 – 25 of 38) sorted by relevance
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9 The u-blox NINA-B1 Evaluation Kit hardware is a Bluetooth28 .. figure:: img/EVK-NINA-B1.jpg30 EVK NINA-B132 More information about the NINA-B1 module and the EVK NINA-B133 can be found at `NINA-B1 product page`_ and34 `EVK-NINA-B1 product page`_.77 disabled. On the EVK-NINA-B1, these pins are81 See `EVK-NINA-B1 product page`_ and `NINA-B1 Data Sheet`_82 for a complete list of EVK NINA-B1 hardware features.105 numbering on the nRF52832 SoC. Please see the `NINA-B1 Data Sheet`_ for[all …]
9 The u-blox ANNA-B1 Evaluation Kit hardware is a Bluetooth low energy30 EVK ANNA-B132 More information about the ANNA-B1 module and the EVK-ANNA-B133 can be found at `ANNA-B1 product page`_ and34 `EVK-ANNA-B1 product page`_.75 See `EVK-ANNA-B1 product page`_ and `ANNA-B1 Data Sheet`_76 for a complete list of EVK ANNA-B1 hardware features.98 numbering on the nRF52832 SoC. Please see the `ANNA-B1 Data Sheet`_ for99 information on how to map ANNA-B1 pins to the pin numbering on the155 Note that the buttons on the EVK-ANNA-B1 are marked SW1 and SW2, which[all …]
3 ARM V2M Musca B110 on the V2M Musca B1 board. It provides support for the Musca B1 ARM Cortex-M3320 :alt: ARM V2M Musca B122 More information about the board can be found at the `V2M Musca B1 Website`_.27 ARM V2M MUSCA B1 provides the following hardware components:97 See the `V2M Musca B1 Website`_ for a complete list of V2M Musca board hardware106 Musca B1 is a Cortex-M33 based SoC and has 15 fixed exceptions and 77 IRQs.167 The ARM V2M Musca B1 Board has 4 GPIO controllers. These controllers are174 Mapping from the ARM V2M Musca B1 Board pins to GPIO controllers:208 For more details please refer to `Musca B1 Technical Reference Manual (TRM)`_.[all …]
12 * nRF21540 (P6) P0.08 RXD -> IMXRT1020-EVK (J17) D1 (GPIO B1 08) (TXD)13 * nRF21540 (P6) P0.07 CTS -> IMXRT1020-EVK (J19) D8 (GPIO B1 07) (RTS)14 * nRF21540 (P6) P0.06 TXD -> IMXRT1020-EVK (J17) D0 (GPIO B1 09) (RXD)15 * nRF21540 (P6) P0.05 RTS -> IMXRT1020-EVK (J17) D7 (GPIO B1 06) (CTS)
13 model = "u-blox EVK-ANNA-B1 NRF52832";30 /* ANNA-B1 GPIO_29 */35 /* ANNA-B1 GPIO_30 */40 /*ANNA-B1 GPIO_31 */62 /* EVK-ANNA-B1 SW1 button */68 /* EVK-ANNA-B1 SW2 button */
1 # u-blox EVK-ANNA-B1 board configuration
13 model = "u-blox EVK-NINA-B1 NRF52832";30 /* NINA-B1 GPIO_1 */35 /* NINA-B1 GPIO_7 */40 /*NINA-B1 GPIO_8 */62 /* EVK-NINA-B1 SW1 button */68 /* EVK-NINA-B1 SW2 button */
1 # u-blox EVK-NINA-B1 board configuration
22 On Musca B126 It can be built and executed on Musca B1 CPU 0 as follows:35 It can be built and executed on Musca B1 CPU 1 as follows:53 # This command is an example for Musca B1
14 ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA-B1
11 Enable Microchip's LAN8650/1 Rev.B0/B1 Internal PHYs and
20 .. |plusminus| unicode:: U+000B1 .. PLUS-MINUS SIGN
4 ignore=title-trailing-punctuation, T3, title-max-length, T1, body-hard-tab, B3, B145 # B1 = body-max-line-length
66 and B1 (Boot 1). The pins B0 and B1 are present in between logic 0 and 1 lines. The67 silk screen on the PCB reads BX- or BX+ to indicate 0 and 1 logic lines for B0 and B1
31 /* NINA-B1 GPIO_1 */41 /*NINA-B1 GPIO_8 */
45 - Two push-buttons: B1 (USER/blue) and B2 (RESET/black)81 - B1 (USER/blue) : PC13
227 * nRF21540 (P6) P0.08 RXD -> IMXRT1020-EVK (J17) D1 (GPIO B1 08) (TXD)228 * nRF21540 (P6) P0.07 CTS -> IMXRT1020-EVK (J19) D8 (GPIO B1 07) (RTS)229 * nRF21540 (P6) P0.06 TXD -> IMXRT1020-EVK (J17) D0 (GPIO B1 09) (RXD)230 * nRF21540 (P6) P0.05 RTS -> IMXRT1020-EVK (J17) D7 (GPIO B1 06) (CTS)
479 XCVR_TSM->TIMING19 -= B1(WU_OPTIM); /* sy_pd_filter_charge_en */ in hpmcal_disable()480 XCVR_TSM->TIMING24 -= B1(WU_OPTIM); /* sy_divn_cal_en */ in hpmcal_disable()481 XCVR_TSM->TIMING13 -= B1(WU_OPTIM); /* sy_vco_autotune_en */ in hpmcal_disable()487 XCVR_TSM->END_OF_SEQ -= B1(WU_OPTIM) + B0(WU_OPTIM); in hpmcal_disable()
57 label = "User B1";
