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/Zephyr-latest/soc/gaisler/leon3/
Dlinker.ld19 RAM (rwx) : ORIGIN = CONFIG_SRAM_BASE_ADDRESS, LENGTH = KB(CONFIG_SRAM_SIZE)
24 REGION_ALIAS("REGION_TEXT", RAM);
25 REGION_ALIAS("REGION_RODATA", RAM);
26 REGION_ALIAS("REGION_DATA_VMA", RAM);
27 REGION_ALIAS("REGION_DATA_LMA", RAM);
28 REGION_ALIAS("REGION_BSS", RAM);
30 #define ROMABLE_REGION RAM
31 #define RAMABLE_REGION RAM
/Zephyr-latest/soc/gaisler/gr716a/
Dlinker.ld18 * available on all systems. bootprom, RAM and SRAM are always available.
26 RAM (rw) : ORIGIN = 0x30000000, LENGTH = 64K
34 REGION_ALIAS("REGION_RODATA", RAM);
35 REGION_ALIAS("REGION_DATA_VMA", RAM);
36 REGION_ALIAS("REGION_DATA_LMA", RAM);
37 REGION_ALIAS("REGION_BSS", RAM);
39 #define ROMABLE_REGION RAM
40 #define RAMABLE_REGION RAM
/Zephyr-latest/snippets/ram-console/
DREADME.rst3 RAM Console Snippet (ram-console)
13 This snippet redirects console output to a RAM buffer. The RAM console
14 buffer is a global array located in RAM region by default, whose address
15 is unknown before building. The RAM console driver also supports using
16 a dedicated section for the RAM console buffer with prefined address.
18 How to enable RAM console buffer section
/Zephyr-latest/samples/net/zperf/
DKconfig7 bool "Relocate networking code into RAM"
10 Relocate networking code into RAM when running the zperf
12 RAM.
17 string "Networking code RAM location"
18 default "RAM"
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/
DKconfig.soc21 28k logic cells, 2.1Mb block RAM, 800 DSP slices, up to 100 I/O pins.
28 74k logic cells, 3.3Mb block RAM, 160 DSP slices, up to 150 I/O pins,
36 85k logic cells, 4.9Mb block RAM, 220 DSP slices, up to 200 I/O pins.
43 125k logic cells, 9.3Mb block RAM, 400 DSP slices, up to 250 I/O pins,
51 275k logic cells, 17.6Mb block RAM, 900 DSP slices, up to 362 I/O pins,
59 350k logic cells, 19.1Mb block RAM, 900 DSP slices, up to 362 I/O pins,
67 444k logic cells, 26.5Mb block RAM, 2020 DSP slices, up to 400 I/O pins,
/Zephyr-latest/samples/subsys/fs/fatfs_fstab/
Dfatfs_fstab.overlay14 mount-point = "/RAM:";
20 disk-name = "RAM";
/Zephyr-latest/dts/arm/nuvoton/
Dnpcx7m7fc.dtsi13 * Reallocate the last 64 KB of code RAM for use as data RAM
28 /* RAM space used by Booter */
/Zephyr-latest/boards/nxp/common/
Dsegger-ecc-systemview.rst15 supports ECC RAM. If the SEGGER tooling searches the ECC RAM space for the
16 control block a fault will occur, provided that ECC is enabled and the RAM
/Zephyr-latest/include/zephyr/arch/mips/
Dlinker.ld18 #define ROMABLE_REGION RAM
19 #define RAMABLE_REGION RAM
27 RAM (rwx) : ORIGIN = CONFIG_SRAM_BASE_ADDRESS, LENGTH = KB(CONFIG_SRAM_SIZE)
32 REGION_ALIAS("REGION_TEXT", RAM);
33 REGION_ALIAS("REGION_RODATA", RAM);
34 REGION_ALIAS("REGION_DATA_VMA", RAM);
35 REGION_ALIAS("REGION_DATA_LMA", RAM);
36 REGION_ALIAS("REGION_BSS", RAM);
/Zephyr-latest/drivers/disk/
DKconfig.ram5 bool "RAM Disk"
9 RAM buffer used to emulate storage disk.
/Zephyr-latest/drivers/retained_mem/
DKconfig.zephyr5 bool "Generic Zephyr RAM retained memory driver"
9 Enable driver for retained memory in RAM.
DKconfig.nrf13 bool "nRF RAM retention driver"
18 Enable driver for Nordic RAM retention.
/Zephyr-latest/samples/boards/nordic/system_off/
DREADME.rst13 RAM Retention
16 This sample can also demonstrate RAM retention.
20 RAM is configured to keep the containing section powered while in system-off mode.
/Zephyr-latest/samples/subsys/fs/format/
DREADME.rst15 * FAT file system on RAM disk
23 The RAM disk scenario is supported on the mimxrt1064_evk board.
24 To build the RAM disk sample, the configuration :file:`prj_ram.conf` needs to be used by setting
35 The RAM disk sample for the MIMXRT1064-EVK board can be built as follow:
/Zephyr-latest/samples/boards/st/power_mgmt/suspend_to_ram/
DREADME.rst2 :name: Suspend to RAM
5 Use suspend to RAM low power mode on STM32.
13 SPI loopback is also available but not yet implemented for Suspend To RAM PM
25 for LPTIM (which is disabled). The board shall also have RAM retention to be
/Zephyr-latest/drivers/bbram/
DKconfig5 bool "Battery-backed RAM (BBRAM) drivers"
7 Enable BBRAM (battery-backed RAM) driver configuration.
16 bool "Battery-backed RAM shell"
DKconfig.microchip10 Enable driver for Microchip MCP7940N SRAM based battery-backed RAM.
19 battery-backed RAM.
/Zephyr-latest/include/zephyr/arch/x86/
Dmemory.ld12 * are in RAM.
17 * in RAM and are copied from flash at boot. Text/rodata linked in-place in
34 /* Bounds of physical RAM from DTS */
39 * the same as its physical location, although an identity mapping for RAM
51 /* "kernel RAM" for linker VMA allocations starts at the offset */
67 /* Physical RAM location where the kernel image is loaded */
87 * or copied into physical RAM by a loader (MMU)
97 RAM (wx) : ORIGIN = KERNEL_BASE_ADDR, LENGTH = KERNEL_RAM_SIZE
/Zephyr-latest/soc/nxp/lpc/lpc55xxx/
DKconfig.defconfig29 # By default, CMSIS SystemInit will enable the clock to these RAM banks.
34 # Some SoC's in the LPC5500 Series do have a dedicated USB RAM.
35 # By default, USB RAM is assumed to be present.
36 # Disable this Kconfig in case there is no dedicated USB RAM.
/Zephyr-latest/soc/espressif/common/
DKconfig.spiram9 bool "Support for external, SPI-connected RAM"
14 This enables support for an external SPI RAM chip, connected in
17 menu "SPI RAM config"
28 bool "Run memory test on SPI RAM initialization"
34 prompt "Mode (QUAD/OCT) of SPI RAM chip in use"
47 prompt "Type of SPI RAM chip in use"
75 prompt "Set RAM clock speed"
78 Select the speed for the SPI RAM chip.
124 can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation
134 can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation
[all …]
/Zephyr-latest/dts/arm/st/h7/
Dstm32h745.dtsi86 * The RAM memories placed here can be used by both cores M4/M7
91 /* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
97 /* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
104 /* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
111 /* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
118 /* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
/Zephyr-latest/samples/application_development/code_relocation_nocopy/
DCMakeLists.txt14 # But still relocate (copy) the data to RAM
18 zephyr_code_relocate(FILES src/sram_code.c LOCATION RAM)
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxxs/
DKconfig.soc21 23k logic cells, 1.8 Mb block RAM, 60 DSP slices, up to 100 I/O pins.
28 55k logic cells, 2.5Mb block RAM, 120 DSP slices, up to 150 I/O pins,
36 65k logic cells, 3.8Mb block RAM, 170 DSP slices, up to 200 I/O pins.
/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dboard.cmake20 \"size\":\"0x00060000\",\"type\":\"RAM\"\}")
22 \"size\":\"0x00008000\",\"type\":\"RAM\"\}")
25 \"size\":\"0x00140000\",\"type\":\"RAM\"\}")
/Zephyr-latest/subsys/demand_paging/backing_store/
DKconfig16 bool "RAM-based test backing store"
18 This implements a backing store using physical RAM pages that the
45 int "Number of pages for RAM backing store"
48 Number of pages of backing store memory to reserve in RAM. All test

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