| /Zephyr-latest/soc/nxp/imx/imx8m/m7/ |
| D | linker.ld | 13 DDR (wx) : ORIGIN = 0x80400000, LENGTH = 0x00C00000
15 DDR (wx) : ORIGIN = 0x80000000, LENGTH = 0x01000000
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| /Zephyr-latest/boards/udoo/udoo_neo_full/ |
| D | udoo_neo_full_mcimx6x_m4.dts | 14 * usually within DDR.
22 * usually within DDR.
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| /Zephyr-latest/boards/nxp/imx93_evk/ |
| D | imx93_evk_mimx9352_m33_ddr.dts | 12 model = "NXP i.MX93 EVK board DDR variant";
|
| /Zephyr-latest/boards/nxp/imx95_evk/ |
| D | imx95_evk_mimx9596_m7_ddr.dts | 12 model = "NXP i.MX95 EVK board DDR variant";
|
| D | imx95_evk_mimx9596_a55.dts | 19 /* sram node actually locates at DDR DRAM */
|
| /Zephyr-latest/boards/phytec/phyboard_pollux/ |
| D | phyboard_pollux_mimx8ml8_m7_defconfig | 17 # y for DDR memory space
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| /Zephyr-latest/boards/nxp/imx8mp_evk/ |
| D | imx8mp_evk_mimx8ml8_m7_ddr.dts | 17 /* DDR */
|
| D | imx8mp_evk_mimx8ml8_a53_smp.dts | 19 /* sram node actually locates at DDR DRAM */
|
| D | imx8mp_evk_mimx8ml8_a53.dts | 21 /* sram node actually locates at DDR DRAM */
|
| /Zephyr-latest/boards/nxp/imx91_evk/ |
| D | imx91_evk_mimx9131.dts | 19 /* sram node actually locates at DDR DRAM */
|
| /Zephyr-latest/boards/beagle/beagley_ai/doc/ |
| D | index.rst | 69 The A53 Linux configuration allocates a region in DDR that is shared with
71 Note that BeagleY-AI has 4GB of DDR.
80 | DDR Shared Region | 0x00A2000000 | 0x00A2000000 | 16MB |
90 | DDR Shared Region | 0x00A1000000 | 0x00A1000000 | 16MB |
|
| /Zephyr-latest/boards/toradex/verdin_imx8mp/ |
| D | verdin_imx8mp_mimx8ml8_m7_ddr.dts | 18 /* DDR */
|
| /Zephyr-latest/boards/nxp/imx8mp_evk/doc/ |
| D | index.rst | 173 supported: ITCM and DDR). These are the memory mapping for A53 and M7:
186 | DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB …
194 imx8mp_evk/mimx8ml8/m7/ddr for DDR).
216 DDR section in Programming and Debugging (M7)
231 and also need to reserve M4 DDR memory if using DDR code and sys address, and also
264 Extra Zephyr Kernel configure item for DDR Image:
266 If use remotepoc to boot DDR board (imx8mp_evk/mimx8ml8/m7/ddr), also need to enable
|
| /Zephyr-latest/boards/nxp/imx8mm_evk/ |
| D | imx8mm_evk_mimx8mm6_a53_smp.dts | 19 /* sram node actually locates at DDR DRAM */
|
| D | imx8mm_evk_mimx8mm6_a53.dts | 21 /* sram node actually locates at DDR DRAM */
|
| /Zephyr-latest/boards/nxp/imx8mn_evk/ |
| D | imx8mn_evk_mimx8mn6_a53_smp.dts | 19 /* sram node actually locates at DDR DRAM */
|
| D | imx8mn_evk_mimx8mn6_a53.dts | 21 /* sram node actually locates at DDR DRAM */
|
| /Zephyr-latest/boards/ti/sk_am62/ |
| D | sk_am62_am6234_m4.dts | 44 zephyr,memory-region = "DDR";
|
| /Zephyr-latest/boards/phytec/phyboard_pollux/doc/ |
| D | index.rst | 121 supported: ITCM and DDR). These are the memory mapping for A53 and M7:
134 | DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB |
145 to use the DDR region. In the devicetree overwrite you can select both options.
159 /* DDR */
165 And in the prj.conf the configuration to the **DDR** memory region:
|
| /Zephyr-latest/boards/sifive/hifive_unleashed/doc/ |
| D | index.rst | 40 Load applications on DDR and run as follows:
|
| /Zephyr-latest/boards/sifive/hifive_unmatched/doc/ |
| D | index.rst | 40 Load applications on DDR and run as follows:
|
| /Zephyr-latest/boards/phytec/phyboard_lyra/doc/ |
| D | phyboard_lyra_am62xx_a53.rst | 58 DDR RAM
61 The board has 2GB of DDR RAM available. This board configuration
|
| /Zephyr-latest/boards/phytec/phyboard_electra/ |
| D | phyboard_electra_am6442_m4.dts | 49 zephyr,memory-region = "DDR";
|
| /Zephyr-latest/boards/phytec/phyboard_lyra/ |
| D | phyboard_lyra_am6234_m4.dts | 49 zephyr,memory-region = "DDR";
|
| /Zephyr-latest/boards/96boards/meerkat96/doc/ |
| D | index.rst | 54 - External DDR memory up to 1 Gbyte
56 - Internal RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR)
163 | DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (les…
231 # DDR
275 2. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR)
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