1/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <nxp/nxp_mimx95_a55.dtsi>
10#include "imx95_evk-pinctrl.dtsi"
11
12/ {
13	model = "NXP i.MX95 A55";
14	compatible = "fsl,mimx95";
15
16	chosen {
17		zephyr,console = &lpuart1;
18		zephyr,shell-uart = &lpuart1;
19		/* sram node actually locates at DDR DRAM */
20		zephyr,sram = &dram;
21	};
22
23	cpus {
24		cpu@0 {
25			status = "disabled";
26		};
27
28		cpu@100 {
29			status = "disabled";
30		};
31
32		cpu@200 {
33			status = "disabled";
34		};
35
36		cpu@300 {
37			status = "disabled";
38		};
39
40		cpu@400 {
41			status = "disabled";
42		};
43	};
44
45	dram: memory@d0000000 {
46		reg = <0xd0000000 DT_SIZE_M(1)>;
47	};
48};
49
50&lpuart1 {
51	status = "okay";
52	current-speed = <115200>;
53	pinctrl-0 = <&lpuart1_default>;
54	pinctrl-names = "default";
55};
56