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Searched refs:hwAttrs (Results 1 – 25 of 48) sorted by relevance

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/hal_ti-latest/simplelink/source/ti/drivers/spi/
DSPICC32XXDMA.c131 SPICC32XXDMA_HWAttrsV1 const *hwAttrs, SPI_Transaction *transaction) in configDMA() argument
177 *hwAttrs->scratchBufPtr = hwAttrs->defaultTxBufValue; in configDMA()
178 buf = hwAttrs->scratchBufPtr; in configDMA()
182 MAP_uDMAChannelControlSet(hwAttrs->txChannelIndex | UDMA_PRI_SELECT, in configDMA()
184 MAP_uDMAChannelAttributeDisable(hwAttrs->txChannelIndex, in configDMA()
186 MAP_uDMAChannelTransferSet(hwAttrs->txChannelIndex | UDMA_PRI_SELECT, in configDMA()
187 UDMA_MODE_BASIC, buf, (void *) (hwAttrs->baseAddr + MCSPI_O_TX0), in configDMA()
202 buf = hwAttrs->scratchBufPtr; in configDMA()
206 MAP_uDMAChannelControlSet(hwAttrs->rxChannelIndex | UDMA_PRI_SELECT, in configDMA()
208 MAP_uDMAChannelAttributeDisable(hwAttrs->rxChannelIndex, in configDMA()
[all …]
/hal_ti-latest/simplelink/source/ti/drivers/camera/
DCameraCC32XXDMA.c93 CameraCC32XXDMA_HWAttrs const *hwAttrs = handle->hwAttrs; in CameraCC32XXDMA_configDMA() local
98 MAP_uDMAChannelAttributeDisable(hwAttrs->channelIndex,UDMA_ATTR_ALTSELECT); in CameraCC32XXDMA_configDMA()
101 MAP_uDMAChannelControlSet(hwAttrs->channelIndex, in CameraCC32XXDMA_configDMA()
103 MAP_uDMAChannelAttributeEnable(hwAttrs->channelIndex,UDMA_ATTR_USEBURST); in CameraCC32XXDMA_configDMA()
104 MAP_uDMAChannelTransferSet(hwAttrs->channelIndex, UDMA_MODE_PINGPONG, in CameraCC32XXDMA_configDMA()
110 MAP_uDMAChannelControlSet(hwAttrs->channelIndex | UDMA_ALT_SELECT, in CameraCC32XXDMA_configDMA()
112 MAP_uDMAChannelAttributeEnable(hwAttrs->channelIndex | UDMA_ALT_SELECT, in CameraCC32XXDMA_configDMA()
114 MAP_uDMAChannelTransferSet(hwAttrs->channelIndex | UDMA_ALT_SELECT, in CameraCC32XXDMA_configDMA()
119 MAP_uDMAChannelEnable(hwAttrs->channelIndex | UDMA_ALT_SELECT); in CameraCC32XXDMA_configDMA()
124 DebugP_log1("Camera:(%p) DMA transfer enabled", hwAttrs->baseAddr); in CameraCC32XXDMA_configDMA()
[all …]
/hal_ti-latest/simplelink/source/ti/drivers/uart/
DUARTCC32XXDMA.c123 static inline bool isFlowControlEnabled(UARTCC32XXDMA_HWAttrsV1 const *hwAttrs) { in isFlowControlEnabled() argument
124 return ((hwAttrs->flowControl == UARTCC32XXDMA_FLOWCTRL_HARDWARE) && in isFlowControlEnabled()
125 (hwAttrs->ctsPin != UARTCC32XXDMA_PIN_UNASSIGNED) && in isFlowControlEnabled()
126 (hwAttrs->rtsPin != UARTCC32XXDMA_PIN_UNASSIGNED)); in isFlowControlEnabled()
156 UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in UARTCC32XXDMA_close() local
160 MAP_UARTDMADisable(hwAttrs->baseAddr, UART_DMA_TX | UART_DMA_RX); in UARTCC32XXDMA_close()
161 MAP_UARTDisable(hwAttrs->baseAddr); in UARTCC32XXDMA_close()
196 padRegister = (PinToPadGet((hwAttrs->rxPin) & 0xff)<<2) + PAD_CONFIG_BASE; in UARTCC32XXDMA_close()
198 padRegister = (PinToPadGet((hwAttrs->txPin) & 0xff)<<2) + PAD_CONFIG_BASE; in UARTCC32XXDMA_close()
200 if (isFlowControlEnabled(hwAttrs)) { in UARTCC32XXDMA_close()
[all …]
DUARTCC32XX.c107 static inline bool isFlowControlEnabled(UARTCC32XX_HWAttrsV1 const *hwAttrs) { in isFlowControlEnabled() argument
108 return ((hwAttrs->flowControl == UARTCC32XX_FLOWCTRL_HARDWARE) && in isFlowControlEnabled()
109 (hwAttrs->ctsPin != UARTCC32XX_PIN_UNASSIGNED) && in isFlowControlEnabled()
110 (hwAttrs->rtsPin != UARTCC32XX_PIN_UNASSIGNED)); in isFlowControlEnabled()
181 UARTCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in UARTCC32XX_close() local
186 MAP_UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX | UART_INT_RX | in UARTCC32XX_close()
188 MAP_UARTDisable(hwAttrs->baseAddr); in UARTCC32XX_close()
216 hwAttrs->baseAddr); in UARTCC32XX_close()
233 padRegister = (PinToPadGet((hwAttrs->rxPin) & 0xff)<<2) + PAD_CONFIG_BASE; in UARTCC32XX_close()
235 padRegister = (PinToPadGet((hwAttrs->txPin) & 0xff)<<2) + PAD_CONFIG_BASE; in UARTCC32XX_close()
[all …]
/hal_ti-latest/simplelink/source/ti/drivers/uart2/
DUART2CC32XX.c230 static inline bool isFlowControlEnabled(UART2CC32XX_HWAttrs const *hwAttrs) { in isFlowControlEnabled() argument
231 return (hwAttrs->flowControl == UART2CC32XX_FLOWCTRL_HARDWARE); in isFlowControlEnabled()
240 UART2CC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in UART2CC32XX_close() local
244 UARTIntDisable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT | UART_INT_OE | in UART2CC32XX_close()
248 uartDmaDisable(hwAttrs->baseAddr, UART_DMA_TX | UART_DMA_RX); in UART2CC32XX_close()
249 MAP_UARTDisable(hwAttrs->baseAddr); in UART2CC32XX_close()
280 padRegister = (PinToPadGet((hwAttrs->rxPin) & 0xff)<<2) + PAD_CONFIG_BASE; in UART2CC32XX_close()
282 padRegister = (PinToPadGet((hwAttrs->txPin) & 0xff)<<2) + PAD_CONFIG_BASE; in UART2CC32XX_close()
284 if (isFlowControlEnabled(hwAttrs)) { in UART2CC32XX_close()
285 if (hwAttrs->ctsPin != UART2CC32XX_PIN_UNASSIGNED) { in UART2CC32XX_close()
[all …]
/hal_ti-latest/simplelink/source/ti/drivers/i2c/
DI2CCC32XX.c102 I2CCC32XX_HWAttrsV1 const *hwAttrs);
104 I2CCC32XX_HWAttrsV1 const *hwAttrs);
106 I2CCC32XX_HWAttrsV1 const *hwAttrs, I2C_Transaction *transaction);
108 I2CCC32XX_HWAttrsV1 const *hwAttrs);
137 I2CCC32XX_HWAttrsV1 const *hwAttrs) in I2CCC32XX_fillTransmitFifo() argument
140 I2CFIFODataPutNonBlocking(hwAttrs->baseAddr, *(object->writeBuf))) { in I2CCC32XX_fillTransmitFifo()
147 I2CMasterIntClearEx(hwAttrs->baseAddr, I2C_MASTER_INT_TX_FIFO_EMPTY); in I2CCC32XX_fillTransmitFifo()
157 I2CCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in I2CCC32XX_initHw() local
171 MAP_I2CMasterIntDisableEx(hwAttrs->baseAddr, 0xFFFFFFFF); in I2CCC32XX_initHw()
177 MAP_I2CMasterInitExpClk(hwAttrs->baseAddr, freq.lo, in I2CCC32XX_initHw()
[all …]
/hal_ti-latest/simplelink/source/ti/drivers/watchdog/
DWatchdogCC32XX.c88 WatchdogCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in WatchdogCC32XX_initHardware() local
91 MAP_WatchdogUnlock(hwAttrs->baseAddr); in WatchdogCC32XX_initHardware()
92 MAP_WatchdogReloadSet(hwAttrs->baseAddr, object->reloadValue); in WatchdogCC32XX_initHardware()
93 MAP_WatchdogIntClear(hwAttrs->baseAddr); in WatchdogCC32XX_initHardware()
97 MAP_WatchdogStallEnable(hwAttrs->baseAddr); in WatchdogCC32XX_initHardware()
100 MAP_WatchdogStallDisable(hwAttrs->baseAddr); in WatchdogCC32XX_initHardware()
103 MAP_WatchdogEnable(hwAttrs->baseAddr); in WatchdogCC32XX_initHardware()
105 MAP_WatchdogLock(hwAttrs->baseAddr); in WatchdogCC32XX_initHardware()
126 WatchdogCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in WatchdogCC32XX_clear() local
128 MAP_WatchdogIntClear(hwAttrs->baseAddr); in WatchdogCC32XX_clear()
[all …]
/hal_ti-latest/simplelink/source/ti/drivers/sd/
DSDHostCC32XX.c173 SDHostCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in SDHostCC32XX_close() local
180 hwAttrs->baseAddr); in SDHostCC32XX_close()
185 MAP_SDHostIntDisable(hwAttrs->baseAddr, DATAERROR | CMDERROR); in SDHostCC32XX_close()
207 padRegister = (PinToPadGet((hwAttrs->dataPin) & 0x3f)<<2) + PAD_CONFIG_BASE; in SDHostCC32XX_close()
209 padRegister = (PinToPadGet((hwAttrs->cmdPin) & 0x3f)<<2) + PAD_CONFIG_BASE; in SDHostCC32XX_close()
211 padRegister = (PinToPadGet((hwAttrs->clkPin) & 0x3f)<<2) + PAD_CONFIG_BASE; in SDHostCC32XX_close()
217 hwAttrs->baseAddr); in SDHostCC32XX_close()
244 SDHostCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in SDHostCC32XX_getNumSectors() local
248 " power constraint", hwAttrs->baseAddr); in SDHostCC32XX_getNumSectors()
254 " power constraint", hwAttrs->baseAddr); in SDHostCC32XX_getNumSectors()
[all …]
DSDSPI.c85 static inline void assertCS(SDSPI_HWAttrs const *hwAttrs);
86 static inline void deassertCS(SDSPI_HWAttrs const *hwAttrs);
147 SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; in SDSPI_getNumSectors() local
151 assertCS(hwAttrs); in SDSPI_getNumSectors()
172 deassertCS(hwAttrs); in SDSPI_getNumSectors()
212 SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; in SDSPI_initialize() local
220 deassertCS(hwAttrs); in SDSPI_initialize()
234 assertCS(hwAttrs); in SDSPI_initialize()
250 deassertCS(hwAttrs); in SDSPI_initialize()
351 deassertCS(hwAttrs); in SDSPI_initialize()
[all …]
/hal_ti-latest/simplelink/source/ti/drivers/nvs/
DNVSSPI25X.c131 NVSSPI25X_HWAttrs const *hwAttrs; in NVSSPI25X_close() local
136 hwAttrs = handle->hwAttrs; in NVSSPI25X_close()
140 spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; in NVSSPI25X_close()
143 if (hwAttrs->spiHandle == NULL) { in NVSSPI25X_close()
144 spiHandleUsers[hwAttrs->spiIndex] -= 1; in NVSSPI25X_close()
147 if (spiHandleUsers[hwAttrs->spiIndex] == 0) { in NVSSPI25X_close()
155 spiHandles[hwAttrs->spiIndex] = NULL; in NVSSPI25X_close()
171 NVSSPI25X_HWAttrs const *hwAttrs; in NVSSPI25X_control() local
176 hwAttrs = handle->hwAttrs; in NVSSPI25X_control()
181 spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; in NVSSPI25X_control()
[all …]
DNVSRAM.c110 NVSRAM_HWAttrs const *hwAttrs = handle->hwAttrs; in NVSRAM_getAttrs() local
112 attrs->regionBase = hwAttrs->regionBase; in NVSRAM_getAttrs()
113 attrs->regionSize = hwAttrs->regionSize; in NVSRAM_getAttrs()
114 attrs->sectorSize = hwAttrs->sectorSize; in NVSRAM_getAttrs()
165 NVSRAM_HWAttrs const *hwAttrs; in NVSRAM_open() local
182 hwAttrs = NVS_config[index].hwAttrs; in NVSRAM_open()
185 object->sectorBaseMask = ~(hwAttrs->sectorSize - 1); in NVSRAM_open()
196 if ((size_t) (hwAttrs->regionBase) & (hwAttrs->sectorSize - 1)) { in NVSRAM_open()
203 if (hwAttrs->regionSize < hwAttrs->sectorSize) { in NVSRAM_open()
210 if (hwAttrs->regionSize != in NVSRAM_open()
[all …]
/hal_ti-latest/simplelink/source/ti/drivers/timer/
DTimerCC32XX.c117 TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in initHw() local
121 TimerDisable(hwAttrs->baseAddress, object->timer); in initHw()
125 HWREG(hwAttrs->baseAddress + TIMER_O_TAMR) = TIMER_TAMR_TAMR_PERIOD; in initHw()
129 HWREG(hwAttrs->baseAddress + TIMER_O_TBMR) = TIMER_TBMR_TBMR_PERIOD; in initHw()
132 if (hwAttrs->subTimer == TimerCC32XX_timer32) { in initHw()
134 HWREG(hwAttrs->baseAddress + TIMER_O_CFG) = TIMER_CFG_32_BIT_TIMER; in initHw()
138 HWREG(hwAttrs->baseAddress + TIMER_O_CFG) = TIMER_CFG_16_BIT; in initHw()
142 HWREG(hwAttrs->baseAddress + TIMER_O_IMR) = ~object->timer; in initHw()
145 TimerPrescaleSet(hwAttrs->baseAddress, object->timer, object->prescaler); in initHw()
146 TimerLoadSet(hwAttrs->baseAddress, object->timer, object->period); in initHw()
[all …]
/hal_ti-latest/simplelink/source/ti/drivers/capture/
DCaptureCC32XX.c94 CaptureCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in CaptureCC32XX_close() local
96 uint32_t baseAddress = getTimerBaseAddress(hwAttrs->capturePin); in CaptureCC32XX_close()
98 subTimer = (TimerCC32XX_SubTimer) getSubTimer(hwAttrs->capturePin); in CaptureCC32XX_close()
103 Power_releaseDependency(getPowerMgrId(getGPIOBaseAddress(hwAttrs->capturePin))); in CaptureCC32XX_close()
114 HWREG(OCP_SHARED_BASE + getPadOffset(hwAttrs->capturePin)) in CaptureCC32XX_close()
133 CaptureCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in CaptureCC32XX_hwiIntFunction() local
135 uint32_t baseAddress = getTimerBaseAddress(hwAttrs->capturePin); in CaptureCC32XX_hwiIntFunction()
194 CaptureCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in CaptureCC32XX_open() local
223 powerId = getPowerMgrId(getGPIOBaseAddress(hwAttrs->capturePin)); in CaptureCC32XX_open()
231 if (!TimerCC32XX_allocateTimerResource(getTimerBaseAddress(hwAttrs->capturePin), in CaptureCC32XX_open()
[all …]
/hal_ti-latest/simplelink/source/ti/drivers/pwm/
DPWMTimerCC32XX.c265 PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; in initHw() local
269 timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; in initHw()
270 halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; in initHw()
336 PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; in PWMTimerCC32XX_close() local
343 timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; in PWMTimerCC32XX_close()
346 PinConfigTimerHalf(hwAttrs->pwmPin)); in PWMTimerCC32XX_close()
352 gpioBaseAddr = (PinConfigGPIOPort(hwAttrs->pwmPin) >= NUMGPIOPORTS) ? in PWMTimerCC32XX_close()
353 0 : gpioBaseAddresses[PinConfigGPIOPort(hwAttrs->pwmPin)]; in PWMTimerCC32XX_close()
368 padRegister = (PinToPadGet((hwAttrs->pwmPin) & 0x3f)<<2) + PAD_CONFIG_BASE; in PWMTimerCC32XX_close()
405 PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; in PWMTimerCC32XX_open() local
[all …]
/hal_ti-latest/simplelink/source/ti/drivers/dma/
DUDMACC32XX.c88 UDMACC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in UDMACC32XX_init() local
95 hwiParams.priority = hwAttrs->intPriority; in UDMACC32XX_init()
98 object->hwiHandle = HwiP_create(hwAttrs->intNum, hwAttrs->dmaErrorFxn, in UDMACC32XX_init()
116 UDMACC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in UDMACC32XX_open() local
135 MAP_uDMAControlBaseSet(hwAttrs->controlBaseAddr); in UDMACC32XX_open()
158 UDMACC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in postNotifyFxn() local
161 MAP_uDMAControlBaseSet(hwAttrs->controlBaseAddr); in postNotifyFxn()
DUDMACC32XX.h127 void const *hwAttrs; /*!< Pointer to hardware attributes */ member
/hal_ti-latest/simplelink/source/ti/drivers/adc/
DADCCC32XX.c102 ADCCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in ADCCC32XX_close() local
104 pin = PinConfigChannel(hwAttrs->adcPin); in ADCCC32XX_close()
118 pin = PinConfigPin(hwAttrs->adcPin); in ADCCC32XX_close()
146 ADCCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in ADCCC32XX_convert() local
148 adcChannel = PinConfigChannel(hwAttrs->adcPin); in ADCCC32XX_convert()
194 ADCCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in ADCCC32XX_open() local
212 pin = PinConfigPin(hwAttrs->adcPin); in ADCCC32XX_open()
216 pin = PinConfigChannel(hwAttrs->adcPin); in ADCCC32XX_open()
/hal_ti-latest/simplelink/source/ti/drivers/i2s/
DI2SCC32XX.c137 static void restorePinpads(I2SCC32XX_HWAttrs const *hwAttrs);
184 I2SCC32XX_HWAttrs const *hwAttrs; in I2S_open() local
190 hwAttrs = handle->hwAttrs; in I2S_open()
210 hwiParams.priority = hwAttrs->intPriority; in I2S_open()
216 restorePinpads(hwAttrs); in I2S_open()
252 I2SCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in I2S_close() local
279 restorePinpads(hwAttrs); in I2S_close()
360 I2SCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in I2S_startRead() local
379 MAP_uDMAChannelAttributeEnable(hwAttrs->rxChannelIndex,UDMA_ATTR_USEBURST); in I2S_startRead()
380 MAP_uDMAChannelAssign(hwAttrs->rxChannelIndex); in I2S_startRead()
[all …]
/hal_ti-latest/simplelink_lpf3/source/ti/drivers/
Dconfig_defaults.c79 .hwAttrs = &AESCCMLPF3_hwAttrs[CONFIG_AESCCM_0]
108 .hwAttrs = &AESCMACLPF3_hwAttrs[CONFIG_AESCMAC_0]
137 .hwAttrs = &AESCTRLPF3_hwAttrs[CONFIG_AESCTR_0]
175 .hwAttrs = &aesctrdrbgXXHWAttrs[CONFIG_AESCTRDRBG_0]
204 .hwAttrs = &AESECBLPF3_hwAttrs[CONFIG_AESECB_0]
DAESCommon.h160 void const *hwAttrs; member
/hal_ti-latest/simplelink_lpf3/source/ti/drivers/utils/
DRandom.c83 const TRNGCC26XX_HWAttrs hwAttrs = { in Random_seedAutomatic() local
91 TRNG_Config config = {.object = &object, .hwAttrs = &hwAttrs}; in Random_seedAutomatic()
136 rngConfig.hwAttrs = NULL; in Random_seedAutomatic()
/hal_ti-latest/simplelink/source/ti/drivers/net/wifi/porting/
DCC3220SF_LAUNCHXL.c78 .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI0]
83 .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI1]
122 .hwAttrs = &udmaCC3220SHWAttrs
/hal_ti-latest/simplelink/source/ti/drivers/utils/
DRandom.c82 const TRNGCC26XX_HWAttrs hwAttrs = { in Random_seedAutomatic() local
91 .hwAttrs = &hwAttrs in Random_seedAutomatic()
/hal_ti-latest/simplelink_lpf3/source/ti/drivers/aesctrdrbg/
DAESCTRDRBGXX.c220 const AESCTRDRBGXX_HWAttrs *hwAttrs; in AESCTRDRBG_construct() local
233 hwAttrs = handle->hwAttrs; in AESCTRDRBG_construct()
272 object->ctrConfig.hwAttrs = &hwAttrs->aesctrHWAttrs; in AESCTRDRBG_construct()
/hal_ti-latest/simplelink/source/ti/drivers/apps/
DButton.c84 Button_HWAttrs *hw = (Button_HWAttrs *)handle->hwAttrs; in Button_close()
104 Button_HWAttrs *hw = (Button_HWAttrs*) Button_config[i].hwAttrs; in Button_gpioCallbackFxn()
169 hw = (Button_HWAttrs*)buttonHandle->hwAttrs; in Button_clockTimeoutHandler()
405 hw = (Button_HWAttrs*)(Button_config[buttonIndex].hwAttrs); in Button_open()

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