Lines Matching refs:hwAttrs
230 static inline bool isFlowControlEnabled(UART2CC32XX_HWAttrs const *hwAttrs) { in isFlowControlEnabled() argument
231 return (hwAttrs->flowControl == UART2CC32XX_FLOWCTRL_HARDWARE); in isFlowControlEnabled()
240 UART2CC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in UART2CC32XX_close() local
244 UARTIntDisable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT | UART_INT_OE | in UART2CC32XX_close()
248 uartDmaDisable(hwAttrs->baseAddr, UART_DMA_TX | UART_DMA_RX); in UART2CC32XX_close()
249 MAP_UARTDisable(hwAttrs->baseAddr); in UART2CC32XX_close()
280 padRegister = (PinToPadGet((hwAttrs->rxPin) & 0xff)<<2) + PAD_CONFIG_BASE; in UART2CC32XX_close()
282 padRegister = (PinToPadGet((hwAttrs->txPin) & 0xff)<<2) + PAD_CONFIG_BASE; in UART2CC32XX_close()
284 if (isFlowControlEnabled(hwAttrs)) { in UART2CC32XX_close()
285 if (hwAttrs->ctsPin != UART2CC32XX_PIN_UNASSIGNED) { in UART2CC32XX_close()
286 padRegister = (PinToPadGet((hwAttrs->ctsPin) & 0xff)<<2) in UART2CC32XX_close()
291 if (hwAttrs->rtsPin != UART2CC32XX_PIN_UNASSIGNED) { in UART2CC32XX_close()
292 padRegister = (PinToPadGet((hwAttrs->rtsPin) & 0xff)<<2) in UART2CC32XX_close()
306 UART2CC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in UART2CC32XX_flushRx() local
309 MAP_UARTRxErrorClear(hwAttrs->baseAddr); in UART2CC32XX_flushRx()
312 while (((int32_t)MAP_UARTCharGetNonBlocking(hwAttrs->baseAddr)) != -1); in UART2CC32XX_flushRx()
326 UART2CC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in UART2CC32XX_hwiIntFxn() local
330 status = MAP_UARTIntStatus(hwAttrs->baseAddr, true); in UART2CC32XX_hwiIntFxn()
331 MAP_UARTIntClear(hwAttrs->baseAddr, status); in UART2CC32XX_hwiIntFxn()
336 UARTDMADisable(hwAttrs->baseAddr, UART_DMA_RX); in UART2CC32XX_hwiIntFxn()
339 bytesToRead = uDMAChannelSizeGet(hwAttrs->rxDmaChannel); in UART2CC32XX_hwiIntFxn()
343 errStatus = UARTRxErrorGet(hwAttrs->baseAddr); in UART2CC32XX_hwiIntFxn()
359 fifoThresholdBytes = rxFifoBytes[hwAttrs->rxIntFifoThr]; in UART2CC32XX_hwiIntFxn()
370 object->readSize && !uDMAChannelIsEnabled(hwAttrs->rxDmaChannel)) { in UART2CC32XX_hwiIntFxn()
371 UARTDMADisable(hwAttrs->baseAddr, UART_DMA_RX); in UART2CC32XX_hwiIntFxn()
373 errStatus = MAP_UARTRxErrorGet(hwAttrs->baseAddr); in UART2CC32XX_hwiIntFxn()
375 MAP_UARTRxErrorClear(hwAttrs->baseAddr); in UART2CC32XX_hwiIntFxn()
377 UARTIntDisable(hwAttrs->baseAddr, UART_INT_DMARX); in UART2CC32XX_hwiIntFxn()
378 UARTIntClear(hwAttrs->baseAddr, UART_INT_DMARX); in UART2CC32XX_hwiIntFxn()
395 if (object->writeCount && !MAP_uDMAChannelIsEnabled(hwAttrs->txDmaChannel)) { in UART2CC32XX_hwiIntFxn()
400 UARTDMADisable(hwAttrs->baseAddr, UART_DMA_TX); in UART2CC32XX_hwiIntFxn()
402 UARTIntDisable(hwAttrs->baseAddr, UART_INT_DMATX); in UART2CC32XX_hwiIntFxn()
403 UARTIntClear(hwAttrs->baseAddr, UART_INT_DMATX); in UART2CC32XX_hwiIntFxn()
434 UART2CC32XX_HWAttrs const *hwAttrs; in UART2CC32XX_open() local
442 hwAttrs = handle->hwAttrs; in UART2CC32XX_open()
499 object->powerMgrId = getPowerMgrId(hwAttrs->baseAddr); in UART2CC32XX_open()
514 pin = (hwAttrs->rxPin) & 0xff; in UART2CC32XX_open()
515 mode = (hwAttrs->rxPin >> 8) & 0xff; in UART2CC32XX_open()
519 pin = (hwAttrs->txPin) & 0xff; in UART2CC32XX_open()
520 mode = (hwAttrs->txPin >> 8) & 0xff; in UART2CC32XX_open()
533 if (isFlowControlEnabled(hwAttrs)) { in UART2CC32XX_open()
534 if (hwAttrs->ctsPin != UART2CC32XX_PIN_UNASSIGNED) { in UART2CC32XX_open()
535 pin = (hwAttrs->ctsPin) & 0xff; in UART2CC32XX_open()
536 mode = (hwAttrs->ctsPin >> 8) & 0xff; in UART2CC32XX_open()
540 if (hwAttrs->rtsPin != UART2CC32XX_PIN_UNASSIGNED) { in UART2CC32XX_open()
541 pin = (hwAttrs->rtsPin) & 0xff; in UART2CC32XX_open()
542 mode = (hwAttrs->rtsPin >> 8) & 0xff; in UART2CC32XX_open()
572 HwiP_clearInterrupt(hwAttrs->intNum); in UART2CC32XX_open()
576 hwiParams.priority = hwAttrs->intPriority; in UART2CC32XX_open()
578 object->hwi = HwiP_create(hwAttrs->intNum, UART2CC32XX_hwiIntFxn, in UART2CC32XX_open()
616 UART2CC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in UART2CC32XX_read() local
629 errStatus = UARTRxErrorGet(hwAttrs->baseAddr); in UART2CC32XX_read()
631 UARTRxErrorClear(hwAttrs->baseAddr); in UART2CC32XX_read()
656 data = UARTCharGetNonBlocking(hwAttrs->baseAddr); in UART2CC32XX_read()
763 UART2CC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in UART2CC32XX_write() local
812 if (!UARTCharPutNonBlocking(hwAttrs->baseAddr, *buf)) { in UART2CC32XX_write()
836 UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX); in UART2CC32XX_write()
837 UARTIntClear(hwAttrs->baseAddr, UART_INT_TX); in UART2CC32XX_write()
859 UART2CC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in UART2CC32XX_writeCancel() local
865 MAP_uDMAChannelDisable(hwAttrs->txDmaChannel); in UART2CC32XX_writeCancel()
866 uartDmaDisable(hwAttrs->baseAddr, UART_DMA_TX); in UART2CC32XX_writeCancel()
868 UARTIntDisable(hwAttrs->baseAddr, UART_INT_DMATX); in UART2CC32XX_writeCancel()
869 UARTIntClear(hwAttrs->baseAddr, UART_INT_DMATX); in UART2CC32XX_writeCancel()
879 bytesRemaining = MAP_uDMAChannelSizeGet(hwAttrs->txDmaChannel); in UART2CC32XX_writeCancel()
907 UART2CC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in configDmaRx() local
917 MAP_uDMAChannelControlSet(hwAttrs->rxDmaChannel, RX_CONTROL_OPTS); in configDmaRx()
918 MAP_uDMAChannelTransferSet(hwAttrs->rxDmaChannel, UDMA_MODE_BASIC, in configDmaRx()
919 (void *)(hwAttrs->baseAddr + UART_O_DR), in configDmaRx()
923 uartDmaEnable(hwAttrs->baseAddr, UART_DMA_RX); in configDmaRx()
925 MAP_UARTIntEnable(hwAttrs->baseAddr, UART_INT_DMARX); in configDmaRx()
927 MAP_uDMAChannelEnable(hwAttrs->rxDmaChannel); in configDmaRx()
939 UART2CC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in configDmaTx() local
950 MAP_uDMAChannelControlSet(hwAttrs->txDmaChannel, TX_CONTROL_OPTS); in configDmaTx()
951 MAP_uDMAChannelTransferSet(hwAttrs->txDmaChannel, UDMA_MODE_BASIC, in configDmaTx()
953 (void *)(hwAttrs->baseAddr + UART_O_DR), txSize); in configDmaTx()
955 uartDmaEnable(hwAttrs->baseAddr, UART_DMA_TX); in configDmaTx()
957 MAP_UARTIntEnable(hwAttrs->baseAddr, UART_INT_DMATX); in configDmaTx()
959 MAP_uDMAChannelEnable(hwAttrs->txDmaChannel); in configDmaTx()
985 UART2CC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in initHw() local
990 MAP_UARTConfigSetExpClk(hwAttrs->baseAddr, freq.lo, object->baudRate, in initHw()
996 UARTIntClear(hwAttrs->baseAddr, UART_INT_OE | UART_INT_BE | UART_INT_PE | in initHw()
1000 UARTEnable(hwAttrs->baseAddr); in initHw()
1002 UARTIntEnable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT | UART_INT_OE | in initHw()
1005 MAP_UARTFIFOLevelSet(hwAttrs->baseAddr, txFifoThreshold[hwAttrs->txIntFifoThr], in initHw()
1006 rxFifoThreshold[hwAttrs->rxIntFifoThr]); in initHw()
1008 if (isFlowControlEnabled(hwAttrs)) { in initHw()
1010 if (hwAttrs->ctsPin != UART2CC32XX_PIN_UNASSIGNED) { in initHw()
1014 if (hwAttrs->rtsPin != UART2CC32XX_PIN_UNASSIGNED) { in initHw()
1018 MAP_UARTFlowControlSet(hwAttrs->baseAddr, mode); in initHw()
1020 if (hwAttrs->rxPin != UART2CC32XX_PIN_UNASSIGNED) { in initHw()
1021 MAP_uDMAChannelAssign(hwAttrs->rxDmaChannel); in initHw()
1023 uDMAChannelAttributeDisable(hwAttrs->rxDmaChannel, (UDMA_ATTR_ALTSELECT | in initHw()
1028 if (hwAttrs->txPin != UART2CC32XX_PIN_UNASSIGNED) { in initHw()
1029 MAP_uDMAChannelAssign(hwAttrs->txDmaChannel); in initHw()
1031 uDMAChannelAttributeDisable(hwAttrs->txDmaChannel, (UDMA_ATTR_ALTSELECT | in initHw()
1057 UART2CC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in cancelDmaRx() local
1069 MAP_uDMAChannelDisable(hwAttrs->rxDmaChannel); in cancelDmaRx()
1070 uartDmaDisable(hwAttrs->baseAddr, UART_DMA_RX); in cancelDmaRx()
1072 UARTIntDisable(hwAttrs->baseAddr, UART_INT_DMARX); in cancelDmaRx()
1073 UARTIntClear(hwAttrs->baseAddr, UART_INT_DMARX); in cancelDmaRx()
1081 bytesRemaining = MAP_uDMAChannelSizeGet(hwAttrs->rxDmaChannel); in cancelDmaRx()
1101 UART2CC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; in readData() local
1109 data = UARTCharGetNonBlocking(hwAttrs->baseAddr); in readData()