Lines Matching refs:hwAttrs
123 static inline bool isFlowControlEnabled(UARTCC32XXDMA_HWAttrsV1 const *hwAttrs) { in isFlowControlEnabled() argument
124 return ((hwAttrs->flowControl == UARTCC32XXDMA_FLOWCTRL_HARDWARE) && in isFlowControlEnabled()
125 (hwAttrs->ctsPin != UARTCC32XXDMA_PIN_UNASSIGNED) && in isFlowControlEnabled()
126 (hwAttrs->rtsPin != UARTCC32XXDMA_PIN_UNASSIGNED)); in isFlowControlEnabled()
156 UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in UARTCC32XXDMA_close() local
160 MAP_UARTDMADisable(hwAttrs->baseAddr, UART_DMA_TX | UART_DMA_RX); in UARTCC32XXDMA_close()
161 MAP_UARTDisable(hwAttrs->baseAddr); in UARTCC32XXDMA_close()
196 padRegister = (PinToPadGet((hwAttrs->rxPin) & 0xff)<<2) + PAD_CONFIG_BASE; in UARTCC32XXDMA_close()
198 padRegister = (PinToPadGet((hwAttrs->txPin) & 0xff)<<2) + PAD_CONFIG_BASE; in UARTCC32XXDMA_close()
200 if (isFlowControlEnabled(hwAttrs)) { in UARTCC32XXDMA_close()
201 padRegister = (PinToPadGet((hwAttrs->ctsPin) & 0xff)<<2) in UARTCC32XXDMA_close()
204 padRegister = (PinToPadGet((hwAttrs->rtsPin) & 0xff)<<2) in UARTCC32XXDMA_close()
211 DebugP_log1("UART:(%p) closed", hwAttrs->baseAddr); in UARTCC32XXDMA_close()
221 UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in UARTCC32XXDMA_control() local
226 *(bool *)arg = MAP_UARTBusy(hwAttrs->baseAddr); in UARTCC32XXDMA_control()
230 *(bool *)arg = MAP_UARTCharsAvail(hwAttrs->baseAddr); in UARTCC32XXDMA_control()
234 *(bool *)arg = MAP_UARTSpaceAvail(hwAttrs->baseAddr); in UARTCC32XXDMA_control()
239 hwAttrs->baseAddr, cmd); in UARTCC32XXDMA_control()
258 UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in UARTCC32XXDMA_open() local
277 object->powerMgrId = getPowerMgrId(hwAttrs->baseAddr); in UARTCC32XXDMA_open()
280 hwAttrs->baseAddr); in UARTCC32XXDMA_open()
291 DebugP_log1("UART:(%p) already in use.", hwAttrs->baseAddr); in UARTCC32XXDMA_open()
342 DebugP_log1("UART:(%p) UDMACC32XX_open() failed.", hwAttrs->baseAddr); in UARTCC32XXDMA_open()
346 pin = (hwAttrs->rxPin) & 0xff; in UARTCC32XXDMA_open()
347 mode = (hwAttrs->rxPin >> 8) & 0xff; in UARTCC32XXDMA_open()
351 pin = (hwAttrs->txPin) & 0xff; in UARTCC32XXDMA_open()
352 mode = (hwAttrs->txPin >> 8) & 0xff; in UARTCC32XXDMA_open()
365 if (isFlowControlEnabled(hwAttrs)) { in UARTCC32XXDMA_open()
366 pin = (hwAttrs->ctsPin) & 0xff; in UARTCC32XXDMA_open()
367 mode = (hwAttrs->ctsPin >> 8) & 0xff; in UARTCC32XXDMA_open()
370 pin = (hwAttrs->rtsPin) & 0xff; in UARTCC32XXDMA_open()
371 mode = (hwAttrs->rtsPin >> 8) & 0xff; in UARTCC32XXDMA_open()
385 HwiP_clearInterrupt(hwAttrs->intNum); in UARTCC32XXDMA_open()
389 hwiParams.priority = hwAttrs->intPriority; in UARTCC32XXDMA_open()
390 object->hwiHandle = HwiP_create(hwAttrs->intNum, in UARTCC32XXDMA_open()
394 DebugP_log1("UART:(%p) HwiP_create() failed", hwAttrs->baseAddr); in UARTCC32XXDMA_open()
400 MAP_UARTIntDisable(hwAttrs->baseAddr, in UARTCC32XXDMA_open()
414 hwAttrs->baseAddr); in UARTCC32XXDMA_open()
426 hwAttrs->baseAddr); in UARTCC32XXDMA_open()
444 hwAttrs->baseAddr); in UARTCC32XXDMA_open()
452 DebugP_log1("UART:(%p) opened", hwAttrs->baseAddr); in UARTCC32XXDMA_open()
469 ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); in UARTCC32XXDMA_read()
480 ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); in UARTCC32XXDMA_read()
528 ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr, in UARTCC32XXDMA_read()
546 UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in UARTCC32XXDMA_readPolling() local
551 *buffer = MAP_UARTCharGet(hwAttrs->baseAddr); in UARTCC32XXDMA_readPolling()
553 hwAttrs->baseAddr, *buffer); in UARTCC32XXDMA_readPolling()
560 MAP_UARTCharPut(hwAttrs->baseAddr, '\r'); in UARTCC32XXDMA_readPolling()
567 MAP_UARTCharPut(hwAttrs->baseAddr, *buffer); in UARTCC32XXDMA_readPolling()
580 hwAttrs->baseAddr, count); in UARTCC32XXDMA_readPolling()
609 ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); in UARTCC32XXDMA_readCancel()
620 UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in UARTCC32XXDMA_write() local
624 DebugP_log1("UART:(%p) Data size too large.", hwAttrs->baseAddr); in UARTCC32XXDMA_write()
631 if (object->writeSize || UARTBusy(hwAttrs->baseAddr)) { in UARTCC32XXDMA_write()
634 ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); in UARTCC32XXDMA_write()
674 ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr, in UARTCC32XXDMA_write()
692 UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in UARTCC32XXDMA_writePolling() local
698 MAP_UARTCharPut(hwAttrs->baseAddr, '\r'); in UARTCC32XXDMA_writePolling()
701 MAP_UARTCharPut(hwAttrs->baseAddr, *buffer); in UARTCC32XXDMA_writePolling()
704 ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr, in UARTCC32XXDMA_writePolling()
712 ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr, in UARTCC32XXDMA_writePolling()
743 ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr, in UARTCC32XXDMA_writeCancel()
754 UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in UARTCC32XXDMA_configDMA() local
761 MAP_uDMAChannelControlSet(hwAttrs->txChannelIndex | UDMA_PRI_SELECT, in UARTCC32XXDMA_configDMA()
764 MAP_uDMAChannelTransferSet(hwAttrs->txChannelIndex | UDMA_PRI_SELECT, in UARTCC32XXDMA_configDMA()
767 (void *)(hwAttrs->baseAddr + UART_O_DR), in UARTCC32XXDMA_configDMA()
775 MAP_uDMAChannelEnable(hwAttrs->txChannelIndex); in UARTCC32XXDMA_configDMA()
777 MAP_UARTIntClear(hwAttrs->baseAddr, UART_INT_DMATX); in UARTCC32XXDMA_configDMA()
778 MAP_UARTIntEnable(hwAttrs->baseAddr, UART_INT_DMATX); in UARTCC32XXDMA_configDMA()
784 MAP_uDMAChannelControlSet(hwAttrs->rxChannelIndex | UDMA_PRI_SELECT, in UARTCC32XXDMA_configDMA()
787 MAP_uDMAChannelTransferSet(hwAttrs->rxChannelIndex | UDMA_PRI_SELECT, in UARTCC32XXDMA_configDMA()
789 (void *)(hwAttrs->baseAddr + UART_O_DR), in UARTCC32XXDMA_configDMA()
794 MAP_uDMAChannelEnable(hwAttrs->rxChannelIndex); in UARTCC32XXDMA_configDMA()
796 MAP_UARTIntClear(hwAttrs->baseAddr, UART_INT_DMARX); in UARTCC32XXDMA_configDMA()
797 MAP_UARTIntEnable(hwAttrs->baseAddr, UART_INT_DMARX); in UARTCC32XXDMA_configDMA()
800 DebugP_log1("UART:(%p) DMA transfer enabled", hwAttrs->baseAddr); in UARTCC32XXDMA_configDMA()
804 hwAttrs->baseAddr, (uintptr_t)(object->writeBuf), in UARTCC32XXDMA_configDMA()
809 hwAttrs->baseAddr, (uintptr_t)(object->readBuf), in UARTCC32XXDMA_configDMA()
828 UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = ((UART_Handle)arg)->hwAttrs; in UARTCC32XXDMA_hwiIntFxn() local
835 status = MAP_UARTIntStatus(hwAttrs->baseAddr, false); in UARTCC32XXDMA_hwiIntFxn()
837 MAP_UARTIntDisable(hwAttrs->baseAddr, UART_INT_DMATX); in UARTCC32XXDMA_hwiIntFxn()
838 MAP_UARTIntClear(hwAttrs->baseAddr, UART_INT_DMATX); in UARTCC32XXDMA_hwiIntFxn()
842 MAP_UARTIntDisable(hwAttrs->baseAddr, UART_INT_DMARX); in UARTCC32XXDMA_hwiIntFxn()
843 MAP_UARTIntClear(hwAttrs->baseAddr, UART_INT_DMARX); in UARTCC32XXDMA_hwiIntFxn()
847 hwAttrs->baseAddr, status); in UARTCC32XXDMA_hwiIntFxn()
851 !MAP_uDMAChannelIsEnabled(hwAttrs->rxChannelIndex)) { in UARTCC32XXDMA_hwiIntFxn()
860 hwAttrs->baseAddr, object->readCount); in UARTCC32XXDMA_hwiIntFxn()
865 !MAP_uDMAChannelIsEnabled(hwAttrs->txChannelIndex)) { in UARTCC32XXDMA_hwiIntFxn()
877 hwAttrs->baseAddr, object->writeCount); in UARTCC32XXDMA_hwiIntFxn()
904 UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in initHw() local
914 MAP_UARTFIFOLevelSet(hwAttrs->baseAddr, UART_FIFO_TX4_8, UART_FIFO_RX4_8); in initHw()
916 if (isFlowControlEnabled(hwAttrs)) { in initHw()
918 MAP_UARTFlowControlSet(hwAttrs->baseAddr, in initHw()
922 MAP_UARTFlowControlSet(hwAttrs->baseAddr, UART_FLOWCONTROL_NONE); in initHw()
926 MAP_UARTConfigSetExpClk(hwAttrs->baseAddr, in initHw()
933 MAP_UARTDMAEnable(hwAttrs->baseAddr, UART_DMA_TX | UART_DMA_RX); in initHw()
936 MAP_uDMAChannelAssign(hwAttrs->txChannelIndex); in initHw()
937 MAP_uDMAChannelAttributeDisable(hwAttrs->txChannelIndex, UDMA_ATTR_ALTSELECT); in initHw()
939 MAP_uDMAChannelAssign(hwAttrs->rxChannelIndex); in initHw()
940 MAP_uDMAChannelAttributeDisable(hwAttrs->rxChannelIndex, UDMA_ATTR_ALTSELECT); in initHw()
941 MAP_UARTEnable(hwAttrs->baseAddr); in initHw()
964 UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in readCancel() local
981 MAP_uDMAChannelDisable(hwAttrs->rxChannelIndex); in readCancel()
983 remainder = MAP_uDMAChannelSizeGet(hwAttrs->rxChannelIndex); in readCancel()
1032 UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in writeCancel() local
1043 MAP_uDMAChannelDisable(hwAttrs->txChannelIndex); in writeCancel()
1045 remainder = MAP_uDMAChannelSizeGet(hwAttrs->txChannelIndex); in writeCancel()
1112 UARTCC32XXDMA_HWAttrsV1 const *hwAttrs; in writeFinishedDoCallback() local
1116 hwAttrs = handle->hwAttrs; in writeFinishedDoCallback()
1123 while (MAP_UARTBusy(hwAttrs->baseAddr)); in writeFinishedDoCallback()
1132 hwAttrs->baseAddr, object->writeCount); in writeFinishedDoCallback()