Lines Matching refs:hwAttrs
102 I2CCC32XX_HWAttrsV1 const *hwAttrs);
104 I2CCC32XX_HWAttrsV1 const *hwAttrs);
106 I2CCC32XX_HWAttrsV1 const *hwAttrs, I2C_Transaction *transaction);
108 I2CCC32XX_HWAttrsV1 const *hwAttrs);
137 I2CCC32XX_HWAttrsV1 const *hwAttrs) in I2CCC32XX_fillTransmitFifo() argument
140 I2CFIFODataPutNonBlocking(hwAttrs->baseAddr, *(object->writeBuf))) { in I2CCC32XX_fillTransmitFifo()
147 I2CMasterIntClearEx(hwAttrs->baseAddr, I2C_MASTER_INT_TX_FIFO_EMPTY); in I2CCC32XX_fillTransmitFifo()
157 I2CCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in I2CCC32XX_initHw() local
171 MAP_I2CMasterIntDisableEx(hwAttrs->baseAddr, 0xFFFFFFFF); in I2CCC32XX_initHw()
177 MAP_I2CMasterInitExpClk(hwAttrs->baseAddr, freq.lo, in I2CCC32XX_initHw()
181 MAP_I2CTxFIFOFlush(hwAttrs->baseAddr); in I2CCC32XX_initHw()
182 MAP_I2CRxFIFOFlush(hwAttrs->baseAddr); in I2CCC32XX_initHw()
185 MAP_I2CTxFIFOConfigSet(hwAttrs->baseAddr, I2C_FIFO_CFG_TX_MASTER); in I2CCC32XX_initHw()
186 MAP_I2CRxFIFOConfigSet(hwAttrs->baseAddr, I2C_FIFO_CFG_RX_MASTER); in I2CCC32XX_initHw()
189 MAP_I2CMasterIntClearEx(hwAttrs->baseAddr, 0xFFFFFFFF); in I2CCC32XX_initHw()
215 I2CCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in I2CCC32XX_completeTransfer() local
218 I2CMasterIntDisableEx(hwAttrs->baseAddr, 0xFFFFFFFF); in I2CCC32XX_completeTransfer()
219 I2CMasterIntClearEx(hwAttrs->baseAddr, 0xFFFFFFFF); in I2CCC32XX_completeTransfer()
279 (I2CCC32XX_HWAttrsV1 const *)handle->hwAttrs, object->headPtr); in I2CCC32XX_completeTransfer()
303 I2CCC32XX_HWAttrsV1 const *hwAttrs = ((I2C_Handle)arg)->hwAttrs; in I2CCC32XX_hwiFxn() local
307 intStatus = I2CMasterIntStatusEx(hwAttrs->baseAddr, true); in I2CCC32XX_hwiFxn()
308 I2CMasterIntClearEx(hwAttrs->baseAddr, intStatus); in I2CCC32XX_hwiFxn()
313 uint32_t status = HWREG(hwAttrs->baseAddr + I2C_O_MCS); in I2CCC32XX_hwiFxn()
341 HWREG(hwAttrs->baseAddr + I2C_O_MCS) = I2C_MCS_STOP; in I2CCC32XX_hwiFxn()
352 I2CCC32XX_primeWriteBurst(object, hwAttrs); in I2CCC32XX_hwiFxn()
355 I2CCC32XX_fillTransmitFifo(object, hwAttrs); in I2CCC32XX_hwiFxn()
362 I2CMasterIntDisableEx(hwAttrs->baseAddr, in I2CCC32XX_hwiFxn()
366 I2CCC32XX_primeReadBurst(object, hwAttrs); in I2CCC32XX_hwiFxn()
370 !(HWREG(hwAttrs->baseAddr + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE)) { in I2CCC32XX_hwiFxn()
372 I2CCC32XX_readRecieveFifo(object, hwAttrs); in I2CCC32XX_hwiFxn()
376 I2CCC32XX_primeReadBurst(object, hwAttrs); in I2CCC32XX_hwiFxn()
387 uint32_t fifoStatus = I2CFIFOStatus(hwAttrs->baseAddr) & in I2CCC32XX_hwiFxn()
405 I2CCC32XX_HWAttrsV1 const *hwAttrs) in I2CCC32XX_primeReadBurst() argument
410 I2CMasterSlaveAddrSet(hwAttrs->baseAddr, in I2CCC32XX_primeReadBurst()
430 I2CCC32XX_updateReg(hwAttrs->baseAddr + I2C_O_FIFOCTL, in I2CCC32XX_primeReadBurst()
434 I2CCC32XX_updateReg(hwAttrs->baseAddr + I2C_O_FIFOCTL, in I2CCC32XX_primeReadBurst()
438 I2CMasterBurstLengthSet(hwAttrs->baseAddr, object->burstCount); in I2CCC32XX_primeReadBurst()
455 I2CMasterIntEnableEx(hwAttrs->baseAddr, I2C_MASTER_INT_RX_FIFO_REQ | in I2CCC32XX_primeReadBurst()
458 HWREG(hwAttrs->baseAddr + I2C_O_MCS) = command; in I2CCC32XX_primeReadBurst()
465 I2CCC32XX_HWAttrsV1 const *hwAttrs) in I2CCC32XX_primeWriteBurst() argument
470 I2CMasterSlaveAddrSet(hwAttrs->baseAddr, in I2CCC32XX_primeWriteBurst()
482 I2CMasterBurstLengthSet(hwAttrs->baseAddr, in I2CCC32XX_primeWriteBurst()
500 I2CCC32XX_fillTransmitFifo(object, hwAttrs); in I2CCC32XX_primeWriteBurst()
503 I2CMasterIntEnableEx(hwAttrs->baseAddr, I2C_MASTER_INT_TX_FIFO_EMPTY in I2CCC32XX_primeWriteBurst()
507 HWREG(hwAttrs->baseAddr + I2C_O_MCS) = command; in I2CCC32XX_primeWriteBurst()
514 I2CCC32XX_HWAttrsV1 const *hwAttrs, I2C_Transaction *transaction) in I2CCC32XX_primeTransfer() argument
538 I2CTxFIFOFlush(hwAttrs->baseAddr); in I2CCC32XX_primeTransfer()
539 I2CRxFIFOFlush(hwAttrs->baseAddr); in I2CCC32XX_primeTransfer()
542 if (I2CMasterBusBusy(hwAttrs->baseAddr)) in I2CCC32XX_primeTransfer()
549 I2CCC32XX_primeWriteBurst(object, hwAttrs); in I2CCC32XX_primeTransfer()
553 I2CCC32XX_primeReadBurst(object, hwAttrs); in I2CCC32XX_primeTransfer()
563 I2CCC32XX_HWAttrsV1 const *hwAttrs) in I2CCC32XX_readRecieveFifo() argument
567 I2CFIFODataGetNonBlocking(hwAttrs->baseAddr, object->readBuf)) { in I2CCC32XX_readRecieveFifo()
573 I2CMasterIntClearEx(hwAttrs->baseAddr, I2C_MASTER_INT_RX_FIFO_REQ); in I2CCC32XX_readRecieveFifo()
591 I2CCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in I2CCC32XX_cancel() local
607 MAP_I2CMasterControl(hwAttrs->baseAddr, I2C_MASTER_CMD_BURST_SEND_FINISH); in I2CCC32XX_cancel()
621 I2CCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in I2CCC32XX_close() local
628 MAP_I2CMasterIntDisableEx(hwAttrs->baseAddr, I2CCC32XX_TRANSFER_INTS); in I2CCC32XX_close()
631 MAP_I2CMasterDisable(hwAttrs->baseAddr); in I2CCC32XX_close()
639 padRegister = (PinToPadGet((hwAttrs->clkPin) & 0xff)<<2) + PAD_CONFIG_BASE; in I2CCC32XX_close()
641 padRegister = (PinToPadGet((hwAttrs->dataPin) & 0xff)<<2) + PAD_CONFIG_BASE; in I2CCC32XX_close()
677 I2CCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in I2CCC32XX_open() local
708 MAP_I2CMasterDisable(hwAttrs->baseAddr); in I2CCC32XX_open()
709 HwiP_clearInterrupt(hwAttrs->intNum); in I2CCC32XX_open()
711 pin = hwAttrs->clkPin & 0xff; in I2CCC32XX_open()
712 mode = (hwAttrs->clkPin >> 8) & 0xff; in I2CCC32XX_open()
715 pin = hwAttrs->dataPin & 0xff; in I2CCC32XX_open()
716 mode = (hwAttrs->dataPin >> 8) & 0xff; in I2CCC32XX_open()
724 hwiParams.priority = hwAttrs->intPriority; in I2CCC32XX_open()
725 object->hwiHandle = HwiP_create(hwAttrs->intNum, I2CCC32XX_hwiFxn, in I2CCC32XX_open()
800 I2CCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; in I2CCC32XX_transfer() local
893 HwiP_disableInterrupt(hwAttrs->intNum); in I2CCC32XX_transfer()
894 ret = I2CCC32XX_primeTransfer(object, hwAttrs, transaction); in I2CCC32XX_transfer()
895 HwiP_enableInterrupt(hwAttrs->intNum); in I2CCC32XX_transfer()