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Searched refs:Timers (Results 1 – 9 of 9) sorted by relevance

/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_hrtim.c6401 uint32_t Timers) in HAL_HRTIM_WaveformCountStart() argument
6404 assert_param(IS_HRTIM_TIMERID(Timers)); in HAL_HRTIM_WaveformCountStart()
6412 hhrtim->Instance->sMasterRegs.MCR |= (Timers); in HAL_HRTIM_WaveformCountStart()
6439 uint32_t Timers) in HAL_HRTIM_WaveformCountStop() argument
6442 assert_param(IS_HRTIM_TIMERID(Timers)); in HAL_HRTIM_WaveformCountStop()
6450 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers); in HAL_HRTIM_WaveformCountStop()
6480 uint32_t Timers) in HAL_HRTIM_WaveformCountStart_IT() argument
6485 assert_param(IS_HRTIM_TIMERID(Timers)); in HAL_HRTIM_WaveformCountStart_IT()
6496 if ((Timers & HRTIM_TIMERID_MASTER) != 0U) in HAL_HRTIM_WaveformCountStart_IT()
6507 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U) in HAL_HRTIM_WaveformCountStart_IT()
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/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_hrtim.c5124 uint32_t Timers) in HAL_HRTIM_WaveformCountStart() argument
5127 assert_param(IS_HRTIM_TIMERID(Timers)); in HAL_HRTIM_WaveformCountStart()
5135 hhrtim->Instance->sMasterRegs.MCR |= (Timers); in HAL_HRTIM_WaveformCountStart()
5161 uint32_t Timers) in HAL_HRTIM_WaveformCountStop() argument
5164 assert_param(IS_HRTIM_TIMERID(Timers)); in HAL_HRTIM_WaveformCountStop()
5172 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers); in HAL_HRTIM_WaveformCountStop()
5201 uint32_t Timers) in HAL_HRTIM_WaveformCountStart_IT() argument
5206 assert_param(IS_HRTIM_TIMERID(Timers)); in HAL_HRTIM_WaveformCountStart_IT()
5217 if ((Timers & HRTIM_TIMERID_MASTER) != 0U) in HAL_HRTIM_WaveformCountStart_IT()
5228 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U) in HAL_HRTIM_WaveformCountStart_IT()
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/hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_hal_hrtim.c5269 uint32_t Timers) in HAL_HRTIM_WaveformCountStart() argument
5272 assert_param(IS_HRTIM_TIMERID(Timers)); in HAL_HRTIM_WaveformCountStart()
5280 hhrtim->Instance->sMasterRegs.MCR |= (Timers); in HAL_HRTIM_WaveformCountStart()
5306 uint32_t Timers) in HAL_HRTIM_WaveformCountStop() argument
5309 assert_param(IS_HRTIM_TIMERID(Timers)); in HAL_HRTIM_WaveformCountStop()
5317 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers); in HAL_HRTIM_WaveformCountStop()
5346 uint32_t Timers) in HAL_HRTIM_WaveformCountStart_IT() argument
5351 assert_param(IS_HRTIM_TIMERID(Timers)); in HAL_HRTIM_WaveformCountStart_IT()
5362 if ((Timers & HRTIM_TIMERID_MASTER) != 0U) in HAL_HRTIM_WaveformCountStart_IT()
5373 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U) in HAL_HRTIM_WaveformCountStart_IT()
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/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_hrtim.h3474 uint32_t Timers);
3477 uint32_t Timers);
3480 uint32_t Timers);
3483 uint32_t Timers);
3486 uint32_t Timers);
3489 uint32_t Timers);
3507 uint32_t Timers);
3510 uint32_t Timers);
3518 uint32_t Timers);
3521 uint32_t Timers);
Dstm32h7xx_ll_hrtim.h1550 __STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) in LL_HRTIM_SuspendUpdate() argument
1552 SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK)); in LL_HRTIM_SuspendUpdate()
1574 __STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) in LL_HRTIM_ResumeUpdate() argument
1576 CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK)); in LL_HRTIM_ResumeUpdate()
1598 __STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) in LL_HRTIM_ForceUpdate() argument
1600 SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK)); in LL_HRTIM_ForceUpdate()
1621 __STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers) in LL_HRTIM_CounterReset() argument
1623 …SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_C… in LL_HRTIM_CounterReset()
2499 __STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers) in LL_HRTIM_TIM_CounterEnable() argument
2501 SET_BIT(HRTIMx->sMasterRegs.MCR, Timers); in LL_HRTIM_TIM_CounterEnable()
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/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_hrtim.h3513 uint32_t Timers);
3516 uint32_t Timers);
3519 uint32_t Timers);
3522 uint32_t Timers);
3525 uint32_t Timers);
3528 uint32_t Timers);
3546 uint32_t Timers);
3549 uint32_t Timers);
3557 uint32_t Timers);
3560 uint32_t Timers);
Dstm32f3xx_ll_hrtim.h1579 __STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) in LL_HRTIM_SuspendUpdate() argument
1581 SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK)); in LL_HRTIM_SuspendUpdate()
1603 __STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) in LL_HRTIM_ResumeUpdate() argument
1605 CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK)); in LL_HRTIM_ResumeUpdate()
1627 __STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) in LL_HRTIM_ForceUpdate() argument
1629 SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK)); in LL_HRTIM_ForceUpdate()
1650 __STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers) in LL_HRTIM_CounterReset() argument
1652 …SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_C… in LL_HRTIM_CounterReset()
2559 __STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers) in LL_HRTIM_TIM_CounterEnable() argument
2561 SET_BIT(HRTIMx->sMasterRegs.MCR, Timers); in LL_HRTIM_TIM_CounterEnable()
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/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_hrtim.h4870 uint32_t Timers);
4888 uint32_t Timers);
4891 uint32_t Timers);
4968 uint32_t Timers);
4971 uint32_t Timers);
4974 uint32_t Timers);
4977 uint32_t Timers);
4980 uint32_t Timers);
4983 uint32_t Timers);
5001 uint32_t Timers);
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Dstm32g4xx_ll_hrtim.h2238 __STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) in LL_HRTIM_SuspendUpdate() argument
2242 SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK)); in LL_HRTIM_SuspendUpdate()
2266 __STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) in LL_HRTIM_ResumeUpdate() argument
2268 CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK)); in LL_HRTIM_ResumeUpdate()
2292 __STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) in LL_HRTIM_ForceUpdate() argument
2294 SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK)); in LL_HRTIM_ForceUpdate()
2317 __STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers) in LL_HRTIM_CounterReset() argument
2319 …SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_C… in LL_HRTIM_CounterReset()
3674 __STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers) in LL_HRTIM_TIM_CounterEnable() argument
3676 SET_BIT(HRTIMx->sMasterRegs.MCR, Timers); in LL_HRTIM_TIM_CounterEnable()
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