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Searched refs:TIM_DTR2_DTGF_Pos (Results 1 – 25 of 44) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9047 #define TIM_DTR2_DTGF_Pos (0U) macro
9048 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F…
9050 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001…
9051 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002…
9052 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004…
9053 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008…
9054 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010…
9055 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020…
9056 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040…
9057 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080…
Dstm32wba52xx.h13215 #define TIM_DTR2_DTGF_Pos (0U) macro
13216 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F…
13218 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001…
13219 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002…
13220 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004…
13221 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008…
13222 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010…
13223 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020…
13224 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040…
13225 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080…
Dstm32wba54xx.h13923 #define TIM_DTR2_DTGF_Pos (0U) macro
13924 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F…
13926 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001…
13927 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002…
13928 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004…
13929 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008…
13930 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010…
13931 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020…
13932 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040…
13933 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080…
Dstm32wba5mxx.h13941 #define TIM_DTR2_DTGF_Pos (0U) macro
13942 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F…
13944 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001…
13945 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002…
13946 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004…
13947 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008…
13948 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010…
13949 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020…
13950 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040…
13951 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080…
Dstm32wba55xx.h13941 #define TIM_DTR2_DTGF_Pos (0U) macro
13942 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F…
13944 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001…
13945 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002…
13946 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004…
13947 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008…
13948 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010…
13949 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020…
13950 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040…
13951 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080…
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h10226 #define TIM_DTR2_DTGF_Pos (0U) macro
10227 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
10229 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
10230 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
10231 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
10232 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
10233 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
10234 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
10235 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
10236 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
Dstm32g411xc.h10444 #define TIM_DTR2_DTGF_Pos (0U) macro
10445 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
10447 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
10448 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
10449 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
10450 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
10451 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
10452 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
10453 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
10454 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
Dstm32g441xx.h11010 #define TIM_DTR2_DTGF_Pos (0U) macro
11011 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
11013 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
11014 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
11015 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
11016 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
11017 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
11018 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
11019 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
11020 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
Dstm32gbk1cb.h10752 #define TIM_DTR2_DTGF_Pos (0U) macro
10753 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
10755 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
10756 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
10757 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
10758 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
10759 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
10760 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
10761 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
10762 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
Dstm32g431xx.h10780 #define TIM_DTR2_DTGF_Pos (0U) macro
10781 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
10783 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
10784 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
10785 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
10786 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
10787 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
10788 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
10789 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
10790 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
Dstm32g4a1xx.h11520 #define TIM_DTR2_DTGF_Pos (0U) macro
11521 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
11523 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
11524 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
11525 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
11526 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
11527 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
11528 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
11529 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
11530 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
Dstm32g491xx.h11290 #define TIM_DTR2_DTGF_Pos (0U) macro
11291 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
11293 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
11294 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
11295 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
11296 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
11297 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
11298 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
11299 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
11300 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
Dstm32g473xx.h12081 #define TIM_DTR2_DTGF_Pos (0U) macro
12082 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
12084 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
12085 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
12086 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
12087 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
12088 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
12089 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
12090 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
12091 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
Dstm32g471xx.h11513 #define TIM_DTR2_DTGF_Pos (0U) macro
11514 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
11516 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
11517 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
11518 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
11519 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
11520 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
11521 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
11522 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
11523 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
Dstm32g483xx.h12311 #define TIM_DTR2_DTGF_Pos (0U) macro
12312 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
12314 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
12315 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
12316 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
12317 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
12318 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
12319 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
12320 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
12321 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
Dstm32g414xx.h14492 #define TIM_DTR2_DTGF_Pos (0U) macro
14493 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
14495 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
14496 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
14497 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
14498 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
14499 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
14500 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
14501 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
14502 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
Dstm32g474xx.h15660 #define TIM_DTR2_DTGF_Pos (0U) macro
15661 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
15663 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
15664 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
15665 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
15666 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
15667 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
15668 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
15669 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
15670 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
Dstm32g484xx.h15890 #define TIM_DTR2_DTGF_Pos (0U) macro
15891 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
15893 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
15894 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
15895 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
15896 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
15897 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
15898 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
15899 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
15900 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h7489 #define TIM_DTR2_DTGF_Pos (0U) macro
7490 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F…
7492 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001…
7493 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002…
7494 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004…
7495 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008…
7496 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010…
7497 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020…
7498 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040…
7499 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080…
Dstm32h523xx.h9928 #define TIM_DTR2_DTGF_Pos (0U) macro
9929 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F…
9931 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001…
9932 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002…
9933 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004…
9934 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008…
9935 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010…
9936 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020…
9937 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040…
9938 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080…
Dstm32h562xx.h10654 #define TIM_DTR2_DTGF_Pos (0U) macro
10655 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F…
10657 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001…
10658 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002…
10659 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004…
10660 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008…
10661 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010…
10662 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020…
10663 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040…
10664 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080…
Dstm32h533xx.h10337 #define TIM_DTR2_DTGF_Pos (0U) macro
10338 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F…
10340 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001…
10341 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002…
10342 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004…
10343 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008…
10344 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010…
10345 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020…
10346 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040…
10347 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080…
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h11023 #define TIM_DTR2_DTGF_Pos (0U) macro
11024 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F…
11026 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001…
11027 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002…
11028 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004…
11029 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008…
11030 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010…
11031 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020…
11032 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040…
11033 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080…
Dstm32u535xx.h10623 #define TIM_DTR2_DTGF_Pos (0U) macro
10624 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F…
10626 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001…
10627 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002…
10628 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004…
10629 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008…
10630 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010…
10631 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020…
10632 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040…
10633 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080…
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h20321 #define TIM_DTR2_DTGF_Pos (0U) macro
20322 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F…
20324 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001…
20325 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002…
20326 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004…
20327 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008…
20328 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010…
20329 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020…
20330 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040…
20331 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080…

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