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Searched refs:TIM_AF1_ETRSEL_3 (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_hal_tim_ex.h115 #define TIM_TIM1_ETR_ADC2_AWD3 TIM_AF1_ETRSEL_3 …
124 #define TIM_TIM2_ETR_LCD_VSYNC TIM_AF1_ETRSEL_3 …
125 #define TIM_TIM2_ETR_TIM3_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) …
126 #define TIM_TIM2_ETR_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) …
127 #define TIM_TIM2_ETR_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) …
128 #define TIM_TIM2_ETR_ETH1_PPS (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) …
129 #define TIM_TIM2_ETR_USB1_SOF (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) …
130 #define TIM_TIM2_ETR_USB2_SOF (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_A…
137 #define TIM_TIM3_ETR_LCD_VSYNC TIM_AF1_ETRSEL_3 …
138 #define TIM_TIM3_ETR_TIM2_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) …
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Dstm32n6xx_ll_tim.h1054 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3 TIM_AF1_ETRSEL_3 …
1069 #define LL_TIM_TIM2_ETRSOURCE_LCD_VSYNC TIM_AF1_ETRSEL_3 …
1070 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) …
1071 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0…
1072 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) …
1073 #define LL_TIM_TIM2_ETRSOURCE_ETH1_PPS (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0…
1074 #define LL_TIM_TIM2_ETRSOURCE_USB1_SOF (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1…
1075 #define LL_TIM_TIM2_ETRSOURCE_USB2_SOF (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1…
1088 #define LL_TIM_TIM3_ETRSOURCE_LCD_VSYNC TIM_AF1_ETRSEL_3 …
1089 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) …
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/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_tim_ex.h115 #define TIM_TIM1_ETR_ADC2_AWD3 (TIM_AF1_ETRSEL_3) /*!…
124 #define TIM_TIM2_ETR_LTDC_VSYNC (TIM_AF1_ETRSEL_3) /*!…
125 #define TIM_TIM2_ETR_TIM3_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) /*!…
126 #define TIM_TIM2_ETR_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!…
127 #define TIM_TIM2_ETR_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!…
128 #define TIM_TIM2_ETR_ETH_PPS (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!…
135 #define TIM_TIM3_ETR_LTDC_VSYNC (TIM_AF1_ETRSEL_3) /*!…
136 #define TIM_TIM3_ETR_TIM2_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!…
137 #define TIM_TIM3_ETR_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!…
138 #define TIM_TIM3_ETR_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!…
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Dstm32h7rsxx_ll_tim.h1038 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3 TIM_AF1_ETRSEL_3 …
1053 #define LL_TIM_TIM2_ETRSOURCE_LTDC_VSYNC TIM_AF1_ETRSEL_3 …
1054 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) …
1055 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0…
1056 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) …
1057 #define LL_TIM_TIM2_ETRSOURCE_ETH_PPS (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0…
1070 #define LL_TIM_TIM3_ETRSOURCE_LTDC_VSYNC TIM_AF1_ETRSEL_3 …
1071 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) …
1072 #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0…
1073 #define LL_TIM_TIM3_ETRSOURCE_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) …
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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_hal_tim_ex.h113 #define TIM_TIM1_ETR_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!…
114 #define TIM_TIM1_ETR_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!…
115 #define TIM_TIM1_ETR_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!…
121 #define TIM_TIM2_ETR_TIM3_ETR TIM_AF1_ETRSEL_3 /*!…
122 #define TIM_TIM2_ETR_LSE (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!…
128 #define TIM_TIM3_ETR_TIM2_ETR TIM_AF1_ETRSEL_3 /*!…
129 #define TIM_TIM3_ETR_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1| TIM_AF1_ETRSEL_0) /*!…
130 #define TIM_TIM3_ETR_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!…
131 #define TIM_TIM3_ETR_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!…
Dstm32wbaxx_ll_tim.h1030 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) …
1031 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) …
1032 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) …
1046 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM_AF1_ETRSEL_3 …
1047 #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)…
1061 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM_AF1_ETRSEL_3 …
1062 #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0)…
1063 #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) …
1064 #define LL_TIM_TIM3_ETRSOURCE_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0)…
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h5833 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
Dstm32c031xx.h5996 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
Dstm32c071xx.h6500 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h8959 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000… macro
Dstm32wba52xx.h13127 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000… macro
Dstm32wba54xx.h13835 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000… macro
Dstm32wba5mxx.h13853 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000… macro
Dstm32wba55xx.h13853 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000… macro
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h7890 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
Dstm32u083xx.h8827 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
Dstm32u073xx.h8557 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h20280 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
Dstm32h7s7xx.h21595 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
Dstm32h7s3xx.h21163 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
Dstm32h7r7xx.h20710 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h36807 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
Dstm32n657xx.h38446 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
Dstm32n655xx.h38057 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro
Dstm32n647xx.h37196 #define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */ macro