Home
last modified time | relevance | path

Searched refs:SYSCFG_ITLINE11_SR_DMA1_CH5 (Results 1 – 25 of 26) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_ll_system.h861 #if defined(SYSCFG_ITLINE11_SR_DMA1_CH5)
869 …return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1… in LL_SYSCFG_IsActiveFlag_DMA1_CH5()
Dstm32c0xx_hal.h306 #if defined(SYSCFG_ITLINE11_SR_DMA1_CH5)
307 #define HAL_ITLINE_DMA1_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5) …
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_ll_system.h1076 #if defined(SYSCFG_ITLINE11_SR_DMA1_CH5)
1084 …return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_… in LL_SYSCFG_IsActiveFlag_DMA1_CH5()
Dstm32f0xx_hal.h215 …E_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< …
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_system.h899 #if defined(SYSCFG_ITLINE11_SR_DMA1_CH5)
907 …return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1… in LL_SYSCFG_IsActiveFlag_DMA1_CH5()
Dstm32g0xx_hal.h289 #define HAL_ITLINE_DMA1_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5) …
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_ll_system.h752 …return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1… in LL_SYSCFG_IsActiveFlag_DMA1_CH5()
Dstm32u0xx_hal.h260 #define HAL_ITLINE_DMA1_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5) …
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c071xx.h5737 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DM… macro
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h5685 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 … macro
Dstm32g050xx.h5731 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 … macro
Dstm32g070xx.h5864 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 … macro
Dstm32g031xx.h5937 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 … macro
Dstm32g041xx.h6235 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 … macro
Dstm32g051xx.h6312 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 … macro
Dstm32g061xx.h6610 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 … macro
Dstm32g071xx.h6687 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 … macro
Dstm32g081xx.h6985 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 … macro
Dstm32g0b0xx.h7014 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 … macro
Dstm32g0c1xx.h8469 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 … macro
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h7045 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Ch… macro
Dstm32u083xx.h7949 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Ch… macro
Dstm32u073xx.h7682 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Ch… macro
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f091xc.h9758 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 … macro
Dstm32f098xx.h9725 #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 … macro

12