1 /**
2 ******************************************************************************
3 * @file stm32u0xx_ll_system.h
4 * @author GPM Application Team
5 * @brief Header file of SYSTEM LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL SYSTEM driver contains a set of generic APIs that can be
12 used by user:
13 (+) Some of the FLASH features need to be handled in the SYSTEM file.
14 (+) Access to DBG registers
15 (+) Access to SYSCFG registers
16 (+) Access to VREFBUF registers
17
18 @endverbatim
19 ******************************************************************************
20 * @attention
21 *
22 * Copyright (c) 2023 STMicroelectronics.
23 * All rights reserved.
24 *
25 * This software is licensed under terms that can be found in the LICENSE file in
26 * the root directory of this software component.
27 * If no LICENSE file comes with this software, it is provided AS-IS.
28 ******************************************************************************
29 */
30
31 /* Define to prevent recursive inclusion -------------------------------------*/
32 #ifndef STM32U0xx_LL_SYSTEM_H
33 #define STM32U0xx_LL_SYSTEM_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32u0xx.h"
41
42 /** @addtogroup STM32U0xx_LL_Driver
43 * @{
44 */
45
46 #if defined (FLASH) || defined (SYSCFG) || defined (DBG)
47
48 /** @defgroup SYSTEM_LL SYSTEM
49 * @{
50 */
51
52 /* Private types -------------------------------------------------------------*/
53 /* Private variables ---------------------------------------------------------*/
54
55 /* Private constants ---------------------------------------------------------*/
56 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
57 * @{
58 */
59
60 /**
61 * @}
62 */
63
64 /* Private macros ------------------------------------------------------------*/
65
66 /* Exported types ------------------------------------------------------------*/
67 /* Exported constants --------------------------------------------------------*/
68 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
69 * @{
70 */
71
72 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
73 * @{
74 */
75 #define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
76 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
77 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x00000000 */
78 /**
79 * @}
80 */
81
82 /** @defgroup SYSTEM_LL_EC_PIN_RMP SYSCFG PIN RMP
83 * @{
84 */
85 #define LL_SYSCFG_PIN_RMP_PA11 SYSCFG_CFGR1_PA11_RMP /*!< PA11 pin behaves as PA9 pin */
86 #define LL_SYSCFG_PIN_RMP_PA12 SYSCFG_CFGR1_PA12_RMP /*!< PA12 pin behaves as PA10 pin */
87 /**
88 * @}
89 */
90
91 /** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation
92 * @{
93 */
94 #define LL_SYSCFG_IR_MOD_TIM16 0x00000000U /*!< 00: Timer16 is selected as IRDA Modulation envelope source */
95 #define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IRDA Modulation envelope source */
96 #define LL_SYSCFG_IR_MOD_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IRDA Modulation envelope source */
97
98 /**
99 * @}
100 */
101 /** @defgroup SYSTEM_LL_EC_IR_POL SYSCFG IR Polarity
102 * @{
103 */
104 #define LL_SYSCFG_IR_POL_NOT_INVERTED 0x00000000U /*!< 0: Output of IRDA (IROut) not inverted */
105 #define LL_SYSCFG_IR_POL_INVERTED (SYSCFG_CFGR1_IR_POL) /*!< 1: Output of IRDA (IROut) inverted */
106 /**
107 * @}
108 */
109
110 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
111 * @{
112 */
113 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< I2C PB6 Fast mode plus */
114 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< I2C PB7 Fast mode plus */
115 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< I2C PB8 Fast mode plus */
116 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< I2C PB9 Fast mode plus */
117 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast Mode Plus on PA9 */
118 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast Mode Plus on PA10 */
119 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 */
120 /**
121 * @}
122 */
123
124 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
125 * @{
126 */
127 #define LL_SYSCFG_TIMBREAK_CCL SYSCFG_CFGR2_CCL /*!< Enables and locks the connection of Cortex-M0+ LOCKUP(HardFault)
128 output of TIM1/15/16 Break Input */
129 #define LL_SYSCFG_TIMBREAK_SPL SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM1 parity error signal connection
130 to TIM1/15/16 Break input */
131 #define LL_SYSCFG_TIMBREAK_PVDL SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection to TIM1/15/16 Break input,
132 and also the PVDE and PLS bits of the Power
133 Control Interface */
134 #define LL_SYSCFG_TIMBREAK_ECCL SYSCFG_CFGR2_ECCL /*!< Enables and locks the flash ECC 2-bit error detection signal connection
135 to TIM1/15/16 Break input */
136 #define LL_SYSCFG_TIMBREAK_BKPL SYSCFG_CFGR2_BKPL /*!< Enables and locks the SRAM2 parity error signal connection */
137 /**
138 * @}
139 */
140
141 /** @defgroup SYSTEM_LL_EC_TSCIOCONTROL SYSCFG TSC IOCONTROL
142 * @{
143 */
144 #define LL_SYSCFG_TSCIOCONTROL_REG 0x00000000U /*!< I/O configured through the corresponding control register */
145 #define LL_SYSCFG_TSCIOCONTROL_ANALOG SYSCFG_TSCCR_TSCIOCTRL /*!< I/O configured as analog when TSC AF is activated */
146
147 /**
148 * @}
149 */
150
151 /** @defgroup SYSTEM_LL_EC_APB1_STOP_IP DBGMCU APB1 STOP IP
152 * @{
153 */
154 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APBFZ1_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
155 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APBFZ1_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
156 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APBFZ1_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
157 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APBFZ1_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
158 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APBFZ1_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
159 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APBFZ1_DBG_RTC_STOP /*!< RTC Calendar frozen when core is halted */
160 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APBFZ1_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
161 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APBFZ1_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
162 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APBFZ1_DBG_I2C3_STOP /*!< I2C3 counter stopped when Core is halted */
163 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APBFZ1_DBG_I2C1_STOP /*!< I2C1 counter stopped when Core is halted */
164 #define LL_DBGMCU_APB1_GRP1_LPTIM2_STOP DBGMCU_APBFZ1_DBG_LPTIM2_STOP /*!< LPTIM2 counter stopped when Core is halted */
165 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APBFZ1_DBG_LPTIM1_STOP /*!< LPTIM1 counter stopped when Core is halted */
166 /**
167 * @}
168 */
169
170 /** @defgroup SYSTEM_LL_EC_APB1_STOP_IP DBGMCU APB1 STOP IP
171 * @{
172 */
173 #define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBGMCU_APBFZ2_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
174 #define LL_DBGMCU_APB1_GRP2_TIM14_STOP DBGMCU_APBFZ2_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
175 #define LL_DBGMCU_APB1_GRP2_TIM15_STOP DBGMCU_APBFZ2_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
176 #define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBGMCU_APBFZ2_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
177 #define LL_DBGMCU_APB1_GRP2_LPTIM3_STOP DBGMCU_APBFZ2_DBG_LPTIM3_STOP /*!< LPTIM3 counter stopped when core is halted */
178 /**
179 * @}
180 */
181
182 #if defined(VREFBUF)
183 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
184 * @{
185 */
186 #define LL_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0 (VREF_OUT1) */
187 #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
188 /**
189 * @}
190 */
191 #endif /* VREFBUF */
192
193 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
194 * @{
195 */
196 #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
197 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
198 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
199 /**
200 * @}
201 */
202
203 /** @defgroup SYSTEM_LL_EC_KEY FLASH KEY
204 * @{
205 */
206 #define FLASH_KEY1 0x45670123U /*!< Flash Unlock key1 */
207 #define FLASH_KEY2 0xCDEF89ABU /*!< Flash Unlock key2 */
208
209 /**
210 * @}
211 */
212
213 /**
214 * @}
215 */
216
217 /* Exported macro ------------------------------------------------------------*/
218
219 /* Exported functions --------------------------------------------------------*/
220 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
221 * @{
222 */
223
224 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
225 * @{
226 */
227
228 /**
229 * @brief Set memory mapping at address 0x00000000
230 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
231 * @param Memory This parameter can be one of the following values:
232 * @arg @ref LL_SYSCFG_REMAP_FLASH
233 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
234 * @arg @ref LL_SYSCFG_REMAP_SRAM
235 * @retval None
236 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)237 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
238 {
239 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
240 }
241
242 /**
243 * @brief Get memory mapping at address 0x00000000
244 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
245 * @retval Returned value can be one of the following values:
246 * @arg @ref LL_SYSCFG_REMAP_FLASH
247 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
248 * @arg @ref LL_SYSCFG_REMAP_SRAM
249 */
LL_SYSCFG_GetRemapMemory(void)250 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
251 {
252 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
253 }
254
255 /**
256 * @brief Enable remap of a pin on different pad
257 * @rmtoll SYSCFG_CFGR1 PA11_RMP LL_SYSCFG_EnablePinRemap\n
258 * SYSCFG_CFGR1 PA12_RMP LL_SYSCFG_EnablePinRemap\n
259 * @param PinRemap This parameter can be a combination of the following values:
260 * @arg @ref LL_SYSCFG_PIN_RMP_PA11
261 * @arg @ref LL_SYSCFG_PIN_RMP_PA12
262 * @retval None
263 */
LL_SYSCFG_EnablePinRemap(uint32_t PinRemap)264 __STATIC_INLINE void LL_SYSCFG_EnablePinRemap(uint32_t PinRemap)
265 {
266 SET_BIT(SYSCFG->CFGR1, PinRemap);
267 }
268
269 /**
270 * @brief Enable remap of a pin on different pad
271 * @rmtoll SYSCFG_CFGR1 PA11_RMP LL_SYSCFG_DisablePinRemap\n
272 * SYSCFG_CFGR1 PA12_RMP LL_SYSCFG_DisablePinRemap\n
273 * @param PinRemap This parameter can be a combination of the following values:
274 * @arg @ref LL_SYSCFG_PIN_RMP_PA11
275 * @arg @ref LL_SYSCFG_PIN_RMP_PA12
276 * @retval None
277 */
LL_SYSCFG_DisablePinRemap(uint32_t PinRemap)278 __STATIC_INLINE void LL_SYSCFG_DisablePinRemap(uint32_t PinRemap)
279 {
280 CLEAR_BIT(SYSCFG->CFGR1, PinRemap);
281 }
282
283 /**
284 * @brief Set IR Modulation Envelope signal source.
285 * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal
286 * @param Source This parameter can be one of the following values:
287 * @arg @ref LL_SYSCFG_IR_MOD_TIM16
288 * @arg @ref LL_SYSCFG_IR_MOD_USART1
289 * @arg @ref LL_SYSCFG_IR_MOD_USART2
290 * @retval None
291 */
LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source)292 __STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source)
293 {
294 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source);
295 }
296
297 /**
298 * @brief Get IR Modulation Envelope signal source.
299 * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal
300 * @retval Returned value can be one of the following values:
301 * @arg @ref LL_SYSCFG_IR_MOD_TIM16
302 * @arg @ref LL_SYSCFG_IR_MOD_USART1
303 * @arg @ref LL_SYSCFG_IR_MOD_USART2
304 */
LL_SYSCFG_GetIRModEnvelopeSignal(void)305 __STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void)
306 {
307 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD));
308 }
309
310 /**
311 * @brief Set IR Output polarity.
312 * @rmtoll SYSCFG_CFGR1 IR_POL LL_SYSCFG_SetIRPolarity
313 * @param Polarity This parameter can be one of the following values:
314 * @arg @ref LL_SYSCFG_IR_POL_INVERTED
315 * @arg @ref LL_SYSCFG_IR_POL_NOT_INVERTED
316 * @retval None
317 */
LL_SYSCFG_SetIRPolarity(uint32_t Polarity)318 __STATIC_INLINE void LL_SYSCFG_SetIRPolarity(uint32_t Polarity)
319 {
320 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL, Polarity);
321 }
322
323 /**
324 * @brief Get IR Output polarity.
325 * @rmtoll SYSCFG_CFGR1 IR_POL LL_SYSCFG_GetIRPolarity
326 * @retval Returned value can be one of the following values:
327 * @arg @ref LL_SYSCFG_IR_POL_INVERTED
328 * @arg @ref LL_SYSCFG_IR_POL_NOT_INVERTED
329 */
LL_SYSCFG_GetIRPolarity(void)330 __STATIC_INLINE uint32_t LL_SYSCFG_GetIRPolarity(void)
331 {
332 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL));
333 }
334
335 /**
336 * @brief Enable I/O analog switch voltage booster.
337 * @note When voltage booster is enabled, I/O analog switches are supplied
338 * by a dedicated voltage booster, from VDD power domain. This is
339 * the recommended configuration with low VDDA voltage operation.
340 * @note The I/O analog switch voltage booster is relevant for peripherals
341 * using I/O in analog input: ADC, COMP.
342 * However, COMP and OPAMP inputs have a high impedance and
343 * voltage booster do not impact performance significantly.
344 * Therefore, the voltage booster is mainly intended for
345 * usage with ADC.
346 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
347 * @retval None
348 */
LL_SYSCFG_EnableAnalogBooster(void)349 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
350 {
351 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
352 }
353
354 /**
355 * @brief Disable I/O analog switch voltage booster.
356 * @note When voltage booster is enabled, I/O analog switches are supplied
357 * by a dedicated voltage booster, from VDD power domain. This is
358 * the recommended configuration with low VDDA voltage operation.
359 * @note The I/O analog switch voltage booster is relevant for peripherals
360 * using I/O in analog input: ADC, COMP.
361 * However, COMP and OPAMP inputs have a high impedance and
362 * voltage booster do not impact performance significantly.
363 * Therefore, the voltage booster is mainly intended for
364 * usage with ADC.
365 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
366 * @retval None
367 */
LL_SYSCFG_DisableAnalogBooster(void)368 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
369 {
370 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
371 }
372
373 /**
374 * @brief Enable the I2C fast mode plus driving capability.
375 * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n
376 * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n
377 * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n
378 * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n
379 * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n
380 * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus\n
381 * SYSCFG_CFGR1 I2C_FMP_I2C3 LL_SYSCFG_EnableFastModePlus\n
382 * @param ConfigFastModePlus This parameter can be a combination of the following values:
383 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
384 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
385 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
386 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
387 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9
388 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10
389 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
390 * @retval None
391 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)392 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
393 {
394 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
395 }
396
397 /**
398 * @brief Disable the I2C fast mode plus driving capability.
399 * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n
400 * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n
401 * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n
402 * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n
403 * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n
404 * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus\n
405 * SYSCFG_CFGR1 I2C_FMP_I2C3 LL_SYSCFG_DisableFastModePlus\n
406 * @param ConfigFastModePlus This parameter can be a combination of the following values:
407 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
408 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
409 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
410 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
411 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9
412 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10
413 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
414 * @retval None
415 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)416 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
417 {
418 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
419 }
420
421 /**
422 * @brief Check if Window watchdog interrupt occurred or not.
423 * @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG
424 * @retval State of bit (1 or 0).
425 */
LL_SYSCFG_IsActiveFlag_WWDG(void)426 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void)
427 {
428 return ((READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_WWDG) == (SYSCFG_ITLINE0_SR_WWDG)) ? 1UL : 0UL);
429 }
430
431 /**
432 * @brief Check if PVD supply monitoring interrupt occurred or not (EXTI line 16).
433 * @rmtoll SYSCFG_ITLINE1 SR_PVDOUT LL_SYSCFG_IsActiveFlag_PVDOUT
434 * @retval State of bit (1 or 0).
435 */
LL_SYSCFG_IsActiveFlag_PVDOUT(void)436 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void)
437 {
438 return ((READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT)) ? 1UL : 0UL);
439 }
440
441 #if defined(SYSCFG_ITLINE1_SR_PVMOUT1)
442 /**
443 * @brief Check if PVM supply monitoring interrupt occurred or not (EXTI line 19).
444 * @rmtoll SYSCFG_ITLINE1 SR_PVMOUT1 LL_SYSCFG_IsActiveFlag_PVMOUT1
445 * @retval State of bit (1 or 0).
446 */
LL_SYSCFG_IsActiveFlag_PVMOUT1(void)447 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVMOUT1(void)
448 {
449 return ((READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVMOUT1) == (SYSCFG_ITLINE1_SR_PVMOUT1)) ? 1UL : 0UL);
450 }
451 #endif /* SYSCFG_ITLINE1_SR_PVMOUT1 */
452
453 /**
454 * @brief Check if PVM supply monitoring interrupt occurred or not (EXTI line 20).
455 * @rmtoll SYSCFG_ITLINE1 SR_PVMOUT3 LL_SYSCFG_IsActiveFlag_PVMOUT3
456 * @retval State of bit (1 or 0).
457 */
LL_SYSCFG_IsActiveFlag_PVMOUT3(void)458 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVMOUT3(void)
459 {
460 return ((READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVMOUT3) == (SYSCFG_ITLINE1_SR_PVMOUT3)) ? 1UL : 0UL);
461 }
462
463 /**
464 * @brief Check if PVM supply monitoring interrupt occurred or not (EXTI line 21).
465 * @rmtoll SYSCFG_ITLINE1 SR_PVMOUT4 LL_SYSCFG_IsActiveFlag_PVMOUT4
466 * @retval State of bit (1 or 0).
467 */
LL_SYSCFG_IsActiveFlag_PVMOUT4(void)468 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVMOUT4(void)
469 {
470 return ((READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVMOUT4) == (SYSCFG_ITLINE1_SR_PVMOUT4)) ? 1UL : 0UL);
471 }
472
473 /**
474 * @brief Check if RTC Wake Up interrupt occurred or not (EXTI line 19).
475 * @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP LL_SYSCFG_IsActiveFlag_RTC_WAKEUP
476 * @retval State of bit (1 or 0).
477 */
LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void)478 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void)
479 {
480 return ((READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC) == (SYSCFG_ITLINE2_SR_RTC)) ? 1UL : 0UL);
481 }
482
483 /**
484 * @brief Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 21).
485 * @rmtoll SYSCFG_ITLINE2 SR_TAMPER LL_SYSCFG_IsActiveFlag_TAMPER
486 * @retval State of bit (1 or 0).
487 */
LL_SYSCFG_IsActiveFlag_TAMPER(void)488 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TAMPER(void)
489 {
490 return ((READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_TAMPER) == (SYSCFG_ITLINE2_SR_TAMPER)) ? 1UL : 0UL);
491 }
492
493 /**
494 * @brief Check if Flash interface interrupt occurred or not.
495 * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF
496 * @retval State of bit (1 or 0).
497 */
LL_SYSCFG_IsActiveFlag_FLASH_ITF(void)498 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void)
499 {
500 return ((READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF)) ? 1UL : 0UL);
501 }
502
503 /**
504 * @brief Check if Flash interface interrupt occurred or not.
505 * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ECC LL_SYSCFG_IsActiveFlag_FLASH_ECC
506 * @retval State of bit (1 or 0).
507 */
LL_SYSCFG_IsActiveFlag_FLASH_ECC(void)508 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ECC(void)
509 {
510 return ((READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ECC) == (SYSCFG_ITLINE3_SR_FLASH_ECC)) ? 1UL : 0UL);
511 }
512
513 /**
514 * @brief Check if Reset and clock control interrupt occurred or not.
515 * @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL
516 * @retval State of bit (1 or 0).
517 */
LL_SYSCFG_IsActiveFlag_CLK_CTRL(void)518 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void)
519 {
520 return ((READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_RCC) == (SYSCFG_ITLINE4_SR_RCC)) ? 1UL : 0UL);
521 }
522 #if defined(CRS)
523 /**
524 * @brief Check if Reset and clock control interrupt occurred or not.
525 * @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS
526 * @retval State of bit (1 or 0).
527 */
LL_SYSCFG_IsActiveFlag_CRS(void)528 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void)
529 {
530 return ((READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS)) ? 1UL : 0UL);
531 }
532 #endif /* CRS */
533 /**
534 * @brief Check if EXTI line 0 interrupt occurred or not.
535 * @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0
536 * @retval State of bit (1 or 0).
537 */
LL_SYSCFG_IsActiveFlag_EXTI0(void)538 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void)
539 {
540 return ((READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0)) ? 1UL : 0UL);
541 }
542
543 /**
544 * @brief Check if EXTI line 1 interrupt occurred or not.
545 * @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1
546 * @retval State of bit (1 or 0).
547 */
LL_SYSCFG_IsActiveFlag_EXTI1(void)548 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void)
549 {
550 return ((READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1)) ? 1UL : 0UL);
551 }
552
553 /**
554 * @brief Check if EXTI line 2 interrupt occurred or not.
555 * @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2
556 * @retval State of bit (1 or 0).
557 */
LL_SYSCFG_IsActiveFlag_EXTI2(void)558 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void)
559 {
560 return ((READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2)) ? 1UL : 0UL);
561 }
562
563 /**
564 * @brief Check if EXTI line 3 interrupt occurred or not.
565 * @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3
566 * @retval State of bit (1 or 0).
567 */
LL_SYSCFG_IsActiveFlag_EXTI3(void)568 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void)
569 {
570 return ((READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3)) ? 1UL : 0UL);
571 }
572
573 /**
574 * @brief Check if EXTI line 4 interrupt occurred or not.
575 * @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4
576 * @retval State of bit (1 or 0).
577 */
LL_SYSCFG_IsActiveFlag_EXTI4(void)578 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void)
579 {
580 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4)) ? 1UL : 0UL);
581 }
582
583 /**
584 * @brief Check if EXTI line 5 interrupt occurred or not.
585 * @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5
586 * @retval State of bit (1 or 0).
587 */
LL_SYSCFG_IsActiveFlag_EXTI5(void)588 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void)
589 {
590 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5)) ? 1UL : 0UL);
591 }
592
593 /**
594 * @brief Check if EXTI line 6 interrupt occurred or not.
595 * @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6
596 * @retval State of bit (1 or 0).
597 */
LL_SYSCFG_IsActiveFlag_EXTI6(void)598 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void)
599 {
600 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6)) ? 1UL : 0UL);
601 }
602
603 /**
604 * @brief Check if EXTI line 7 interrupt occurred or not.
605 * @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7
606 * @retval State of bit (1 or 0).
607 */
LL_SYSCFG_IsActiveFlag_EXTI7(void)608 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void)
609 {
610 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7)) ? 1UL : 0UL);
611 }
612
613 /**
614 * @brief Check if EXTI line 8 interrupt occurred or not.
615 * @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8
616 * @retval State of bit (1 or 0).
617 */
LL_SYSCFG_IsActiveFlag_EXTI8(void)618 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void)
619 {
620 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8)) ? 1UL : 0UL);
621 }
622
623 /**
624 * @brief Check if EXTI line 9 interrupt occurred or not.
625 * @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9
626 * @retval State of bit (1 or 0).
627 */
LL_SYSCFG_IsActiveFlag_EXTI9(void)628 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void)
629 {
630 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9)) ? 1UL : 0UL);
631 }
632
633 /**
634 * @brief Check if EXTI line 10 interrupt occurred or not.
635 * @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10
636 * @retval State of bit (1 or 0).
637 */
LL_SYSCFG_IsActiveFlag_EXTI10(void)638 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void)
639 {
640 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10)) ? 1UL : 0UL);
641 }
642
643 /**
644 * @brief Check if EXTI line 11 interrupt occurred or not.
645 * @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11
646 * @retval State of bit (1 or 0).
647 */
LL_SYSCFG_IsActiveFlag_EXTI11(void)648 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void)
649 {
650 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11)) ? 1UL : 0UL);
651 }
652
653 /**
654 * @brief Check if EXTI line 12 interrupt occurred or not.
655 * @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12
656 * @retval State of bit (1 or 0).
657 */
LL_SYSCFG_IsActiveFlag_EXTI12(void)658 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void)
659 {
660 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12)) ? 1UL : 0UL);
661 }
662
663 /**
664 * @brief Check if EXTI line 13 interrupt occurred or not.
665 * @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13
666 * @retval State of bit (1 or 0).
667 */
LL_SYSCFG_IsActiveFlag_EXTI13(void)668 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void)
669 {
670 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13)) ? 1UL : 0UL);
671 }
672
673 /**
674 * @brief Check if EXTI line 14 interrupt occurred or not.
675 * @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14
676 * @retval State of bit (1 or 0).
677 */
LL_SYSCFG_IsActiveFlag_EXTI14(void)678 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void)
679 {
680 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14)) ? 1UL : 0UL);
681 }
682
683 /**
684 * @brief Check if EXTI line 15 interrupt occurred or not.
685 * @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15
686 * @retval State of bit (1 or 0).
687 */
LL_SYSCFG_IsActiveFlag_EXTI15(void)688 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void)
689 {
690 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15)) ? 1UL : 0UL);
691 }
692
693 #if defined(SYSCFG_ITLINE8_SR_USBFS)
694 /**
695 * @brief Check if EXTI USB interrupt occurred or not.
696 * @rmtoll SYSCFG_ITLINE8 SR_USB LL_SYSCFG_IsActiveFlag_USB
697 * @retval State of bit (1 or 0).
698 */
LL_SYSCFG_IsActiveFlag_USB(void)699 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USB(void)
700 {
701 return ((READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_USBFS) == (SYSCFG_ITLINE8_SR_USBFS)) ? 1UL : 0UL);
702 }
703 #endif /* SYSCFG_ITLINE8_SR_USBFS */
704
705 /**
706 * @brief Check if DMA1 channel 1 interrupt occurred or not.
707 * @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1
708 * @retval State of bit (1 or 0).
709 */
LL_SYSCFG_IsActiveFlag_DMA1_CH1(void)710 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void)
711 {
712 return ((READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1)) ? 1UL : 0UL);
713 }
714
715 /**
716 * @brief Check if DMA1 channel 2 interrupt occurred or not.
717 * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2
718 * @retval State of bit (1 or 0).
719 */
LL_SYSCFG_IsActiveFlag_DMA1_CH2(void)720 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void)
721 {
722 return ((READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2)) ? 1UL : 0UL);
723 }
724
725 /**
726 * @brief Check if DMA1 channel 3 interrupt occurred or not.
727 * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3
728 * @retval State of bit (1 or 0).
729 */
LL_SYSCFG_IsActiveFlag_DMA1_CH3(void)730 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void)
731 {
732 return ((READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3)) ? 1UL : 0UL);
733 }
734
735 /**
736 * @brief Check if DMA1 channel 4 interrupt occurred or not.
737 * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4
738 * @retval State of bit (1 or 0).
739 */
LL_SYSCFG_IsActiveFlag_DMA1_CH4(void)740 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void)
741 {
742 return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4)) ? 1UL : 0UL);
743 }
744
745 /**
746 * @brief Check if DMA1 channel 5 interrupt occurred or not.
747 * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5
748 * @retval State of bit (1 or 0).
749 */
LL_SYSCFG_IsActiveFlag_DMA1_CH5(void)750 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void)
751 {
752 return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5)) ? 1UL : 0UL);
753 }
754
755 /**
756 * @brief Check if DMA1 channel 6 interrupt occurred or not.
757 * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6
758 * @retval State of bit (1 or 0).
759 */
LL_SYSCFG_IsActiveFlag_DMA1_CH6(void)760 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void)
761 {
762 return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6)) ? 1UL : 0UL);
763 }
764
765 /**
766 * @brief Check if DMA1 channel 7 interrupt occurred or not.
767 * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7
768 * @retval State of bit (1 or 0).
769 */
LL_SYSCFG_IsActiveFlag_DMA1_CH7(void)770 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void)
771 {
772 return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7)) ? 1UL : 0UL);
773 }
774
775 /**
776 * @brief Check if DMAMUX interrupt occurred or not.
777 * @rmtoll SYSCFG_ITLINE11 SR_DMAMUX1 LL_SYSCFG_IsActiveFlag_DMAMUX
778 * @retval State of bit (1 or 0).
779 */
LL_SYSCFG_IsActiveFlag_DMAMUX(void)780 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMAMUX(void)
781 {
782 return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMAMUX) == (SYSCFG_ITLINE11_SR_DMAMUX)) ? 1UL : 0UL);
783 }
784
785 #if defined(DMA2)
786 /**
787 * @brief Check if DMA2 channel 1 interrupt occurred or not.
788 * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH1 LL_SYSCFG_IsActiveFlag_DMA2_CH1
789 * @retval State of bit (1 or 0).
790 */
LL_SYSCFG_IsActiveFlag_DMA2_CH1(void)791 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void)
792 {
793 return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH1) == (SYSCFG_ITLINE11_SR_DMA2_CH1)) ? 1UL : 0UL);
794 }
795
796 /**
797 * @brief Check if DMA2 channel 2 interrupt occurred or not.
798 * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH2 LL_SYSCFG_IsActiveFlag_DMA2_CH2
799 * @retval State of bit (1 or 0).
800 */
LL_SYSCFG_IsActiveFlag_DMA2_CH2(void)801 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void)
802 {
803 return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH2) == (SYSCFG_ITLINE11_SR_DMA2_CH2)) ? 1UL : 0UL);
804 }
805
806 /**
807 * @brief Check if DMA2 channel 3 interrupt occurred or not.
808 * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3 LL_SYSCFG_IsActiveFlag_DMA2_CH3
809 * @retval State of bit (1 or 0).
810 */
LL_SYSCFG_IsActiveFlag_DMA2_CH3(void)811 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void)
812 {
813 return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2_CH3)) ? 1UL : 0UL);
814 }
815
816 /**
817 * @brief Check if DMA2 channel 4 interrupt occurred or not.
818 * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4 LL_SYSCFG_IsActiveFlag_DMA2_CH4
819 * @retval State of bit (1 or 0).
820 */
LL_SYSCFG_IsActiveFlag_DMA2_CH4(void)821 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void)
822 {
823 return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2_CH4)) ? 1UL : 0UL);
824 }
825
826 /**
827 * @brief Check if DMA2 channel 5 interrupt occurred or not.
828 * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5 LL_SYSCFG_IsActiveFlag_DMA2_CH5
829 * @retval State of bit (1 or 0).
830 */
LL_SYSCFG_IsActiveFlag_DMA2_CH5(void)831 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void)
832 {
833 return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2_CH5)) ? 1UL : 0UL);
834 }
835 #endif /* DMA2 */
836
837 /**
838 * @brief Check if ADC interrupt occurred or not.
839 * @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC
840 * @retval State of bit (1 or 0).
841 */
LL_SYSCFG_IsActiveFlag_ADC(void)842 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void)
843 {
844 return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC)) ? 1UL : 0UL);
845 }
846
847 /**
848 * @brief Check if Comparator 1 interrupt occurred or not (EXTI line 17).
849 * @rmtoll SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1
850 * @retval State of bit (1 or 0).
851 */
LL_SYSCFG_IsActiveFlag_COMP1(void)852 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void)
853 {
854 return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1)) ? 1UL : 0UL);
855 }
856
857 #if defined(SYSCFG_ITLINE12_SR_COMP2)
858 /**
859 * @brief Check if Comparator 2 interrupt occurred or not (EXTI line 18).
860 * @rmtoll SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2
861 * @retval State of bit (1 or 0).
862 */
LL_SYSCFG_IsActiveFlag_COMP2(void)863 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void)
864 {
865 return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2)) ? 1UL : 0UL);
866 }
867 #endif /* SYSCFG_ITLINE12_SR_COMP2 */
868
869 /**
870 * @brief Check if Timer 1 break interrupt occurred or not.
871 * @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK
872 * @retval State of bit (1 or 0).
873 */
LL_SYSCFG_IsActiveFlag_TIM1_BRK(void)874 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void)
875 {
876 return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK)) ? 1UL : 0UL);
877 }
878
879 /**
880 * @brief Check if Timer 1 update interrupt occurred or not.
881 * @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD
882 * @retval State of bit (1 or 0).
883 */
LL_SYSCFG_IsActiveFlag_TIM1_UPD(void)884 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void)
885 {
886 return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD)) ? 1UL : 0UL);
887 }
888
889 /**
890 * @brief Check if Timer 1 trigger interrupt occurred or not.
891 * @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG
892 * @retval State of bit (1 or 0).
893 */
LL_SYSCFG_IsActiveFlag_TIM1_TRG(void)894 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void)
895 {
896 return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG)) ? 1UL : 0UL);
897 }
898
899 /**
900 * @brief Check if Timer 1 commutation interrupt occurred or not.
901 * @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU
902 * @retval State of bit (1 or 0).
903 */
LL_SYSCFG_IsActiveFlag_TIM1_CCU(void)904 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void)
905 {
906 return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU)) ? 1UL : 0UL);
907 }
908
909 /**
910 * @brief Check if Timer 1 capture compare interrupt occurred or not.
911 * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC
912 * @retval State of bit (1 or 0).
913 */
LL_SYSCFG_IsActiveFlag_TIM1_CC1(void)914 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC1(void)
915 {
916 return ((READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC1) == (SYSCFG_ITLINE14_SR_TIM1_CC1)) ? 1UL : 0UL);
917 }
918
919 /**
920 * @brief Check if Timer 1 capture compare interrupt occurred or not.
921 * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC2 LL_SYSCFG_IsActiveFlag_TIM1_CC2
922 * @retval State of bit (1 or 0).
923 */
LL_SYSCFG_IsActiveFlag_TIM1_CC2(void)924 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC2(void)
925 {
926 return ((READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC2) == (SYSCFG_ITLINE14_SR_TIM1_CC2)) ? 1UL : 0UL);
927 }
928
929 /**
930 * @brief Check if Timer 1 capture compare interrupt occurred or not.
931 * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC3 LL_SYSCFG_IsActiveFlag_TIM1_CC3
932 * @retval State of bit (1 or 0).
933 */
LL_SYSCFG_IsActiveFlag_TIM1_CC3(void)934 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC3(void)
935 {
936 return ((READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC3) == (SYSCFG_ITLINE14_SR_TIM1_CC3)) ? 1UL : 0UL);
937 }
938
939 /**
940 * @brief Check if Timer 1 capture compare interrupt occurred or not.
941 * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC4 LL_SYSCFG_IsActiveFlag_TIM1_CC4
942 * @retval State of bit (1 or 0).
943 */
LL_SYSCFG_IsActiveFlag_TIM1_CC4(void)944 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC4(void)
945 {
946 return ((READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC4) == (SYSCFG_ITLINE14_SR_TIM1_CC4)) ? 1UL : 0UL);
947 }
948
949 /**
950 * @brief Check if Timer 2 interrupt occurred or not.
951 * @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2
952 * @retval State of bit (1 or 0).
953 */
LL_SYSCFG_IsActiveFlag_TIM2(void)954 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void)
955 {
956 return ((READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2) == (SYSCFG_ITLINE15_SR_TIM2)) ? 1UL : 0UL);
957 }
958
959 /**
960 * @brief Check if Timer 3 interrupt occurred or not.
961 * @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3
962 * @retval State of bit (1 or 0).
963 */
LL_SYSCFG_IsActiveFlag_TIM3(void)964 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void)
965 {
966 return ((READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3) == (SYSCFG_ITLINE16_SR_TIM3)) ? 1UL : 0UL);
967 }
968
969 /**
970 * @brief Check if DAC underrun interrupt occurred or not.
971 * @rmtoll SYSCFG_ITLINE17 SR_DAC LL_SYSCFG_IsActiveFlag_DAC
972 * @retval State of bit (1 or 0).
973 */
LL_SYSCFG_IsActiveFlag_DAC(void)974 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void)
975 {
976 return ((READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC)) ? 1UL : 0UL);
977 }
978
979 /**
980 * @brief Check if Timer 6 interrupt occurred or not.
981 * @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB LL_SYSCFG_IsActiveFlag_TIM6
982 * @retval State of bit (1 or 0).
983 */
LL_SYSCFG_IsActiveFlag_TIM6(void)984 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void)
985 {
986 return ((READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6) == (SYSCFG_ITLINE17_SR_TIM6)) ? 1UL : 0UL);
987 }
988
989 /**
990 * @brief Check if LPTIM1 interrupt occurred or not.
991 * @rmtoll SYSCFG_ITLINE17 SR_LPTIM1_GLB LL_SYSCFG_IsActiveFlag_LPTIM1
992 * @retval State of bit (1 or 0).
993 */
LL_SYSCFG_IsActiveFlag_LPTIM1(void)994 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPTIM1(void)
995 {
996 return ((READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_LPTIM1) == (SYSCFG_ITLINE17_SR_LPTIM1)) ? 1UL : 0UL);
997 }
998
999 /**
1000 * @brief Check if Timer 7 interrupt occurred or not.
1001 * @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB LL_SYSCFG_IsActiveFlag_TIM7
1002 * @retval State of bit (1 or 0).
1003 */
LL_SYSCFG_IsActiveFlag_TIM7(void)1004 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void)
1005 {
1006 return ((READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7) == (SYSCFG_ITLINE18_SR_TIM7)) ? 1UL : 0UL);
1007 }
1008
1009 /**
1010 * @brief Check if LPTIM2 interrupt occurred or not.
1011 * @rmtoll SYSCFG_ITLINE18 SR_LPTIM2_GLB LL_SYSCFG_IsActiveFlag_LPTIM2
1012 * @retval State of bit (1 or 0).
1013 */
LL_SYSCFG_IsActiveFlag_LPTIM2(void)1014 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPTIM2(void)
1015 {
1016 return ((READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_LPTIM2) == (SYSCFG_ITLINE18_SR_LPTIM2)) ? 1UL : 0UL);
1017 }
1018
1019 /**
1020 * @brief Check if Timer 15 interrupt occurred or not.
1021 * @rmtoll SYSCFG_ITLINE19 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15
1022 * @retval State of bit (1 or 0).
1023 */
LL_SYSCFG_IsActiveFlag_TIM15(void)1024 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void)
1025 {
1026 return ((READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM15) == (SYSCFG_ITLINE19_SR_TIM15)) ? 1UL : 0UL);
1027 }
1028
1029 #if defined(SYSCFG_ITLINE19_SR_LPTIM3)
1030 /**
1031 * @brief Check if LPTIM3 interrupt occurred or not.
1032 * @rmtoll SYSCFG_ITLINE19 SR_LPTIM3_GLB LL_SYSCFG_IsActiveFlag_LPTIM3
1033 * @retval State of bit (1 or 0).
1034 */
LL_SYSCFG_IsActiveFlag_LPTIM3(void)1035 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPTIM3(void)
1036 {
1037 return ((READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_LPTIM3) == (SYSCFG_ITLINE19_SR_LPTIM3)) ? 1UL : 0UL);
1038 }
1039 #endif /* SYSCFG_ITLINE19_SR_LPTIM3_GLB */
1040
1041 /**
1042 * @brief Check if Timer 16 interrupt occurred or not.
1043 * @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM16
1044 * @retval State of bit (1 or 0).
1045 */
LL_SYSCFG_IsActiveFlag_TIM16(void)1046 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void)
1047 {
1048 return ((READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM16) == (SYSCFG_ITLINE20_SR_TIM16)) ? 1UL : 0UL);
1049 }
1050
1051 /**
1052 * @brief Check if TSC interrupt occurred or not.
1053 * @rmtoll SYSCFG_ITLINE21 SR_TSC_MCE LL_SYSCFG_IsActiveFlag_TSC_MCE
1054 * @retval State of bit (1 or 0).
1055 */
LL_SYSCFG_IsActiveFlag_TSC_MCE(void)1056 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_MCE(void)
1057 {
1058 return ((READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TSC_MCE) == (SYSCFG_ITLINE21_SR_TSC_MCE)) ? 1UL : 0UL);
1059 }
1060
1061 /**
1062 * @brief Check if TSC interrupt occurred or not.
1063 * @rmtoll SYSCFG_ITLINE21 SR_TSC_EOA LL_SYSCFG_IsActiveFlag_TSC_EOA
1064 * @retval State of bit (1 or 0).
1065 */
LL_SYSCFG_IsActiveFlag_TSC_EOA(void)1066 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_EOA(void)
1067 {
1068 return ((READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TSC_EOA) == (SYSCFG_ITLINE21_SR_TSC_EOA)) ? 1UL : 0UL);
1069 }
1070
1071 #if defined(SYSCFG_ITLINE22_SR_LCD)
1072 /**
1073 * @brief Check if TSC interrupt occurred or not.
1074 * @rmtoll SYSCFG_ITLINE22 SR_LCD LL_SYSCFG_IsActiveFlag_LCD
1075 * @retval State of bit (1 or 0).
1076 */
LL_SYSCFG_IsActiveFlag_LCD(void)1077 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LCD(void)
1078 {
1079 return ((READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_LCD) == (SYSCFG_ITLINE22_SR_LCD)) ? 1UL : 0UL);
1080 }
1081 #endif /* SYSCFG_ITLINE21_SR_LCD */
1082
1083 /**
1084 * @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 33.
1085 * @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1
1086 * @retval State of bit (1 or 0).
1087 */
LL_SYSCFG_IsActiveFlag_I2C1(void)1088 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void)
1089 {
1090 return ((READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1) == (SYSCFG_ITLINE23_SR_I2C1)) ? 1UL : 0UL);
1091 }
1092
1093 /**
1094 * @brief Check if I2C2 interrupt occurred or not.
1095 * @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2
1096 * @retval State of bit (1 or 0).
1097 */
LL_SYSCFG_IsActiveFlag_I2C2(void)1098 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void)
1099 {
1100 return ((READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2) == (SYSCFG_ITLINE24_SR_I2C2)) ? 1UL : 0UL);
1101 }
1102
1103 /**
1104 * @brief Check if I2C3 interrupt occurred or not.
1105 * @rmtoll SYSCFG_ITLINE24 SR_I2C3_GLB LL_SYSCFG_IsActiveFlag_I2C3
1106 * @retval State of bit (1 or 0).
1107 */
LL_SYSCFG_IsActiveFlag_I2C3(void)1108 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C3(void)
1109 {
1110 return ((READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C3) == (SYSCFG_ITLINE24_SR_I2C3)) ? 1UL : 0UL);
1111 }
1112
1113 /**
1114 * @brief Check if I2C4 interrupt occurred or not.
1115 * @rmtoll SYSCFG_ITLINE24 SR_I2C4_GLB LL_SYSCFG_IsActiveFlag_I2C4
1116 * @retval State of bit (1 or 0).
1117 */
LL_SYSCFG_IsActiveFlag_I2C4(void)1118 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C4(void)
1119 {
1120 return ((READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C4) == (SYSCFG_ITLINE24_SR_I2C4)) ? 1UL : 0UL);
1121 }
1122
1123 /**
1124 * @brief Check if SPI1 interrupt occurred or not.
1125 * @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1
1126 * @retval State of bit (1 or 0).
1127 */
LL_SYSCFG_IsActiveFlag_SPI1(void)1128 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void)
1129 {
1130 return ((READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1)) ? 1UL : 0UL);
1131 }
1132
1133 /**
1134 * @brief Check if SPI2 interrupt occurred or not.
1135 * @rmtoll SYSCFG_ITLINE26 SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2
1136 * @retval State of bit (1 or 0).
1137 */
LL_SYSCFG_IsActiveFlag_SPI2(void)1138 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void)
1139 {
1140 return ((READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2)) ? 1UL : 0UL);
1141 }
1142
1143 #if defined(SPI3)
1144 /**
1145 * @brief Check if SPI2 interrupt occurred or not.
1146 * @rmtoll SYSCFG_ITLINE26 SR_SPI3 LL_SYSCFG_IsActiveFlag_SPI3
1147 * @retval State of bit (1 or 0).
1148 */
LL_SYSCFG_IsActiveFlag_SPI3(void)1149 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI3(void)
1150 {
1151 return ((READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI3) == (SYSCFG_ITLINE26_SR_SPI3)) ? 1UL : 0UL);
1152 }
1153 #endif /* SPI3 */
1154
1155 /**
1156 * @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25.
1157 * @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1
1158 * @retval State of bit (1 or 0).
1159 */
LL_SYSCFG_IsActiveFlag_USART1(void)1160 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void)
1161 {
1162 return ((READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1) == (SYSCFG_ITLINE27_SR_USART1)) ? 1UL : 0UL);
1163 }
1164
1165 /**
1166 * @brief Check if USART2 interrupt occurred or not, combined with EXTI line 35.
1167 * @rmtoll SYSCFG_ITLINE28 SR_USART2 LL_SYSCFG_IsActiveFlag_USART2
1168 * @retval State of bit (1 or 0).
1169 */
LL_SYSCFG_IsActiveFlag_USART2(void)1170 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void)
1171 {
1172 return ((READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2) == (SYSCFG_ITLINE28_SR_USART2)) ? 1UL : 0UL);
1173 }
1174
1175 /**
1176 * @brief Check if LPUART2 interrupt occurred or not, combined with EXTI line 31.
1177 * @rmtoll SYSCFG_ITLINE28 SR_LPUART2 LL_SYSCFG_IsActiveFlag_LPUART2
1178 * @retval State of bit (1 or 0).
1179 */
LL_SYSCFG_IsActiveFlag_LPUART2(void)1180 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPUART2(void)
1181 {
1182 return ((READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_LPUART2) == (SYSCFG_ITLINE28_SR_LPUART2)) ? 1UL : 0UL);
1183 }
1184
1185 /**
1186 * @brief Check if USART3 interrupt occurred or not, combined with EXTI line 29.
1187 * @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3
1188 * @retval State of bit (1 or 0).
1189 */
LL_SYSCFG_IsActiveFlag_USART3(void)1190 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void)
1191 {
1192 return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3) == (SYSCFG_ITLINE29_SR_USART3)) ? 1UL : 0UL);
1193 }
1194
1195 /**
1196 * @brief Check if LPUART1 interrupt occurred or not, combined with EXTI line 30.
1197 * @rmtoll SYSCFG_ITLINE29 SR_LPUART1_GLB LL_SYSCFG_IsActiveFlag_LPUART1
1198 * @retval State of bit (1 or 0).
1199 */
LL_SYSCFG_IsActiveFlag_LPUART1(void)1200 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPUART1(void)
1201 {
1202 return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_LPUART1) == (SYSCFG_ITLINE29_SR_LPUART1)) ? 1UL : 0UL);
1203 }
1204
1205 /**
1206 * @brief Check if USART4 interrupt occurred or not.
1207 * @rmtoll SYSCFG_ITLINE29 SR_USART4 LL_SYSCFG_IsActiveFlag_USART4
1208 * @retval State of bit (1 or 0).
1209 */
LL_SYSCFG_IsActiveFlag_USART4(void)1210 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void)
1211 {
1212 return ((READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_USART4) == (SYSCFG_ITLINE30_SR_USART4)) ? 1UL : 0UL);
1213 }
1214
1215 #if defined(SYSCFG_ITLINE30_SR_LPUART3)
1216 /**
1217 * @brief Check if LPUART1 interrupt occurred or not, combined with EXTI line 32.
1218 * @rmtoll SYSCFG_ITLINE30 SR_LPUART3_GLB LL_SYSCFG_IsActiveFlag_LPUART3
1219 * @retval State of bit (1 or 0).
1220 */
LL_SYSCFG_IsActiveFlag_LPUART3(void)1221 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPUART3(void)
1222 {
1223 return ((READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_LPUART3) == (SYSCFG_ITLINE30_SR_LPUART3)) ? 1UL : 0UL);
1224 }
1225 #endif /* SYSCFG_ITLINE30_SR_LPUART3 */
1226
1227 #if defined(AES)
1228 /**
1229 * @brief Check if AES interrupt occurred or not
1230 * @rmtoll SYSCFG_ITLINE31 SR_AES LL_SYSCFG_IsActiveFlag_AES
1231 * @retval State of bit (1 or 0).
1232 */
LL_SYSCFG_IsActiveFlag_AES(void)1233 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_AES(void)
1234 {
1235 return ((READ_BIT(SYSCFG->IT_LINE_SR[31], SYSCFG_ITLINE31_SR_AES) == (SYSCFG_ITLINE31_SR_AES)) ? 1UL : 0UL);
1236 }
1237 #endif /* AES */
1238
1239 /**
1240 * @brief Check if RNG interrupt occurred or not, combined with EXTI line 31.
1241 * @rmtoll SYSCFG_ITLINE31 SR_RNG LL_SYSCFG_IsActiveFlag_RNG
1242 * @retval State of bit (1 or 0).
1243 */
LL_SYSCFG_IsActiveFlag_RNG(void)1244 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RNG(void)
1245 {
1246 return ((READ_BIT(SYSCFG->IT_LINE_SR[31], SYSCFG_ITLINE31_SR_RNG) == (SYSCFG_ITLINE31_SR_RNG)) ? 1UL : 0UL);
1247 }
1248
1249 /**
1250 * @brief Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
1251 * automatically cleared at the end of the SRAM2 erase operation.)
1252 * @note This bit is write-protected: setting this bit is possible only after the
1253 * correct key sequence is written in the SYSCFG_SKR register as described in
1254 * the Reference Manual.
1255 * @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase
1256 * @retval None
1257 */
LL_SYSCFG_EnableSRAM2Erase(void)1258 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
1259 {
1260 /* Starts a hardware SRAM2 erase operation*/
1261 SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
1262 }
1263
1264 /**
1265 * @brief Check if SRAM2 erase operation is on going
1266 * @rmtoll SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing
1267 * @retval State of bit (1 or 0).
1268 */
LL_SYSCFG_IsSRAM2EraseOngoing(void)1269 __STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
1270 {
1271 return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY)) ? 1UL : 0UL) ;
1272 }
1273
1274 /**
1275 * @brief Set connections to TIM1/15/16 Break inputs
1276 * @rmtoll SYSCFG_CFGR2 CCL LL_SYSCFG_SetTIMBreakInputs\n
1277 * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
1278 * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
1279 * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
1280 * SYSCFG_CFGR2 BKPL LL_SYSCFG_SetTIMBreakInputs
1281 * @param Break This parameter can be a combination of the following values:
1282 * @arg @ref LL_SYSCFG_TIMBREAK_CCL
1283 * @arg @ref LL_SYSCFG_TIMBREAK_SPL
1284 * @arg @ref LL_SYSCFG_TIMBREAK_PVDL
1285 * @arg @ref LL_SYSCFG_TIMBREAK_ECCL
1286 * @arg @ref LL_SYSCFG_TIMBREAK_BKPL
1287 *
1288 * @retval None
1289 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)1290 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
1291 {
1292 MODIFY_REG(SYSCFG->CFGR2,
1293 SYSCFG_CFGR2_CCL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL | SYSCFG_CFGR2_BKPL, Break);
1294 }
1295
1296 /**
1297 * @brief Set connections to TIM1/15/16 Break inputs
1298 * @rmtoll SYSCFG_CFGR2 CCL LL_SYSCFG_GetTIMBreakInputs\n
1299 * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
1300 * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
1301 * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
1302 * SYSCFG_CFGR2 BKPL LL_SYSCFG_GetTIMBreakInputs
1303 *
1304 * @retval None
1305 */
LL_SYSCFG_GetTIMBreakInputs(void)1306 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
1307 {
1308 return (uint32_t)(READ_BIT(SYSCFG->CFGR2,
1309 SYSCFG_CFGR2_CCL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL | \
1310 SYSCFG_CFGR2_BKPL));
1311 }
1312
1313 /**
1314 * @brief Check if SRAM2 parity error detected
1315 * @rmtoll SYSCFG_CFGR2 BKPF LL_SYSCFG_IsActiveFlag_BKP
1316 * @retval State of bit (1 or 0).
1317 */
LL_SYSCFG_IsActiveFlag_BKP(void)1318 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_BKP(void)
1319 {
1320 return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_BKPF) == (SYSCFG_CFGR2_BKPF)) ? 1UL : 0UL);
1321 }
1322
1323 /**
1324 * @brief Clear SRAM2 parity error flag
1325 * @rmtoll SYSCFG_CFGR2 BKPF LL_SYSCFG_ClearFlag_BKP
1326 * @retval None
1327 */
LL_SYSCFG_ClearFlag_BKP(void)1328 __STATIC_INLINE void LL_SYSCFG_ClearFlag_BKP(void)
1329 {
1330 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_BKPF);
1331 }
1332
1333 /**
1334 * @brief Check if SRAM1 parity error detected
1335 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
1336 * @retval State of bit (1 or 0).
1337 */
LL_SYSCFG_IsActiveFlag_SP(void)1338 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
1339 {
1340 return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)) ? 1UL : 0UL);
1341 }
1342
1343 /**
1344 * @brief Clear SRAM1 parity error flag
1345 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
1346 * @retval None
1347 */
LL_SYSCFG_ClearFlag_SP(void)1348 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
1349 {
1350 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
1351 }
1352
1353 /**
1354 * @brief SRAM2 page write protection lock prior to erase
1355 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP
1356 * @retval None
1357 */
LL_SYSCFG_LockSRAM2WRP(void)1358 __STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
1359 {
1360 /* Writing a wrong key reactivates the write protection */
1361 WRITE_REG(SYSCFG->SKR, 0x00);
1362 }
1363
1364 /**
1365 * @brief Enable connection of PB4 to COMP2
1366 * @rmtoll SYSCFG_TSCCR G2_IO1 LL_SYSCFG_EnableTSCCmpMod_G2IO1
1367 * @retval None
1368 */
LL_SYSCFG_EnableTSCCmpMod_G2IO1(void)1369 __STATIC_INLINE void LL_SYSCFG_EnableTSCCmpMod_G2IO1(void)
1370 {
1371 SET_BIT(SYSCFG->TSCCR, SYSCFG_TSCCR_G2IO1);
1372 }
1373
1374 /**
1375 * @brief Disable connection of PB4 to COMP2
1376 * @rmtoll SYSCFG_TSCCR G2_IO1 LL_SYSCFG_DisableTSCCmpMod_G2IO1
1377 * @retval None
1378 */
LL_SYSCFG_DisableTSCCmpMod_G2IO1(void)1379 __STATIC_INLINE void LL_SYSCFG_DisableTSCCmpMod_G2IO1(void)
1380 {
1381 CLEAR_BIT(SYSCFG->TSCCR, SYSCFG_TSCCR_G2IO1);
1382 }
1383
1384 /**
1385 * @brief Enable connection of PB6 to COMP2
1386 * @rmtoll SYSCFG_TSCCR G2_IO3 LL_SYSCFG_EnableTSCCmpMod_G2IO3
1387 * @retval None
1388 */
LL_SYSCFG_EnableTSCCmpMod_G2IO3(void)1389 __STATIC_INLINE void LL_SYSCFG_EnableTSCCmpMod_G2IO3(void)
1390 {
1391 SET_BIT(SYSCFG->TSCCR, SYSCFG_TSCCR_G2IO3);
1392 }
1393
1394 /**
1395 * @brief Disable connection of PB6 to COMP2
1396 * @rmtoll SYSCFG_TSCCR G2_IO3 LL_SYSCFG_DisableTSCCmpMod_G2IO3
1397 * @retval None
1398 */
LL_SYSCFG_DisableTSCCmpMod_G2IO3(void)1399 __STATIC_INLINE void LL_SYSCFG_DisableTSCCmpMod_G2IO3(void)
1400 {
1401 CLEAR_BIT(SYSCFG->TSCCR, SYSCFG_TSCCR_G2IO3);
1402 }
1403
1404 /**
1405 * @brief Enable connection of PC6 to COMP1
1406 * @rmtoll SYSCFG_TSCCR G4_IO1 LL_SYSCFG_EnableTSCCmpMod_G4IO1
1407 * @retval None
1408 */
LL_SYSCFG_EnableTSCCmpMod_G4IO1(void)1409 __STATIC_INLINE void LL_SYSCFG_EnableTSCCmpMod_G4IO1(void)
1410 {
1411 SET_BIT(SYSCFG->TSCCR, SYSCFG_TSCCR_G4IO1);
1412 }
1413
1414 /**
1415 * @brief Disable connection of PC6 to COMP1
1416 * @rmtoll SYSCFG_TSCCR G4_IO1 LL_SYSCFG_DisableTSCCmpMod_G4IO1
1417 * @retval None
1418 */
LL_SYSCFG_DisableTSCCmpMod_G4IO1(void)1419 __STATIC_INLINE void LL_SYSCFG_DisableTSCCmpMod_G4IO1(void)
1420 {
1421 CLEAR_BIT(SYSCFG->TSCCR, SYSCFG_TSCCR_G4IO1);
1422 }
1423
1424 /**
1425 * @brief Enable connection of PD10 to COMP2
1426 * @rmtoll SYSCFG_TSCCR G6_IO1 LL_SYSCFG_EnableTSCCmpMod_G6IO1
1427 * @retval None
1428 */
LL_SYSCFG_EnableTSCCmpMod_G6IO1(void)1429 __STATIC_INLINE void LL_SYSCFG_EnableTSCCmpMod_G6IO1(void)
1430 {
1431 SET_BIT(SYSCFG->TSCCR, SYSCFG_TSCCR_G6IO1);
1432 }
1433
1434 /**
1435 * @brief Disable connection of PD10 to COMP2
1436 * @rmtoll SYSCFG_TSCCR G6_IO1 LL_SYSCFG_DisableTSCCmpMod_G6IO1
1437 * @retval None
1438 */
LL_SYSCFG_DisableTSCCmpMod_G6IO1(void)1439 __STATIC_INLINE void LL_SYSCFG_DisableTSCCmpMod_G6IO1(void)
1440 {
1441 CLEAR_BIT(SYSCFG->TSCCR, SYSCFG_TSCCR_G6IO1);
1442 }
1443
1444 /**
1445 * @brief Enable connection of PA9 to COMP1
1446 * @rmtoll SYSCFG_TSCCR G7_IO2 LL_SYSCFG_EnableTSCCmpMod_G7IO2
1447 * @retval None
1448 */
LL_SYSCFG_EnableTSCCmpMod_G7IO2(void)1449 __STATIC_INLINE void LL_SYSCFG_EnableTSCCmpMod_G7IO2(void)
1450 {
1451 SET_BIT(SYSCFG->TSCCR, SYSCFG_TSCCR_G7IO2);
1452 }
1453
1454 /**
1455 * @brief Disable connection of PA9 to COMP1
1456 * @rmtoll SYSCFG_TSCCR G7_IO2 LL_SYSCFG_DisableTSCCmpMod_G7IO2
1457 * @retval None
1458 */
LL_SYSCFG_DisableTSCCmpMod_G7IO2(void)1459 __STATIC_INLINE void LL_SYSCFG_DisableTSCCmpMod_G7IO2(void)
1460 {
1461 CLEAR_BIT(SYSCFG->TSCCR, SYSCFG_TSCCR_G7IO2);
1462 }
1463
1464 /**
1465 * @brief I/O control in comparator mode
1466 * @rmtoll SYSCFG_TSCCR TSC_IOCTRL LL_SYSCFG_SetTSCIOControl
1467 * @arg TSCIOControl This parameter can be a combination of the following values:
1468 * @arg @ref LL_SYSCFG_TSCIOCONTROL_REG
1469 * @arg @ref LL_SYSCFG_TSCIOCONTROL_ANALOG
1470 * @retval None
1471 */
LL_SYSCFG_SetTSCIOControl(uint32_t TSCIOControl)1472 __STATIC_INLINE void LL_SYSCFG_SetTSCIOControl(uint32_t TSCIOControl)
1473 {
1474 SET_BIT(SYSCFG->TSCCR, TSCIOControl);
1475 }
1476
1477 /**
1478 * @brief I/O control in comparator mode
1479 * @rmtoll SYSCFG_TSCCR TSC_IOCTRL LL_SYSCFG_GetTSCIOControl
1480 * @retval Returned value can be one of the following values:
1481 * @arg @ref LL_SYSCFG_TSCIOCONTROL_REG
1482 * @arg @ref LL_SYSCFG_TSCIOCONTROL_ANALOG
1483 */
LL_SYSCFG_GetTSCIOControl(void)1484 __STATIC_INLINE uint32_t LL_SYSCFG_GetTSCIOControl(void)
1485 {
1486 return (READ_BIT(SYSCFG->TSCCR, SYSCFG_TSCCR_TSCIOCTRL));
1487 }
1488
1489 /**
1490 * @brief SRAM2 page write protection unlock prior to erase
1491 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP
1492 * @retval None
1493 */
LL_SYSCFG_UnlockSRAM2WRP(void)1494 __STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
1495 {
1496 /* unlock the write protection of the SRAM2ER bit */
1497 WRITE_REG(SYSCFG->SKR, 0xCA);
1498 WRITE_REG(SYSCFG->SKR, 0x53);
1499 }
1500
1501 /**
1502 * @}
1503 */
1504
1505 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1506 * @{
1507 */
1508
1509 /**
1510 * @brief Return the device identifier
1511 * @note For STM32U083xx devices, the device ID is 0x460
1512 * @rmtoll DBG_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1513 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
1514 */
LL_DBGMCU_GetDeviceID(void)1515 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1516 {
1517 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1518 }
1519
1520 /**
1521 * @brief Return the device revision identifier
1522 * @note This field indicates the revision of the device.
1523 * @rmtoll DBG_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1524 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1525 */
LL_DBGMCU_GetRevisionID(void)1526 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1527 {
1528 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1529 }
1530
1531 /**
1532 * @brief Enable the Debug Module during STOP mode
1533 * @rmtoll DBG_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1534 * @retval None
1535 */
LL_DBGMCU_EnableDBGStopMode(void)1536 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1537 {
1538 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1539 }
1540
1541 /**
1542 * @brief Disable the Debug Module during STOP mode
1543 * @rmtoll DBG_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1544 * @retval None
1545 */
LL_DBGMCU_DisableDBGStopMode(void)1546 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1547 {
1548 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1549 }
1550
1551 /**
1552 * @brief Enable the Debug Module during STANDBY mode
1553 * @rmtoll DBG_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1554 * @retval None
1555 */
LL_DBGMCU_EnableDBGStandbyMode(void)1556 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1557 {
1558 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1559 }
1560
1561 /**
1562 * @brief Disable the Debug Module during STANDBY mode
1563 * @rmtoll DBG_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1564 * @retval None
1565 */
LL_DBGMCU_DisableDBGStandbyMode(void)1566 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1567 {
1568 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1569 }
1570
1571 /**
1572 * @brief Freeze APB1 peripherals (group1 peripherals)
1573 * @rmtoll DBG_APBFZ1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1574 * DBG_APBFZ1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1575 * DBG_APBFZ1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1576 * DBG_APBFZ1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1577 * DBG_APBFZ1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1578 * DBG_APBFZ1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1579 * DBG_APBFZ1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1580 * DBG_APBFZ1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1581 * DBG_APBFZ1 DBG_I2C3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1582 * DBG_APBFZ1 DBG_I2C1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1583 * DBG_APBFZ1 DBG_LPTIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1584 * DBG_APBFZ1 DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1585 * @param Periphs This parameter can be a combination of the following values:
1586 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1587 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1588 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1589 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1590 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1591 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1592 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1593 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1594 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1595 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1596 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM2_STOP
1597 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1598 *
1599 * @retval None
1600 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1601 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1602 {
1603 SET_BIT(DBGMCU->APBFZ1, Periphs);
1604 }
1605
1606 /**
1607 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1608 @rmtoll DBG_APBFZ1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1609 * DBG_APBFZ1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1610 * DBG_APBFZ1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1611 * DBG_APBFZ1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1612 * DBG_APBFZ1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1613 * DBG_APBFZ1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1614 * DBG_APBFZ1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1615 * DBG_APBFZ1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1616 * DBG_APBFZ1 DBG_I2C3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1617 * DBG_APBFZ1 DBG_I2C1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1618 * DBG_APBFZ1 DBG_LPTIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1619 * DBG_APBFZ1 DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1620 * @param Periphs This parameter can be a combination of the following values:
1621 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1622 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1623 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1624 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1625 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1626 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1627 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1628 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1629 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1630 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1631 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM2_STOP
1632 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1633 *
1634 * @retval None
1635 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1636 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1637 {
1638 CLEAR_BIT(DBGMCU->APBFZ1, Periphs);
1639 }
1640
1641 /**
1642 * @brief Freeze APB2 peripherals
1643 * @rmtoll DBG_APBFZ2 DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
1644 * DBG_APBFZ2 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
1645 * DBG_APBFZ2 DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
1646 * DBG_APBFZ2 DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
1647 * DBG_APBFZ2 DBG_LPTIM3_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
1648 * @param Periphs This parameter can be a combination of the following values:
1649 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP
1650 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM14_STOP
1651 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP
1652 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP
1653 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM3_STOP
1654 *
1655 * @retval None
1656 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1657 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1658 {
1659 SET_BIT(DBGMCU->APBFZ2, Periphs);
1660 }
1661
1662 /**
1663 * @brief Unfreeze APB2 peripherals
1664 * @rmtoll DBG_APBFZ2 DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
1665 * DBG_APBFZ2 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
1666 * DBG_APBFZ2 DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
1667 * DBG_APBFZ2 DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
1668 * DBG_APBFZ2 DBG_LPTIM3_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
1669 * @param Periphs This parameter can be a combination of the following values:
1670 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP
1671 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM14_STOP
1672 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP
1673 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP
1674 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM3_STOP
1675 *
1676 * @retval None
1677 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1678 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1679 {
1680 CLEAR_BIT(DBGMCU->APBFZ2, Periphs);
1681 }
1682 /**
1683 * @}
1684 */
1685
1686 #if defined(VREFBUF)
1687 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
1688 * @{
1689 */
1690
1691 /**
1692 * @brief Enable Internal voltage reference
1693 * @rmtoll VREFBUF_CSR VREFBUF_CSR_ENVR LL_VREFBUF_Enable
1694 * @retval None
1695 */
LL_VREFBUF_Enable(void)1696 __STATIC_INLINE void LL_VREFBUF_Enable(void)
1697 {
1698 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1699 }
1700
1701 /**
1702 * @brief Disable Internal voltage reference
1703 * @rmtoll VREFBUF_CSR VREFBUF_CSR_ENVR LL_VREFBUF_Disable
1704 * @retval None
1705 */
LL_VREFBUF_Disable(void)1706 __STATIC_INLINE void LL_VREFBUF_Disable(void)
1707 {
1708 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1709 }
1710
1711 /**
1712 * @brief Enable high impedance (VREF+pin is high impedance)
1713 * @rmtoll VREFBUF_CSR VREFBUF_CSR_HIZ LL_VREFBUF_EnableHIZ
1714 * @retval None
1715 */
LL_VREFBUF_EnableHIZ(void)1716 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
1717 {
1718 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1719 }
1720
1721 /**
1722 * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
1723 * @rmtoll VREFBUF_CSR VREFBUF_CSR_HIZ LL_VREFBUF_DisableHIZ
1724 * @retval None
1725 */
LL_VREFBUF_DisableHIZ(void)1726 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
1727 {
1728 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1729 }
1730
1731 /**
1732 * @brief Set the Voltage reference scale
1733 * @rmtoll VREFBUF_CSR VREFBUF_CSR_VRS LL_VREFBUF_SetVoltageScaling
1734 * @param Scale This parameter can be one of the following values:
1735 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1736 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1737 * @retval None
1738 */
LL_VREFBUF_SetVoltageScaling(uint32_t Scale)1739 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
1740 {
1741 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
1742 }
1743
1744 /**
1745 * @brief Get the Voltage reference scale
1746 * @rmtoll VREFBUF_CSR VREFBUF_CSR_VRS LL_VREFBUF_GetVoltageScaling
1747 * @retval Returned value can be one of the following values:
1748 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1749 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1750 */
LL_VREFBUF_GetVoltageScaling(void)1751 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
1752 {
1753 return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
1754 }
1755
1756 /**
1757 * @brief Check if Voltage reference buffer is ready
1758 * @rmtoll VREFBUF_CSR VREFBUF_CSR_VRS LL_VREFBUF_IsVREFReady
1759 * @retval State of bit (1 or 0).
1760 */
LL_VREFBUF_IsVREFReady(void)1761 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
1762 {
1763 return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)) ? 1UL : 0UL);
1764 }
1765
1766 /**
1767 * @brief Get the trimming code for VREFBUF calibration
1768 * @rmtoll VREFBUF_CCR VREFBUF_CCR_TRIM LL_VREFBUF_GetTrimming
1769 * @retval Between 0 and 0x3F
1770 */
LL_VREFBUF_GetTrimming(void)1771 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
1772 {
1773 return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
1774 }
1775
1776 /**
1777 * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
1778 * @rmtoll VREFBUF_CCR VREFBUF_CCR_TRIM LL_VREFBUF_SetTrimming
1779 * @param Value Between 0 and 0x3F
1780 * @retval None
1781 */
LL_VREFBUF_SetTrimming(uint32_t Value)1782 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
1783 {
1784 WRITE_REG(VREFBUF->CCR, Value);
1785 }
1786
1787 /**
1788 * @}
1789 */
1790 #endif /* VREFBUF */
1791
1792 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1793 * @{
1794 */
1795
1796 /**
1797 * @brief Set FLASH Latency
1798 * @rmtoll FLASH_ACR FLASH_ACR_LATENCY LL_FLASH_SetLatency
1799 * @param Latency This parameter can be one of the following values:
1800 * @arg @ref LL_FLASH_LATENCY_0
1801 * @arg @ref LL_FLASH_LATENCY_1
1802 * @arg @ref LL_FLASH_LATENCY_2
1803 * @retval None
1804 */
LL_FLASH_SetLatency(uint32_t Latency)1805 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1806 {
1807 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1808 }
1809
1810 /**
1811 * @brief Get FLASH Latency
1812 * @rmtoll FLASH_ACR FLASH_ACR_LATENCY LL_FLASH_GetLatency
1813 * @retval Returned value can be one of the following values:
1814 * @arg @ref LL_FLASH_LATENCY_0
1815 * @arg @ref LL_FLASH_LATENCY_1
1816 * @arg @ref LL_FLASH_LATENCY_2
1817 */
LL_FLASH_GetLatency(void)1818 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1819 {
1820 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1821 }
1822
1823 /**
1824 * @brief Unlock the Flash
1825 * @rmtoll FLASH_KEYR FLASH_KEYR_KEY LL_FLASH_Unlock
1826 * @retval None
1827 */
LL_FLASH_Unlock(void)1828 __STATIC_INLINE void LL_FLASH_Unlock(void)
1829 {
1830 /* Following values must be written consecutively to unlock the FLASH control register */
1831 FLASH->KEYR = FLASH_KEY1;
1832 FLASH->KEYR = FLASH_KEY2;
1833 }
1834
1835 /**
1836 * @brief Enable Prefetch
1837 * @rmtoll FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_EnablePrefetch
1838 * @retval None
1839 */
LL_FLASH_EnablePrefetch(void)1840 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1841 {
1842 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1843 }
1844
1845 /**
1846 * @brief Disable Prefetch
1847 * @rmtoll FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_DisablePrefetch
1848 * @retval None
1849 */
LL_FLASH_DisablePrefetch(void)1850 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1851 {
1852 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1853 }
1854
1855 /**
1856 * @brief Check if Prefetch buffer is enabled
1857 * @rmtoll FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_IsPrefetchEnabled
1858 * @retval State of bit (1 or 0).
1859 */
LL_FLASH_IsPrefetchEnabled(void)1860 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1861 {
1862 return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL);
1863 }
1864
1865 /**
1866 * @brief Enable Instruction cache
1867 * @rmtoll FLASH_ACR FLASH_ACR_ICEN LL_FLASH_EnableInstCache
1868 * @retval None
1869 */
LL_FLASH_EnableInstCache(void)1870 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
1871 {
1872 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1873 }
1874
1875 /**
1876 * @brief Disable Instruction cache
1877 * @rmtoll FLASH_ACR FLASH_ACR_ICEN LL_FLASH_DisableInstCache
1878 * @retval None
1879 */
LL_FLASH_DisableInstCache(void)1880 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
1881 {
1882 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1883 }
1884
1885 /**
1886 * @brief Enable Instruction cache reset
1887 * @note bit can be written only when the instruction cache is disabled
1888 * @rmtoll FLASH_ACR FLASH_ACR_ICRST LL_FLASH_EnableInstCacheReset
1889 * @retval None
1890 */
LL_FLASH_EnableInstCacheReset(void)1891 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
1892 {
1893 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1894 }
1895
1896 /**
1897 * @brief Disable Instruction cache reset
1898 * @rmtoll FLASH_ACR FLASH_ACR_ICRST LL_FLASH_DisableInstCacheReset
1899 * @retval None
1900 */
LL_FLASH_DisableInstCacheReset(void)1901 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
1902 {
1903 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1904 }
1905
1906 /** Set EMPTY flag information as Flash User area empty
1907 * @brief
1908 * @rmtoll FLASH_ACR FLASH_ACR_EMPTY LL_FLASH_SetEmptyFlag
1909 * @retval None
1910 */
LL_FLASH_SetEmptyFlag(void)1911 __STATIC_INLINE void LL_FLASH_SetEmptyFlag(void)
1912 {
1913 SET_BIT(FLASH->ACR, FLASH_ACR_EMPTY);
1914 }
1915
1916 /** Clear EMPTY flag information as Flash User area programmed
1917 * @brief
1918 * @rmtoll FLASH_ACR FLASH_ACR_EMPTY LL_FLASH_ClearEmptyFlag
1919 * @retval None
1920 */
LL_FLASH_ClearEmptyFlag(void)1921 __STATIC_INLINE void LL_FLASH_ClearEmptyFlag(void)
1922 {
1923 CLEAR_BIT(FLASH->ACR, FLASH_ACR_EMPTY);
1924 }
1925
1926 /**
1927 * @brief Check if the EMPTY flag is set or reset
1928 * @rmtoll FLASH_ACR EMPTY LL_FLASH_IsEmptyFlag
1929 * @retval State of bit (1 or 0).
1930 */
LL_FLASH_IsEmptyFlag(void)1931 __STATIC_INLINE uint32_t LL_FLASH_IsEmptyFlag(void)
1932 {
1933 return ((READ_BIT(FLASH->ACR, FLASH_ACR_EMPTY) == FLASH_ACR_EMPTY) ? 1UL : 0UL);
1934 }
1935
1936 /** Set EMPTY flag information as Flash User area empty
1937 * @brief
1938 * @rmtoll FLASH_ACR FLASH_ACR_DBG_SWEN LL_FLASH_EnableDBGAccess
1939 * @retval None
1940 */
LL_FLASH_EnableDBGAccess(void)1941 __STATIC_INLINE void LL_FLASH_EnableDBGAccess(void)
1942 {
1943 SET_BIT(FLASH->ACR, FLASH_ACR_DBG_SWEN);
1944 }
1945
1946 /** Clear EMPTY flag information as Flash User area programmed
1947 * @brief
1948 * @rmtoll FLASH_ACR FLASH_ACR_DBG_SWEN LL_FLASH_DisableDBGAccess
1949 * @retval None
1950 */
LL_FLASH_DisableDBGAccess(void)1951 __STATIC_INLINE void LL_FLASH_DisableDBGAccess(void)
1952 {
1953 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DBG_SWEN);
1954 }
1955
1956 /**
1957 * @}
1958 */
1959
1960 /**
1961 * @}
1962 */
1963
1964 /**
1965 * @}
1966 */
1967
1968 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBG) */
1969
1970 /**
1971 * @}
1972 */
1973
1974 #ifdef __cplusplus
1975 }
1976 #endif
1977
1978 #endif /* STM32U0xx_LL_SYSTEM_H */
1979
