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Searched refs:RCC_PLLCFGR_PLLSRC_Pos (Results 1 – 25 of 110) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h4089 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
4090 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
4092 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
4093 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
Dstm32g050xx.h4108 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
4109 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
4111 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
4112 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
Dstm32g070xx.h4237 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
4238 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
4240 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
4241 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
Dstm32g031xx.h4269 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
4270 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
4272 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
4273 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
Dstm32g041xx.h4505 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
4506 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
4508 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
4509 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
Dstm32g051xx.h4605 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
4606 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
4608 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
4609 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
Dstm32g061xx.h4841 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
4842 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
4844 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
4845 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
Dstm32g071xx.h4940 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
4941 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
4943 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
4944 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
Dstm32g081xx.h5176 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
5177 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
5179 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
5180 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
Dstm32g0b0xx.h5228 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
5229 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
5231 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
5232 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h5990 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
5991 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000003 */
5993 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000001 */
5994 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000002 */
Dstm32wle5xx.h5990 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
5991 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000003 */
5993 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000001 */
5994 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000002 */
Dstm32wl5mxx.h6861 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
6862 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000003 */
6864 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000001 */
6865 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000002 */
Dstm32wl54xx.h6861 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
6862 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000003 */
6864 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000001 */
6865 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000002 */
Dstm32wl55xx.h6861 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
6862 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000003 */
6864 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000001 */
6865 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000002 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h5079 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
5080 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
5082 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
5083 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
Dstm32u083xx.h5844 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
5845 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
5847 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
5848 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
Dstm32u073xx.h5586 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
5587 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
5589 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
5590 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb50xx.h6506 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
6507 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
6509 #define RCC_PLLCFGR_PLLSRC_0 (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
6510 #define RCC_PLLCFGR_PLLSRC_1 (0x2U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
Dstm32wb1mxx.h6180 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
6181 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
6183 #define RCC_PLLCFGR_PLLSRC_0 (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
6184 #define RCC_PLLCFGR_PLLSRC_1 (0x2U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
Dstm32wb30xx.h6505 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
6506 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
6508 #define RCC_PLLCFGR_PLLSRC_0 (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
6509 #define RCC_PLLCFGR_PLLSRC_1 (0x2U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h6048 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
6049 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
6051 #define RCC_PLLCFGR_PLLSRC_0 (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
6052 #define RCC_PLLCFGR_PLLSRC_1 (0x2U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
Dstm32wb15xx.h6180 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
6181 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
6183 #define RCC_PLLCFGR_PLLSRC_0 (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
6184 #define RCC_PLLCFGR_PLLSRC_1 (0x2U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h7258 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
7259 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
7261 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
7262 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
Dstm32g411xc.h7423 #define RCC_PLLCFGR_PLLSRC_Pos (0U) macro
7424 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
7426 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
7427 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */

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