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Searched refs:RCC_APBENR2_ADCEN_Pos (Results 1 – 18 of 18) sorted by relevance

/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h4129 #define RCC_APBENR2_ADCEN_Pos (20U) macro
4130 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
Dstm32c031xx.h4289 #define RCC_APBENR2_ADCEN_Pos (20U) macro
4290 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
Dstm32c071xx.h4757 #define RCC_APBENR2_ADCEN_Pos (20U) macro
4758 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h4365 #define RCC_APBENR2_ADCEN_Pos (20U) macro
4366 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
Dstm32g050xx.h4402 #define RCC_APBENR2_ADCEN_Pos (20U) macro
4403 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
Dstm32g070xx.h4543 #define RCC_APBENR2_ADCEN_Pos (20U) macro
4544 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
Dstm32g031xx.h4579 #define RCC_APBENR2_ADCEN_Pos (20U) macro
4580 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
Dstm32g041xx.h4827 #define RCC_APBENR2_ADCEN_Pos (20U) macro
4828 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
Dstm32g051xx.h4939 #define RCC_APBENR2_ADCEN_Pos (20U) macro
4940 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
Dstm32g061xx.h5187 #define RCC_APBENR2_ADCEN_Pos (20U) macro
5188 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
Dstm32g071xx.h5304 #define RCC_APBENR2_ADCEN_Pos (20U) macro
5305 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
Dstm32g081xx.h5552 #define RCC_APBENR2_ADCEN_Pos (20U) macro
5553 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
Dstm32g0b0xx.h5592 #define RCC_APBENR2_ADCEN_Pos (20U) macro
5593 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
Dstm32g0c1xx.h6910 #define RCC_APBENR2_ADCEN_Pos (20U) macro
6911 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
Dstm32g0b1xx.h6662 #define RCC_APBENR2_ADCEN_Pos (20U) macro
6663 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h5447 #define RCC_APBENR2_ADCEN_Pos (20U) macro
5448 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
Dstm32u083xx.h6281 #define RCC_APBENR2_ADCEN_Pos (20U) macro
6282 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
Dstm32u073xx.h6017 #define RCC_APBENR2_ADCEN_Pos (20U) macro
6018 #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */