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Searched refs:RCC_APB1SMENR1_TIM4SMEN (Results 1 – 25 of 46) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_rcc.h2140 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
2203 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
2525 …HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)
2586 …HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_rcc.h2169 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
2230 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
2503 …HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)
2560 …HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_rcc.h3015 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
3114 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
3589 …HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)
3688 …HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_rcc.h3538 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
3592 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h7753 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32g411xc.h7933 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32g441xx.h8152 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32gbk1cb.h7902 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32g431xx.h7922 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32g4a1xx.h8543 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32g491xx.h8313 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32g473xx.h9021 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32g471xx.h8474 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32g483xx.h9251 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32g414xx.h11827 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32g474xx.h12597 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32g484xx.h12827 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l471xx.h11200 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32l475xx.h11364 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32l476xx.h11399 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32l486xx.h11618 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32l485xx.h11589 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32l4a6xx.h12772 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
Dstm32l496xx.h12432 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h11938 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk macro

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