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Searched refs:RCC_AHBENR_TSCEN (Results 1 – 25 of 46) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_rcc.h745 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
747 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
760 #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
909 #define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
920 #define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
Dstm32f3xx_ll_bus.h97 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal_rcc_ex.h972 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
974 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
978 #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
1522 #define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
1523 #define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
Dstm32f0xx_ll_bus.h91 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_rcc_ex.h598 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
600 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
603 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN))
605 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) != 0U)
606 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) == 0U)
Dstm32l0xx_ll_bus.h78 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_rcc.h735 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN); \
737 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN); \
766 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN)
1251 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) != 0U)
1263 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) == 0U)
Dstm32u0xx_ll_bus.h87 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h3635 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS controller c… macro
3639 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Dstm32f051x8.h3660 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS controller c… macro
3664 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Dstm32f071xb.h4100 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS controller c… macro
4104 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Dstm32f042x6.h7407 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS controller c… macro
7411 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Dstm32f048xx.h7383 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS controller c… macro
7387 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Dstm32f072xb.h7881 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS controller c… macro
7885 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Dstm32f091xc.h8343 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS controller c… macro
8347 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Dstm32f098xx.h8319 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS controller c… macro
8323 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Dstm32f078xx.h7857 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TS controller c… macro
7861 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Dstm32f030x6.h3078 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Dstm32f030x8.h3107 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Dstm32f031x6.h3204 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Dstm32f038xx.h3179 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h4045 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enabl… macro
Dstm32l062xx.h4176 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enabl… macro
Dstm32l053xx.h4192 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enabl… macro
Dstm32l072xx.h4224 #define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enabl… macro

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