RCC (reference) in projects: hal_stm32-latest

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Searched refs:RCC (Results 1 – 25 of 491) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
D	stm32mp1xx_hal_rcc.h	947 #define RCC_FLAG_HSIRDY ( (RCC->OCRDYR & RCC_OCRDYR_HSIRDY) == RCC_OCRDYR_HSIRDY ) 948 #define RCC_FLAG_HSIDIVRDY ( (RCC->OCRDYR & RCC_OCRDYR_HSIDIVRDY) == RCC_OCRDYR_HSIDIVRDY ) 949 #define RCC_FLAG_CSIRDY ( (RCC->OCRDYR & RCC_OCRDYR_CSIRDY) == RCC_OCRDYR_CSIRDY ) 950 #define RCC_FLAG_HSERDY ( (RCC->OCRDYR & RCC_OCRDYR_HSERDY) == RCC_OCRDYR_HSERDY ) 951 #define RCC_FLAG_AXICKRDY ( (RCC->OCRDYR & RCC_OCRDYR_AXICKRDY) == RCC_OCRDYR_AXICKRDY ) 952 #define RCC_FLAG_CKREST ( (RCC->OCRDYR & RCC_OCRDYR_CKREST) == RCC_OCRDYR_CKREST ) 955 #define RCC_FLAG_MPUSRCRDY ( (RCC->MPCKSELR & RCC_MPCKSELR_MPUSRCRDY) == RCC_MPCKSELR_MP… 958 #define RCC_FLAG_AXISSRCRDY ( (RCC->ASSCKSELR & RCC_ASSCKSELR_AXISSRCRDY) == RCC_ASSCKSELR_A… 961 #define RCC_FLAG_MCUSSRCRDY ( (RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRCRDY) == RCC_MSSCKSELR_M… 964 #define RCC_FLAG_PLL12SRCRDY ( (RCC->RCK12SELR & RCC_RCK12SELR_PLL12SRCRDY) == RCC_RCK12SELR_P… [all …]
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
D	stm32f4xx_hal_rcc_ex.h	972 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 974 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 979 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 981 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ 986 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 988 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 993 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 995 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 1000 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 1002 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ [all …]
D	stm32f4xx_hal_rcc.h	386 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ 388 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ 393 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ 395 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ 400 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ 402 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ 407 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ 409 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ 414 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 416 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ [all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
D	stm32u5xx_hal_rcc.h	677 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 679 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 684 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 686 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 691 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 693 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 698 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 700 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 705 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 707 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ [all …]
D	stm32u5xx_ll_rcc.h	34 #if defined(RCC) 1170 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) 1177 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) 1470 SET_BIT(RCC->CR, RCC_CR_CSSON); in LL_RCC_HSE_EnableCSS() 1480 SET_BIT(RCC->CR, RCC_CR_HSEBYP); in LL_RCC_HSE_EnableBypass() 1490 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); in LL_RCC_HSE_DisableBypass() 1500 SET_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Enable() 1510 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Disable() 1520 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL); in LL_RCC_HSE_IsReady() 1534 MODIFY_REG(RCC->CR, RCC_CR_HSEEXT, HSEMode); in LL_RCC_HSE_SetClockMode() [all …]
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
D	stm32g4xx_hal_rcc.h	518 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 520 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 526 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 528 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 534 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 536 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 542 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 544 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 550 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 552 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ [all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
D	stm32h7rsxx_hal_rcc.h	712 #define __HAL_RCC_AXI_INTERCONNECT_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AXI… 714 #define __HAL_RCC_AXI_MASTER_AHB_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AHB… 716 #define __HAL_RCC_AXI_MASTER_SDMMC1_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_SDM… 718 #define __HAL_RCC_AXI_MASTER_HPDMA1_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_HPD… 720 #define __HAL_RCC_AXI_MASTER_CPU_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_CPU… 722 #define __HAL_RCC_AXI_MASTER_GPU2D_0_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU… 724 #define __HAL_RCC_AXI_MASTER_GPU2D_1_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU… 726 #define __HAL_RCC_AXI_MASTER_GPU2D_CACHE_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GP… 728 #define __HAL_RCC_AXI_MASTER_DCMIPP_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_DCM… 730 #define __HAL_RCC_AXI_MASTER_DMA2D_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_DMA… [all …]
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
D	stm32l4xx_hal_rcc.h	639 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 641 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 647 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 649 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 656 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 658 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 665 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 667 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 673 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 675 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ [all …]
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
D	stm32f7xx_hal_rcc_ex.h	589 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 591 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 597 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ 599 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ 605 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 607 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 613 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 615 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 621 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 623 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ [all …]
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
D	stm32f2xx_hal_rcc.h	412 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ 414 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ 419 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ 421 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ 426 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ 428 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ 433 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 435 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 440 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 442 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ [all …]
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
D	stm32l5xx_hal_rcc.h	654 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 656 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 662 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 664 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 670 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 672 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 677 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 679 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 685 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 687 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ [all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
D	stm32h5xx_hal_rcc.h	734 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 736 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 742 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \ 744 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \ 751 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 753 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 761 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 763 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 770 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 772 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ [all …]
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
D	stm32g0xx_hal_rcc.h	861 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 863 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 870 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ 872 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ 881 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 883 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 889 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 891 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 898 SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \ 900 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \ [all …]
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
D	stm32l0xx_hal_rcc_ex.h	583 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\ 585 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\ 588 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN)) 590 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) != 0U) 591 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN) == 0U) 598 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ 600 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ 603 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN)) 605 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) != 0U) 606 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN) == 0U) [all …]
D	stm32l0xx_hal_rcc.h	678 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 680 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 686 SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\ 688 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\ 694 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 696 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 701 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) 702 #define __HAL_RCC_MIF_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) 703 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) 718 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\ [all …]
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
D	stm32wbaxx_hal_rcc.h	570 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 572 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 578 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 580 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 586 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 588 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 595 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 597 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 604 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 606 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ [all …]
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
D	stm32l1xx_hal_rcc.h	643 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ 645 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ 650 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ 652 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ 657 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ 659 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ 664 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ 666 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ 671 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ 673 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ [all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
D	stm32h7xx_hal_rcc.h	767 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ 769 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ 775 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ 777 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ 784 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ 786 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ 793 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 795 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 802 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 804 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ [all …]
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
D	stm32u0xx_hal_rcc.h	702 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 704 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 710 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ 712 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ 719 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 721 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 727 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 729 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 735 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN); \ 737 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN); \ [all …]
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
D	stm32c0xx_hal_rcc.h	698 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 700 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 706 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 708 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 714 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 716 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 721 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) 722 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) 723 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) 739 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ [all …]
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
D	stm32f1xx_hal_rcc_ex.h	629 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 631 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 635 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) 642 SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ 644 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ 648 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) 654 SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ 656 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ 661 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN)) 667 SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ [all …]
D	stm32f1xx_hal_rcc.h	323 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 325 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 331 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ 333 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ 339 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ 341 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ 347 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 349 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 353 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) 354 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) [all …]
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
D	stm32f3xx_hal_rcc_ex.h	1804 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ 1805 …MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSource_… 1825 …MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSource_… 1851 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__)) 1856 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV) 1876 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\ 1878 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\ 1882 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN)) 1889 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 1891 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ [all …]
D	stm32f3xx_hal_rcc.h	682 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ 684 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ 689 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ 691 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ 696 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ 698 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ 703 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ 705 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ 710 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ 712 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ [all …]
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
D	stm32f0xx_hal_rcc.h	622 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ 624 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ 629 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ 631 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ 636 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ 638 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ 643 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ 645 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ 650 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 652 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ [all …]

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