Lines Matching refs:RCC

712 #define __HAL_RCC_AXI_INTERCONNECT_CLK_GATING_ENABLE()      CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AXI…
714 #define __HAL_RCC_AXI_MASTER_AHB_CLK_GATING_ENABLE()        CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AHB…
716 #define __HAL_RCC_AXI_MASTER_SDMMC1_CLK_GATING_ENABLE()     CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_SDM…
718 #define __HAL_RCC_AXI_MASTER_HPDMA1_CLK_GATING_ENABLE()     CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_HPD…
720 #define __HAL_RCC_AXI_MASTER_CPU_CLK_GATING_ENABLE()        CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_CPU…
722 #define __HAL_RCC_AXI_MASTER_GPU2D_0_CLK_GATING_ENABLE()    CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU…
724 #define __HAL_RCC_AXI_MASTER_GPU2D_1_CLK_GATING_ENABLE()    CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU…
726 #define __HAL_RCC_AXI_MASTER_GPU2D_CACHE_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GP…
728 #define __HAL_RCC_AXI_MASTER_DCMIPP_CLK_GATING_ENABLE()     CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_DCM…
730 #define __HAL_RCC_AXI_MASTER_DMA2D_CLK_GATING_ENABLE()      CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_DMA…
732 #define __HAL_RCC_AXI_MASTER_LTDC_CLK_GATING_ENABLE()       CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_LTD…
734 #define __HAL_RCC_AXI_MASTER_GFXMMU_CLK_GATING_ENABLE()     CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GFX…
736 #define __HAL_RCC_AXI_SLAVE_GFXMMU_CLK_GATING_ENABLE()      CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GFX…
738 #define __HAL_RCC_AXI_SLAVE_AHB_CLK_GATING_ENABLE()         CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AHB…
740 #define __HAL_RCC_AXI_SLAVE_FMC_CLK_GATING_ENABLE()         CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_FMC…
742 #define __HAL_RCC_AXI_SLAVE_XSPI1_CLK_GATING_ENABLE()       CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_XSP…
744 #define __HAL_RCC_AXI_SLAVE_XSPI2_CLK_GATING_ENABLE()       CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_XSP…
746 #define __HAL_RCC_AXI_SLAVE_SRAM0_CLK_GATING_ENABLE()       CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AXI…
748 #define __HAL_RCC_AXI_SLAVE_SRAM1_CLK_GATING_ENABLE()       CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AXI…
750 #define __HAL_RCC_AXI_SLAVE_SRAM2_CLK_GATING_ENABLE()       CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AXI…
752 #define __HAL_RCC_AXI_SLAVE_SRAM3_CLK_GATING_ENABLE()       CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AXI…
754 #define __HAL_RCC_AXI_SLAVE_FLASH_CLK_GATING_ENABLE()       CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_FLI…
756 #define __HAL_RCC_AXI_SLAVE_EXTI_CLK_GATING_ENABLE()        CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_EXT…
758 #define __HAL_RCC_AXI_SLAVE_JTAG_CLK_GATING_ENABLE()        CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_JTA…
761 #define __HAL_RCC_AXI_INTERCONNECT_CLK_GATING_DISABLE()     SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AXICK…
763 #define __HAL_RCC_AXI_MASTER_AHB_CLK_GATING_DISABLE()       SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AHBCK…
765 #define __HAL_RCC_AXI_MASTER_SDMMC1_CLK_GATING_DISABLE()    SET_BIT(RCC->CKGDISR, RCC_CKGDISR_SDMMC…
767 #define __HAL_RCC_AXI_MASTER_HPDMA1_CLK_GATING_DISABLE()    SET_BIT(RCC->CKGDISR, RCC_CKGDISR_HPDMA…
769 #define __HAL_RCC_AXI_MASTER_CPU_CLK_GATING_DISABLE()       SET_BIT(RCC->CKGDISR, RCC_CKGDISR_CPUCK…
771 #define __HAL_RCC_AXI_MASTER_GPU_0_CLK_GATING_DISABLE()     SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2D…
773 #define __HAL_RCC_AXI_MASTER_GPU_1_CLK_GATING_DISABLE()     SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2D…
775 #define __HAL_RCC_AXI_MASTER_GPU_CACHE_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2D…
777 #define __HAL_RCC_AXI_MASTER_DCMIPP_CLK_GATING_DISABLE()    SET_BIT(RCC->CKGDISR, RCC_CKGDISR_DCMIP…
779 #define __HAL_RCC_AXI_MASTER_DMA2D_CLK_GATING_DISABLE()     SET_BIT(RCC->CKGDISR, RCC_CKGDISR_DMA2D…
781 #define __HAL_RCC_AXI_MASTER_LTDC_CLK_GATING_DISABLE()      SET_BIT(RCC->CKGDISR, RCC_CKGDISR_LTDCC…
783 #define __HAL_RCC_AXI_MASTER_GFXMMU_CLK_GATING_DISABLE()    SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GFXMM…
785 #define __HAL_RCC_AXI_SLAVE_GFXMMU_CLK_GATING_DISABLE()     SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GFXMM…
787 #define __HAL_RCC_AXI_SLAVE_AHB_CLK_GATING_DISABLE()        SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AHBSC…
789 #define __HAL_RCC_AXI_SLAVE_FMC_CLK_GATING_DISABLE()        SET_BIT(RCC->CKGDISR, RCC_CKGDISR_FMCCK…
791 #define __HAL_RCC_AXI_SLAVE_XSPI1_CLK_GATING_DISABLE()      SET_BIT(RCC->CKGDISR, RCC_CKGDISR_XSPI1…
793 #define __HAL_RCC_AXI_SLAVE_XSPI2_CLK_GATING_DISABLE()      SET_BIT(RCC->CKGDISR, RCC_CKGDISR_XSPI2…
795 #define __HAL_RCC_AXI_SLAVE_SRAM0_CLK_GATING_DISABLE()      SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISR…
797 #define __HAL_RCC_AXI_SLAVE_SRAM1_CLK_GATING_DISABLE()      SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISR…
799 #define __HAL_RCC_AXI_SLAVE_SRAM2_CLK_GATING_DISABLE()      SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISR…
801 #define __HAL_RCC_AXI_SLAVE_SRAM3_CLK_GATING_DISABLE()      SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISR…
803 #define __HAL_RCC_AXI_SLAVE_FLASH_CLK_GATING_DISABLE()      SET_BIT(RCC->CKGDISR, RCC_CKGDISR_FLIFT…
805 #define __HAL_RCC_AXI_SLAVE_EXTI_CLK_GATING_DISABLE()       SET_BIT(RCC->CKGDISR, RCC_CKGDISR_EXTIC…
807 #define __HAL_RCC_AXI_SLAVE_JTAG_CLK_GATING_DISABLE()       SET_BIT(RCC->CKGDISR, RCC_CKGDISR_JTAGC…
823                                             SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN);\
825                                             tmpreg = READ_REG(RCC->AHB1ENR);\
831                                             SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
833                                             tmpreg = READ_REG(RCC->AHB1ENR);\
840                                             SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
842                                             tmpreg = READ_REG(RCC->AHB1ENR);\
848                                             SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
850                                             tmpreg = READ_REG(RCC->AHB1ENR);\
856                                             SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
858                                             tmpreg = READ_REG(RCC->AHB1ENR);\
865                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
867                                                 tmpreg = READ_REG(RCC->AHB1ENR);\
873                                                 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGFSEN);\
875                                                 tmpreg = READ_REG(RCC->AHB1ENR);\
881                                             SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USBPHYCEN);\
883                                             tmpreg = READ_REG(RCC->AHB1ENR);\
889                                             SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADF1EN);\
891                                             tmpreg = READ_REG(RCC->AHB1ENR);\
896 #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN)
898 #define __HAL_RCC_ADC12_CLK_DISABLE()  CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN)
901 #define __HAL_RCC_ETH1MAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN)
903 #define __HAL_RCC_ETH1TX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN)
905 #define __HAL_RCC_ETH1RX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN)
908 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN)
910 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGFSEN)
912 #define __HAL_RCC_USBPHYC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USBPHYCEN)
914 #define __HAL_RCC_ADF1_CLK_DISABLE()   CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADF1EN)
930                                             SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PSSIEN);\
932                                             tmpreg = READ_REG(RCC->AHB2ENR);\
938                                             SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
940                                             tmpreg = READ_REG(RCC->AHB2ENR);\
946                                             SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\
948                                             tmpreg = READ_REG(RCC->AHB2ENR);\
954                                             SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM1EN);\
956                                             tmpreg = READ_REG(RCC->AHB2ENR);\
962                                             SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN);\
964                                             tmpreg = READ_REG(RCC->AHB2ENR);\
968 #define __HAL_RCC_PSSI_CLK_DISABLE()   CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PSSIEN)
970 #define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN)
972 #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN)
974 #define __HAL_RCC_SRAM1_CLK_DISABLE()  CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM1EN)
976 #define __HAL_RCC_SRAM2_CLK_DISABLE()  CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN)
992                                             SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_RNGEN);\
994                                             tmpreg = READ_REG(RCC->AHB3ENR);\
1000                                             SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_HASHEN);\
1002                                             tmpreg = READ_REG(RCC->AHB3ENR);\
1009                                             SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_CRYPEN);\
1011                                             tmpreg = READ_REG(RCC->AHB3ENR);\
1019                                             SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SAESEN);\
1021                                             tmpreg = READ_REG(RCC->AHB3ENR);\
1029                                             SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PKAEN);\
1031                                             tmpreg = READ_REG(RCC->AHB3ENR);\
1036 #define __HAL_RCC_RNG_CLK_DISABLE()    CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_RNGEN)
1038 #define __HAL_RCC_HASH_CLK_DISABLE()   CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_HASHEN)
1041 #define __HAL_RCC_CRYP_CLK_DISABLE()   CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_CRYPEN)
1045 #define __HAL_RCC_SAES_CLK_DISABLE()   CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SAESEN)
1049 #define __HAL_RCC_PKA_CLK_DISABLE()    CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PKAEN)
1066                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
1068                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1074                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
1076                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1082                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
1084                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1090                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
1092                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1098                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
1100                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1106                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
1108                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1114                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
1116                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1122                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
1124                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1130                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOMEN);\
1132                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1138                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIONEN);\
1140                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1146                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOOEN);\
1148                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1154                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOPEN);\
1156                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1162                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
1164                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1170                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
1172                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1177 #define __HAL_RCC_GPIOA_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN)
1179 #define __HAL_RCC_GPIOB_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN)
1181 #define __HAL_RCC_GPIOC_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN)
1183 #define __HAL_RCC_GPIOD_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN)
1185 #define __HAL_RCC_GPIOE_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN)
1187 #define __HAL_RCC_GPIOF_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN)
1189 #define __HAL_RCC_GPIOG_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN)
1191 #define __HAL_RCC_GPIOH_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN)
1193 #define __HAL_RCC_GPIOM_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOMEN)
1195 #define __HAL_RCC_GPION_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIONEN)
1197 #define __HAL_RCC_GPIOO_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOOEN)
1199 #define __HAL_RCC_GPIOP_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOPEN)
1201 #define __HAL_RCC_CRC_CLK_DISABLE()    CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN)
1203 #define __HAL_RCC_BKPRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN)
1219                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_HPDMA1EN);\
1221                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1227                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_DMA2DEN);\
1229                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1236                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_JPEGEN);\
1238                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1245                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_FMCEN);\
1247                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1253                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI1EN);\
1255                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1261                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_SDMMC1EN);\
1263                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1269                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI2EN);\
1271                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1277                                           SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPIMEN);\
1279                                           tmpreg = READ_REG(RCC->AHB5ENR);\
1286                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GFXMMUEN);\
1288                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1296                                             SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GPU2DEN);\
1298                                             tmpreg = READ_REG(RCC->AHB5ENR);\
1303 #define __HAL_RCC_HPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_HPDMA1EN)
1305 #define __HAL_RCC_DMA2D_CLK_DISABLE()  CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_DMA2DEN)
1308 #define __HAL_RCC_JPEG_CLK_DISABLE()   CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_JPEGEN)
1311 #define __HAL_RCC_FMC_CLK_DISABLE()    CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_FMCEN)
1313 #define __HAL_RCC_XSPI1_CLK_DISABLE()  CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI1EN)
1315 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_SDMMC1EN)
1317 #define __HAL_RCC_XSPI2_CLK_DISABLE()  CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI2EN)
1319 #define __HAL_RCC_XSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPIMEN)
1322 #define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GFXMMUEN)
1326 #define __HAL_RCC_GPU2D_CLK_DISABLE()  CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GPU2DEN)
1343                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN);\
1345                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1351                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN);\
1353                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1359                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN);\
1361                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1367                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN);\
1369                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1375                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN);\
1377                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1383                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN);\
1385                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1391                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM12EN);\
1393                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1399                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM13EN);\
1401                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1407                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM14EN);\
1409                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1415                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN);\
1417                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1423                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN);\
1425                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1431                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN);\
1433                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1439                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN);\
1441                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1447                                             SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPDIFRXEN);\
1449                                             tmpreg = READ_REG(RCC->APB1ENR1);\
1455                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN);\
1457                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1463                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN);\
1465                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1471                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN);\
1473                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1479                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN);\
1481                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1487                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN);\
1489                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1495                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN);\
1497                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1503                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN);\
1505                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1511                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN);\
1513                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1519                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CECEN);\
1521                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1527                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART7EN);\
1529                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1535                                            SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART8EN);\
1537                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1543                                            SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_CRSEN);\
1545                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1551                                            SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_MDIOSEN);\
1553                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1559                                            SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCANEN);\
1561                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1567                                            SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN);\
1569                                            tmpreg = READ_REG(RCC->APB1ENR1);\
1573 #define __HAL_RCC_TIM2_CLK_DISABLE()   CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
1575 #define __HAL_RCC_TIM3_CLK_DISABLE()   CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
1577 #define __HAL_RCC_TIM4_CLK_DISABLE()   CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
1579 #define __HAL_RCC_TIM5_CLK_DISABLE()   CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
1581 #define __HAL_RCC_TIM6_CLK_DISABLE()   CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
1583 #define __HAL_RCC_TIM7_CLK_DISABLE()   CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
1585 #define __HAL_RCC_TIM12_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM12EN)
1587 #define __HAL_RCC_TIM13_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM13EN)
1589 #define __HAL_RCC_TIM14_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM14EN)
1591 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
1593 #define __HAL_RCC_SPI2_CLK_DISABLE()   CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
1595 #define __HAL_RCC_SPI3_CLK_DISABLE()   CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
1597 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPDIFRXEN)
1599 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
1601 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
1603 #define __HAL_RCC_UART4_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
1605 #define __HAL_RCC_UART5_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
1607 #define __HAL_RCC_I2C1_CLK_DISABLE()   CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN)
1609 #define __HAL_RCC_I2C2_CLK_DISABLE()   CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
1611 #define __HAL_RCC_I2C3_CLK_DISABLE()   CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
1613 #define __HAL_RCC_I3C1_CLK_DISABLE()   CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN)
1615 #define __HAL_RCC_CEC_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CECEN)
1617 #define __HAL_RCC_UART7_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART7EN)
1619 #define __HAL_RCC_UART8_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART8EN)
1621 #define __HAL_RCC_CRS_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_CRSEN)
1623 #define __HAL_RCC_MDIOS_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_MDIOSEN)
1625 #define __HAL_RCC_FDCAN_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCANEN)
1627 #define __HAL_RCC_UCPD1_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN)
1643                                             SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
1645                                             tmpreg = READ_REG(RCC->APB2ENR);\
1651                                             SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
1653                                             tmpreg = READ_REG(RCC->APB2ENR);\
1659                                             SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
1661                                             tmpreg = READ_REG(RCC->APB2ENR);\
1667                                             SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
1669                                             tmpreg = READ_REG(RCC->APB2ENR);\
1675                                             SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
1677                                             tmpreg = READ_REG(RCC->APB2ENR);\
1683                                             SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
1685                                             tmpreg = READ_REG(RCC->APB2ENR);\
1691                                             SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
1693                                             tmpreg = READ_REG(RCC->APB2ENR);\
1699                                             SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
1701                                             tmpreg = READ_REG(RCC->APB2ENR);\
1707                                             SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
1709                                             tmpreg = READ_REG(RCC->APB2ENR);\
1715                                             SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
1717                                             tmpreg = READ_REG(RCC->APB2ENR);\
1723                                             SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
1725                                             tmpreg = READ_REG(RCC->APB2ENR);\
1729 #define __HAL_RCC_TIM1_CLK_DISABLE()   CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
1731 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
1733 #define __HAL_RCC_SPI1_CLK_DISABLE()   CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
1735 #define __HAL_RCC_SPI4_CLK_DISABLE()   CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN)
1737 #define __HAL_RCC_TIM15_CLK_DISABLE()  CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
1739 #define __HAL_RCC_TIM16_CLK_DISABLE()  CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
1741 #define __HAL_RCC_TIM17_CLK_DISABLE()  CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
1743 #define __HAL_RCC_TIM9_CLK_DISABLE()   CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN)
1745 #define __HAL_RCC_SPI5_CLK_DISABLE()   CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN)
1747 #define __HAL_RCC_SAI1_CLK_DISABLE()   CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
1749 #define __HAL_RCC_SAI2_CLK_DISABLE()   CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
1765                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SBSEN);\
1767                                             tmpreg = READ_REG(RCC->APB4ENR);\
1773                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
1775                                             tmpreg = READ_REG(RCC->APB4ENR);\
1781                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
1783                                             tmpreg = READ_REG(RCC->APB4ENR);\
1789                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
1791                                             tmpreg = READ_REG(RCC->APB4ENR);\
1797                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
1799                                             tmpreg = READ_REG(RCC->APB4ENR);\
1805                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
1807                                             tmpreg = READ_REG(RCC->APB4ENR);\
1813                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
1815                                             tmpreg = READ_REG(RCC->APB4ENR);\
1821                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
1823                                             tmpreg = READ_REG(RCC->APB4ENR);\
1829                                                SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
1831                                                tmpreg = READ_REG(RCC->APB4ENR);\
1837                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
1839                                             tmpreg = READ_REG(RCC->APB4ENR);\
1843 #define __HAL_RCC_SBS_CLK_DISABLE()     CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_SBSEN)
1845 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN)
1847 #define __HAL_RCC_SPI6_CLK_DISABLE()   CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN)
1849 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN)
1851 #define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN)
1853 #define __HAL_RCC_LPTIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN)
1855 #define __HAL_RCC_LPTIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN)
1857 #define __HAL_RCC_VREF_CLK_DISABLE()   CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN)
1859 #define __HAL_RCC_RTCAPB_CLK_DISABLE()    CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN)
1861 #define __HAL_RCC_DTS_CLK_DISABLE()    CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN)
1877                                             SET_BIT(RCC->APB5ENR, RCC_APB5ENR_LTDCEN);\
1879                                             tmpreg = READ_REG(RCC->APB5ENR);\
1885                                             SET_BIT(RCC->APB5ENR, RCC_APB5ENR_DCMIPPEN);\
1887                                             tmpreg = READ_REG(RCC->APB5ENR);\
1893                                             SET_BIT(RCC->APB5ENR, RCC_APB5ENR_GFXTIMEN);\
1895                                             tmpreg = READ_REG(RCC->APB5ENR);\
1899 #define __HAL_RCC_LTDC_CLK_DISABLE()   CLEAR_BIT(RCC->APB5ENR, RCC_APB5ENR_LTDCEN)
1901 #define __HAL_RCC_DCMIPP_CLK_DISABLE() CLEAR_BIT(RCC->APB5ENR, RCC_APB5ENR_DCMIPPEN)
1903 #define __HAL_RCC_GFXTIM_CLK_DISABLE() CLEAR_BIT(RCC->APB5ENR, RCC_APB5ENR_GFXTIMEN)
1917 #define __HAL_RCC_GPDMA1_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U)
1919 #define __HAL_RCC_ADC12_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN) != 0U)
1922 #define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN) != 0U)
1924 #define __HAL_RCC_ETH1TX_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN) != 0U)
1926 #define __HAL_RCC_ETH1RX_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN) != 0U)
1929 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN) != 0U)
1931 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGFSEN) != 0U)
1933 #define __HAL_RCC_USBPHYC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USBPHYCEN) != 0U)
1935 #define __HAL_RCC_ADF1_IS_CLK_ENABLED()    (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADF1EN) != 0U)
1949 #define __HAL_RCC_PSSI_IS_CLK_ENABLED()    (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PSSIEN) != 0U)
1951 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) != 0U)
1953 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN) != 0U)
1955 #define __HAL_RCC_SRAM1_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM1EN) != 0U)
1957 #define __HAL_RCC_SRAM2_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) != 0U)
1971 #define __HAL_RCC_RNG_IS_CLK_ENABLED()     (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_RNGEN) != 0U)
1973 #define __HAL_RCC_HASH_IS_CLK_ENABLED()    (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_HASHEN) != 0U)
1976 #define __HAL_RCC_CRYP_IS_CLK_ENABLED()    (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_CRYPEN) != 0U)
1980 #define __HAL_RCC_SAES_IS_CLK_ENABLED()    (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SAESEN) != 0U)
1984 #define __HAL_RCC_PKA_IS_CLK_ENABLED()     (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PKAEN) != 0U)
1999 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN) != 0U)
2001 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN) != 0U)
2003 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN) != 0U)
2005 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN) != 0U)
2007 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN) != 0U)
2009 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN) != 0U)
2011 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN) != 0U)
2013 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN) != 0U)
2015 #define __HAL_RCC_GPIOM_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOMEN) != 0U)
2017 #define __HAL_RCC_GPION_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIONEN) != 0U)
2019 #define __HAL_RCC_GPIOO_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOOEN) != 0U)
2021 #define __HAL_RCC_GPIOP_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOPEN) != 0U)
2023 #define __HAL_RCC_CRC_IS_CLK_ENABLED()     (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN) != 0U)
2025 #define __HAL_RCC_BKPRAM_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN) != 0U)
2039 #define __HAL_RCC_HPDMA1_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_HPDMA1EN) != 0U)
2041 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_DMA2DEN) != 0U)
2044 #define __HAL_RCC_JPEG_IS_CLK_ENABLED()    (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_JPEGEN) != 0U)
2047 #define __HAL_RCC_FMC_IS_CLK_ENABLED()     (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_FMCEN) != 0U)
2049 #define __HAL_RCC_XSPI1_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI1EN) != 0U)
2051 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_SDMMC1EN) != 0U)
2053 #define __HAL_RCC_XSPI2_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI2EN) != 0U)
2055 #define __HAL_RCC_XSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPIMEN) != 0U)
2058 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GFXMMUEN) != 0U)
2062 #define __HAL_RCC_GPU2D_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GPU2DEN) != 0U)
2077 #define __HAL_RCC_TIM2_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)
2079 #define __HAL_RCC_TIM3_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)
2081 #define __HAL_RCC_TIM4_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)
2083 #define __HAL_RCC_TIM5_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
2085 #define __HAL_RCC_TIM6_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)
2087 #define __HAL_RCC_TIM7_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)
2089 #define __HAL_RCC_TIM12_IS_CLK_ENABLED()   (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM12EN) != 0U)
2091 #define __HAL_RCC_TIM13_IS_CLK_ENABLED()   (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM13EN) != 0U)
2093 #define __HAL_RCC_TIM14_IS_CLK_ENABLED()   (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM14EN) != 0U)
2095 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)
2097 #define __HAL_RCC_WWDG_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)
2099 #define __HAL_RCC_SPI2_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)
2101 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)
2103 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPDIFRXEN) != 0U)
2105 #define __HAL_RCC_USART2_IS_CLK_ENABLED()  (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)
2107 #define __HAL_RCC_USART3_IS_CLK_ENABLED()  (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)
2109 #define __HAL_RCC_UART4_IS_CLK_ENABLED()   (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)
2111 #define __HAL_RCC_UART5_IS_CLK_ENABLED()   (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U)
2113 #define __HAL_RCC_I2C1_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN) != 0U)
2115 #define __HAL_RCC_I2C2_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)
2117 #define __HAL_RCC_I2C3_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)
2119 #define __HAL_RCC_I3C1_IS_CLK_ENABLED()    (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN) != 0U)
2121 #define __HAL_RCC_CEC_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CECEN) != 0U)
2123 #define __HAL_RCC_UART7_IS_CLK_ENABLED()   (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART7EN) != 0U)
2125 #define __HAL_RCC_UART8_IS_CLK_ENABLED()   (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART8EN) != 0U)
2127 #define __HAL_RCC_CRS_IS_CLK_ENABLED()     (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_CRSEN) != 0U)
2129 #define __HAL_RCC_MDIOS_IS_CLK_ENABLED()   (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_MDIOSEN) != 0U)
2131 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED()   (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCANEN) != 0U)
2133 #define __HAL_RCC_UCPD1_IS_CLK_ENABLED()   (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U)
2147 #define __HAL_RCC_TIM1_IS_CLK_ENABLED()    (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)
2149 #define __HAL_RCC_USART1_IS_CLK_ENABLED()  (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
2151 #define __HAL_RCC_SPI1_IS_CLK_ENABLED()    (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
2153 #define __HAL_RCC_SPI4_IS_CLK_ENABLED()    (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U)
2155 #define __HAL_RCC_TIM15_IS_CLK_ENABLED()   (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)
2157 #define __HAL_RCC_TIM16_IS_CLK_ENABLED()   (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)
2159 #define __HAL_RCC_TIM17_IS_CLK_ENABLED()   (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)
2161 #define __HAL_RCC_TIM9_IS_CLK_ENABLED()    (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN) != 0U)
2163 #define __HAL_RCC_SPI5_IS_CLK_ENABLED()    (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN) != 0U)
2165 #define __HAL_RCC_SAI1_IS_CLK_ENABLED()    (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)
2167 #define __HAL_RCC_SAI2_IS_CLK_ENABLED()    (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U)
2181 #define __HAL_RCC_SBS_IS_CLK_ENABLED()     (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SBSEN) != 0U)
2183 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN) != 0U)
2185 #define __HAL_RCC_SPI6_IS_CLK_ENABLED()    (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN) != 0U)
2187 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()  (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN) != 0U)
2189 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED()  (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN) != 0U)
2191 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED()  (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN) != 0U)
2193 #define __HAL_RCC_LPTIM5_IS_CLK_ENABLED()  (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN) != 0U)
2195 #define __HAL_RCC_VREF_IS_CLK_ENABLED()    (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN) != 0U)
2197 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()     (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN) != 0U)
2199 #define __HAL_RCC_DTS_IS_CLK_ENABLED()     (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN) != 0U)
2213 #define __HAL_RCC_LTDC_IS_CLK_ENABLED()    (READ_BIT(RCC->APB5ENR, RCC_APB5ENR_LTDCEN) != 0U)
2215 #define __HAL_RCC_DCMIPP_IS_CLK_ENABLED()  (READ_BIT(RCC->APB5ENR, RCC_APB5ENR_DCMIPPEN) != 0U)
2217 #define __HAL_RCC_GFXTIM_IS_CLK_ENABLED()  (READ_BIT(RCC->APB5ENR, RCC_APB5ENR_GFXTIMEN) != 0U)
2228 #define __HAL_RCC_AHB1_FORCE_RESET()       WRITE_REG(RCC->AHB1RSTR, 0x8E008030UL)
2229 #define __HAL_RCC_AHB1_RELEASE_RESET()     WRITE_REG(RCC->AHB1RSTR, 0UL)
2231 #define __HAL_RCC_GPDMA1_FORCE_RESET()     SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST)
2232 #define __HAL_RCC_GPDMA1_RELEASE_RESET()   CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST)
2234 #define __HAL_RCC_ADC12_FORCE_RESET()      SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ADC12RST)
2235 #define __HAL_RCC_ADC12_RELEASE_RESET()    CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ADC12RST)
2238 #define __HAL_RCC_ETH1_FORCE_RESET()       SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETH1RST)
2239 #define __HAL_RCC_ETH1_RELEASE_RESET()     CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETH1RST)
2242 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET()   SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_OTGHSRST)
2243 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_OTGHSRST)
2245 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_OTGFSRST)
2246 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_OTGFSRST)
2248 #define __HAL_RCC_USBPHYC_FORCE_RESET()    SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_USBPHYCRST)
2249 #define __HAL_RCC_USBPHYC_RELEASE_RESET()  CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_USBPHYCRST)
2251 #define __HAL_RCC_ADF1_FORCE_RESET()       SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ADF1RST)
2252 #define __HAL_RCC_ADF1_RELEASE_RESET()     CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ADF1RST)
2263 #define __HAL_RCC_AHB2_FORCE_RESET()       WRITE_REG(RCC->AHB2RSTR, 0x00004202UL)
2264 #define __HAL_RCC_AHB2_RELEASE_RESET()     WRITE_REG(RCC->AHB2RSTR, 0UL)
2266 #define __HAL_RCC_PSSI_FORCE_RESET()       SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PSSIRST)
2267 #define __HAL_RCC_PSSI_RELEASE_RESET()     CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PSSIRST)
2269 #define __HAL_RCC_SDMMC2_FORCE_RESET()     SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC2RST)
2270 #define __HAL_RCC_SDMMC2_RELEASE_RESET()   CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC2RST)
2272 #define __HAL_RCC_CORDIC_FORCE_RESET()     SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_CORDICRST)
2273 #define __HAL_RCC_CORDIC_RELEASE_RESET()   CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_CORDICRST)
2284 #define __HAL_RCC_AHB3_FORCE_RESET()       WRITE_REG(RCC->AHB3RSTR, 0x00000057UL)
2285 #define __HAL_RCC_AHB3_RELEASE_RESET()     WRITE_REG(RCC->AHB3RSTR, 0UL)
2287 #define __HAL_RCC_RNG_FORCE_RESET()        SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_RNGRST)
2288 #define __HAL_RCC_RNG_RELEASE_RESET()      CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_RNGRST)
2290 #define __HAL_RCC_HASH_FORCE_RESET()       SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_HASHRST)
2291 #define __HAL_RCC_HASH_RELEASE_RESET()     CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_HASHRST)
2294 #define __HAL_RCC_CRYP_FORCE_RESET()       SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_CRYPRST)
2295 #define __HAL_RCC_CRYP_RELEASE_RESET()     CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_CRYPRST)
2299 #define __HAL_RCC_SAES_FORCE_RESET()       SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_SAESRST)
2300 #define __HAL_RCC_SAES_RELEASE_RESET()     CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_SAESRST)
2304 #define __HAL_RCC_PKA_FORCE_RESET()        SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_PKARST)
2305 #define __HAL_RCC_PKA_RELEASE_RESET()      CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_PKARST)
2317 #define __HAL_RCC_AHB4_FORCE_RESET()       WRITE_REG(RCC->AHB4RSTR, 0x0008B0FFUL)
2318 #define __HAL_RCC_AHB4_RELEASE_RESET()     WRITE_REG(RCC->AHB4RSTR, 0UL)
2320 #define __HAL_RCC_GPIOA_FORCE_RESET()      SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOARST)
2321 #define __HAL_RCC_GPIOA_RELEASE_RESET()    CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOARST)
2323 #define __HAL_RCC_GPIOB_FORCE_RESET()      SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOBRST)
2324 #define __HAL_RCC_GPIOB_RELEASE_RESET()    CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOBRST)
2326 #define __HAL_RCC_GPIOC_FORCE_RESET()      SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOCRST)
2327 #define __HAL_RCC_GPIOC_RELEASE_RESET()    CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOCRST)
2329 #define __HAL_RCC_GPIOD_FORCE_RESET()      SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIODRST)
2330 #define __HAL_RCC_GPIOD_RELEASE_RESET()    CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIODRST)
2332 #define __HAL_RCC_GPIOE_FORCE_RESET()      SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOERST)
2333 #define __HAL_RCC_GPIOE_RELEASE_RESET()    CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOERST)
2335 #define __HAL_RCC_GPIOF_FORCE_RESET()      SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOFRST)
2336 #define __HAL_RCC_GPIOF_RELEASE_RESET()    CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOFRST)
2338 #define __HAL_RCC_GPIOG_FORCE_RESET()      SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOGRST)
2339 #define __HAL_RCC_GPIOG_RELEASE_RESET()    CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOGRST)
2341 #define __HAL_RCC_GPIOH_FORCE_RESET()      SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOHRST)
2342 #define __HAL_RCC_GPIOH_RELEASE_RESET()    CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOHRST)
2344 #define __HAL_RCC_GPIOM_FORCE_RESET()      SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOMRST)
2345 #define __HAL_RCC_GPIOM_RELEASE_RESET()    CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOMRST)
2347 #define __HAL_RCC_GPION_FORCE_RESET()      SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIONRST)
2348 #define __HAL_RCC_GPION_RELEASE_RESET()    CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIONRST)
2350 #define __HAL_RCC_GPIOO_FORCE_RESET()      SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOORST)
2351 #define __HAL_RCC_GPIOO_RELEASE_RESET()    CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOORST)
2353 #define __HAL_RCC_GPIOP_FORCE_RESET()      SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOPRST)
2354 #define __HAL_RCC_GPIOP_RELEASE_RESET()    CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOPRST)
2356 #define __HAL_RCC_CRC_FORCE_RESET()        SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_CRCRST)
2357 #define __HAL_RCC_CRC_RELEASE_RESET()      CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_CRCRST)
2368 #define __HAL_RCC_AHB5_FORCE_RESET()       WRITE_REG(RCC->AHB5RSTR, 0x0018513BUL)
2369 #define __HAL_RCC_AHB5_RELEASE_RESET()     WRITE_REG(RCC->AHB5RSTR, 0UL)
2371 #define __HAL_RCC_HPDMA1_FORCE_RESET()     SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_HPDMA1RST)
2372 #define __HAL_RCC_HPDMA1_RELEASE_RESET()   CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_HPDMA1RST)
2374 #define __HAL_RCC_DMA2D_FORCE_RESET()      SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_DMA2DRST)
2375 #define __HAL_RCC_DMA2D_RELEASE_RESET()    CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_DMA2DRST)
2378 #define __HAL_RCC_JPEG_FORCE_RESET()       SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_JPEGRST)
2379 #define __HAL_RCC_JPEG_RELEASE_RESET()     CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_JPEGRST)
2382 #define __HAL_RCC_FMC_FORCE_RESET()        SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_FMCRST)
2383 #define __HAL_RCC_FMC_RELEASE_RESET()      CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_FMCRST)
2385 #define __HAL_RCC_XSPI1_FORCE_RESET()      SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPI1RST)
2386 #define __HAL_RCC_XSPI1_RELEASE_RESET()    CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPI1RST)
2388 #define __HAL_RCC_SDMMC1_FORCE_RESET()     SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_SDMMC1RST)
2389 #define __HAL_RCC_SDMMC1_RELEASE_RESET()   CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_SDMMC1RST)
2391 #define __HAL_RCC_XSPI2_FORCE_RESET()      SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPI2RST)
2392 #define __HAL_RCC_XSPI2_RELEASE_RESET()    CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPI2RST)
2394 #define __HAL_RCC_XSPIM_FORCE_RESET()   SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPIMRST)
2395 #define __HAL_RCC_XSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPIMRST)
2398 #define __HAL_RCC_GFXMMU_FORCE_RESET()     SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_GFXMMURST)
2399 #define __HAL_RCC_GFXMMU_RELEASE_RESET()   CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_GFXMMURST)
2403 #define __HAL_RCC_GPU2D_FORCE_RESET()      SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_GPU2DRST)
2404 #define __HAL_RCC_GPU2D_RELEASE_RESET()    CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_GPU2DRST)
2417                                                 WRITE_REG(RCC->APB1RSTR1, 0xC8FFC3FFUL); \
2418                                                 WRITE_REG(RCC->APB1RSTR2, 0x08000122UL); \
2421                                                 WRITE_REG(RCC->APB1RSTR1, 0UL); \
2422                                                 WRITE_REG(RCC->APB1RSTR2, 0UL); \
2425 #define __HAL_RCC_TIM2_FORCE_RESET()       SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
2426 #define __HAL_RCC_TIM2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
2428 #define __HAL_RCC_TIM3_FORCE_RESET()       SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
2429 #define __HAL_RCC_TIM3_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
2431 #define __HAL_RCC_TIM4_FORCE_RESET()       SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
2432 #define __HAL_RCC_TIM4_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
2434 #define __HAL_RCC_TIM5_FORCE_RESET()       SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
2435 #define __HAL_RCC_TIM5_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
2437 #define __HAL_RCC_TIM6_FORCE_RESET()       SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
2438 #define __HAL_RCC_TIM6_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
2440 #define __HAL_RCC_TIM7_FORCE_RESET()       SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
2441 #define __HAL_RCC_TIM7_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
2443 #define __HAL_RCC_TIM12_FORCE_RESET()      SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM12RST)
2444 #define __HAL_RCC_TIM12_RELEASE_RESET()    CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM12RST)
2446 #define __HAL_RCC_TIM13_FORCE_RESET()      SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM13RST)
2447 #define __HAL_RCC_TIM13_RELEASE_RESET()    CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM13RST)
2449 #define __HAL_RCC_TIM14_FORCE_RESET()      SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM14RST)
2450 #define __HAL_RCC_TIM14_RELEASE_RESET()    CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM14RST)
2452 #define __HAL_RCC_LPTIM1_FORCE_RESET()     SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
2453 #define __HAL_RCC_LPTIM1_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
2455 #define __HAL_RCC_SPI2_FORCE_RESET()       SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
2456 #define __HAL_RCC_SPI2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
2458 #define __HAL_RCC_SPI3_FORCE_RESET()       SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
2459 #define __HAL_RCC_SPI3_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
2461 #define __HAL_RCC_SPDIFRX_FORCE_RESET()    SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPDIFRXRST)
2462 #define __HAL_RCC_SPDIFRX_RELEASE_RESET()  CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPDIFRXRST)
2464 #define __HAL_RCC_USART2_FORCE_RESET()     SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
2465 #define __HAL_RCC_USART2_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
2467 #define __HAL_RCC_USART3_FORCE_RESET()     SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
2468 #define __HAL_RCC_USART3_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
2470 #define __HAL_RCC_UART4_FORCE_RESET()      SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
2471 #define __HAL_RCC_UART4_RELEASE_RESET()    CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
2473 #define __HAL_RCC_UART5_FORCE_RESET()      SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
2474 #define __HAL_RCC_UART5_RELEASE_RESET()    CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
2476 #define __HAL_RCC_I2C1_FORCE_RESET()       SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1_I3C1RST)
2477 #define __HAL_RCC_I2C1_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1_I3C1RST)
2479 #define __HAL_RCC_I2C2_FORCE_RESET()       SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
2480 #define __HAL_RCC_I2C2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
2482 #define __HAL_RCC_I2C3_FORCE_RESET()       SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
2483 #define __HAL_RCC_I2C3_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
2485 #define __HAL_RCC_I3C1_FORCE_RESET()       SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1_I3C1RST)
2486 #define __HAL_RCC_I3C1_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1_I3C1RST)
2488 #define __HAL_RCC_CEC_FORCE_RESET()        SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CECRST)
2489 #define __HAL_RCC_CEC_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CECRST)
2491 #define __HAL_RCC_UART7_FORCE_RESET()      SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART7RST)
2492 #define __HAL_RCC_UART7_RELEASE_RESET()    CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART7RST)
2494 #define __HAL_RCC_UART8_FORCE_RESET()      SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART8RST)
2495 #define __HAL_RCC_UART8_RELEASE_RESET()    CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART8RST)
2497 #define __HAL_RCC_CRS_FORCE_RESET()        SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_CRSRST)
2498 #define __HAL_RCC_CRS_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_CRSRST)
2500 #define __HAL_RCC_MDIOS_FORCE_RESET()      SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_MDIOSRST)
2501 #define __HAL_RCC_MDIOS_RELEASE_RESET()    CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_MDIOSRST)
2503 #define __HAL_RCC_FDCAN_FORCE_RESET()      SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCANRST)
2504 #define __HAL_RCC_FDCAN_RELEASE_RESET()    CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCANRST)
2506 #define __HAL_RCC_UCPD1_FORCE_RESET()      SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
2507 #define __HAL_RCC_UCPD1_RELEASE_RESET()    CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
2518 #define __HAL_RCC_APB2_FORCE_RESET()       WRITE_REG(RCC->APB2RSTR, 0xC8FFC3FFUL)
2519 #define __HAL_RCC_APB2_RELEASE_RESET()     WRITE_REG(RCC->APB2RSTR, 0UL)
2521 #define __HAL_RCC_TIM1_FORCE_RESET()       SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
2522 #define __HAL_RCC_TIM1_RELEASE_RESET()     CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
2524 #define __HAL_RCC_USART1_FORCE_RESET()     SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
2525 #define __HAL_RCC_USART1_RELEASE_RESET()   CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
2527 #define __HAL_RCC_SPI1_FORCE_RESET()       SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
2528 #define __HAL_RCC_SPI1_RELEASE_RESET()     CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
2530 #define __HAL_RCC_SPI4_FORCE_RESET()       SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
2531 #define __HAL_RCC_SPI4_RELEASE_RESET()     CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
2533 #define __HAL_RCC_TIM15_FORCE_RESET()      SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
2534 #define __HAL_RCC_TIM15_RELEASE_RESET()    CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
2536 #define __HAL_RCC_TIM16_FORCE_RESET()      SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
2537 #define __HAL_RCC_TIM16_RELEASE_RESET()    CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
2539 #define __HAL_RCC_TIM17_FORCE_RESET()      SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
2540 #define __HAL_RCC_TIM17_RELEASE_RESET()    CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
2542 #define __HAL_RCC_TIM9_FORCE_RESET()       SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM9RST)
2543 #define __HAL_RCC_TIM9_RELEASE_RESET()     CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM9RST)
2545 #define __HAL_RCC_SPI5_FORCE_RESET()       SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI5RST)
2546 #define __HAL_RCC_SPI5_RELEASE_RESET()     CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI5RST)
2548 #define __HAL_RCC_SAI1_FORCE_RESET()       SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
2549 #define __HAL_RCC_SAI1_RELEASE_RESET()     CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
2551 #define __HAL_RCC_SAI2_FORCE_RESET()       SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
2552 #define __HAL_RCC_SAI2_RELEASE_RESET()     CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
2563 #define __HAL_RCC_APB4_FORCE_RESET()       WRITE_REG(RCC->APB4RSTR, 0x04009E2AUL)
2564 #define __HAL_RCC_APB4_RELEASE_RESET()     WRITE_REG(RCC->APB4RSTR, 0UL)
2566 #define __HAL_RCC_SBS_FORCE_RESET()        SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_SBSRST)
2567 #define __HAL_RCC_SBS_RELEASE_RESET()      CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_SBSRST)
2569 #define __HAL_RCC_LPUART1_FORCE_RESET()    SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPUART1RST)
2570 #define __HAL_RCC_LPUART1_RELEASE_RESET()  CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPUART1RST)
2572 #define __HAL_RCC_SPI6_FORCE_RESET()       SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_SPI6RST)
2573 #define __HAL_RCC_SPI6_RELEASE_RESET()     CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_SPI6RST)
2575 #define __HAL_RCC_LPTIM2_FORCE_RESET()     SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM2RST)
2576 #define __HAL_RCC_LPTIM2_RELEASE_RESET()   CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM2RST)
2578 #define __HAL_RCC_LPTIM3_FORCE_RESET()     SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM3RST)
2579 #define __HAL_RCC_LPTIM3_RELEASE_RESET()   CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM3RST)
2581 #define __HAL_RCC_LPTIM4_FORCE_RESET()     SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM4RST)
2582 #define __HAL_RCC_LPTIM4_RELEASE_RESET()   CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM4RST)
2584 #define __HAL_RCC_LPTIM5_FORCE_RESET()     SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM5RST)
2585 #define __HAL_RCC_LPTIM5_RELEASE_RESET()   CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM5RST)
2587 #define __HAL_RCC_VREF_FORCE_RESET()       SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_VREFRST)
2588 #define __HAL_RCC_VREF_RELEASE_RESET()     CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_VREFRST)
2590 #define __HAL_RCC_DTS_FORCE_RESET()        SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_DTSRST)
2591 #define __HAL_RCC_DTS_RELEASE_RESET()      CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_DTSRST)
2602 #define __HAL_RCC_APB5_FORCE_RESET()       WRITE_REG(RCC->APB5RSTR, 0x00000016UL)
2603 #define __HAL_RCC_APB5_RELEASE_RESET()     WRITE_REG(RCC->APB5RSTR, 0UL)
2605 #define __HAL_RCC_LTDC_FORCE_RESET()       SET_BIT(RCC->APB5RSTR, RCC_APB5RSTR_LTDCRST)
2606 #define __HAL_RCC_LTDC_RELEASE_RESET()     CLEAR_BIT(RCC->APB5RSTR, RCC_APB5RSTR_LTDCRST)
2608 #define __HAL_RCC_DCMIPP_FORCE_RESET()     SET_BIT(RCC->APB5RSTR, RCC_APB5RSTR_DCMIPPRST)
2609 #define __HAL_RCC_DCMIPP_RELEASE_RESET()   CLEAR_BIT(RCC->APB5RSTR, RCC_APB5RSTR_DCMIPPRST)
2611 #define __HAL_RCC_GFXTIM_FORCE_RESET()     SET_BIT(RCC->APB5RSTR, RCC_APB5RSTR_GFXTIMRST)
2612 #define __HAL_RCC_GFXTIM_RELEASE_RESET()   CLEAR_BIT(RCC->APB5RSTR, RCC_APB5RSTR_GFXTIMRST)
2628 #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN)
2630 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADC12LPEN)
2632 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1MACLPEN)
2634 #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1TXLPEN)
2636 #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1RXLPEN)
2639 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGHSLPEN)
2641 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGFSLPEN)
2643 #define __HAL_RCC_USBPHYC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_USBPHYCLPEN)
2645 #define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADF1LPEN)
2648 #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN)
2650 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADC12LPEN)
2653 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1MACLPEN)
2655 #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1TXLPEN)
2657 #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1RXLPEN)
2660 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGHSLPEN)
2662 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGFSLPEN)
2664 #define __HAL_RCC_USBPHYC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_USBPHYCLPEN)
2666 #define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADF1LPEN)
2681 #define __HAL_RCC_PSSI_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PSSILPEN)
2683 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SDMMC2LPEN)
2685 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_CORDICLPEN)
2687 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM1LPEN)
2689 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN)
2692 #define __HAL_RCC_PSSI_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PSSILPEN)
2694 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SDMMC2LPEN)
2696 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_CORDICLPEN)
2698 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM1LPEN)
2700 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN)
2715 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_RNGLPEN)
2717 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_HASHLPEN)
2720 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_CRYPLPEN)
2724 #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_SAESLPEN)
2728 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_PKALPEN)
2732 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_RNGLPEN)
2734 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_HASHLPEN)
2737 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_CRYPLPEN)
2741 #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_SAESLPEN)
2745 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_PKALPEN)
2761 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOALPEN)
2763 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOBLPEN)
2765 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOCLPEN)
2767 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIODLPEN)
2769 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOELPEN)
2771 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOFLPEN)
2773 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOGLPEN)
2775 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOHLPEN)
2777 #define __HAL_RCC_GPIOM_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOMLPEN)
2779 #define __HAL_RCC_GPION_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIONLPEN)
2781 #define __HAL_RCC_GPIOO_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOOLPEN)
2783 #define __HAL_RCC_GPIOP_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOPLPEN)
2785 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_CRCLPEN)
2787 #define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_BKPRAMLPEN)
2790 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOALPEN)
2792 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOBLPEN)
2794 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOCLPEN)
2796 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIODLPEN)
2798 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOELPEN)
2800 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOFLPEN)
2802 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOGLPEN)
2804 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOHLPEN)
2806 #define __HAL_RCC_GPIOM_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOMLPEN)
2808 #define __HAL_RCC_GPION_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIONLPEN)
2810 #define __HAL_RCC_GPIOO_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOOLPEN)
2812 #define __HAL_RCC_GPIOP_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOPLPEN)
2814 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_CRCLPEN)
2816 #define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_BKPRAMLPEN)
2831 #define __HAL_RCC_HPDMA1_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_HPDMA1LPEN)
2833 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DMA2DLPEN)
2835 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FLASHLPEN)
2838 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_JPEGLPEN)
2841 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FMCLPEN)
2843 #define __HAL_RCC_XSPI1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI1LPEN)
2845 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_SDMMC1LPEN)
2847 #define __HAL_RCC_XSPI2_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI2LPEN)
2849 #define __HAL_RCC_XSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPIMLPEN)
2852 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GFXMMULPEN)
2856 #define __HAL_RCC_GPU2D_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GPU2DLPEN)
2859 #define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM1LPEN)
2861 #define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM2LPEN)
2863 #define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_ITCMLPEN)
2865 #define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_AXISRAMLPEN)
2868 #define __HAL_RCC_HPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_HPDMA1LPEN)
2870 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DMA2DLPEN)
2872 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FLASHLPEN)
2875 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_JPEGLPEN)
2878 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FMCLPEN)
2880 #define __HAL_RCC_XSPI1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI1LPEN)
2882 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_SDMMC1LPEN)
2884 #define __HAL_RCC_XSPI2_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI2LPEN)
2886 #define __HAL_RCC_XSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPIMLPEN)
2889 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GFXMMULPEN)
2893 #define __HAL_RCC_GPU2D_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GPU2DLPEN)
2896 #define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM1LPEN)
2898 #define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM2LPEN)
2900 #define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_ITCMLPEN)
2902 #define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_AXISRAMLPEN)
2917 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM2LPEN)
2919 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM3LPEN)
2921 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM4LPEN)
2923 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM5LPEN)
2925 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM6LPEN)
2927 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM7LPEN)
2929 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM12LPEN)
2931 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM13LPEN)
2933 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM14LPEN)
2935 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_LPTIM1LPEN)
2937 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_WWDGLPEN)
2939 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI2LPEN)
2941 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI3LPEN)
2943 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPDIFRXLPEN)
2945 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART2LPEN)
2947 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART3LPEN)
2949 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART4LPEN)
2951 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART5LPEN)
2953 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1LPEN)
2955 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C2LPEN)
2957 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C3LPEN)
2959 #define __HAL_RCC_I3C1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1LPEN)
2961 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_CECLPEN)
2963 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART7LPEN)
2965 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART8LPEN)
2967 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_CRSLPEN)
2969 #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_MDIOSLPEN)
2971 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_FDCANLPEN)
2973 #define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_UCPD1LPEN)
2976 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM2LPEN)
2978 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM3LPEN)
2980 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM4LPEN)
2982 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM5LPEN)
2984 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM6LPEN)
2986 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM7LPEN)
2988 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM12LPEN)
2990 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM13LPEN)
2992 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM14LPEN)
2994 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_LPTIM1LPEN)
2996 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_WWDGLPEN)
2998 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI2LPEN)
3000 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI3LPEN)
3002 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPDIFRXLPEN)
3004 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART2LPEN)
3006 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART3LPEN)
3008 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART4LPEN)
3010 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART5LPEN)
3012 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1LPE…
3014 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C2LPEN)
3016 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C3LPEN)
3018 #define __HAL_RCC_I3C1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1LPE…
3020 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_CECLPEN)
3022 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART7LPEN)
3024 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART8LPEN)
3026 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_CRSLPEN)
3028 #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_MDIOSLPEN)
3030 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_FDCANLPEN)
3032 #define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_UCPD1LPEN)
3047 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN)
3049 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN)
3051 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN)
3053 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN)
3055 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN)
3057 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN)
3059 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN)
3061 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM9LPEN)
3063 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI5LPEN)
3065 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN)
3067 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN)
3070 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN)
3072 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN)
3074 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN)
3076 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN)
3078 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN)
3080 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN)
3082 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN)
3084 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM9LPEN)
3086 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI5LPEN)
3088 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN)
3090 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN)
3105 #define __HAL_RCC_SBS_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SBSLPEN)
3107 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPUART1LPEN)
3109 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SPI6LPEN)
3111 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM2LPEN)
3113 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM3LPEN)
3115 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM4LPEN)
3117 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM5LPEN)
3119 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_VREFLPEN)
3121 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_RTCAPBLPEN)
3123 #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_DTSLPEN)
3126 #define __HAL_RCC_SBS_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SBSLPEN)
3128 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPUART1LPEN)
3130 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SPI6LPEN)
3132 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM2LPEN)
3134 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM3LPEN)
3136 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM4LPEN)
3138 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM5LPEN)
3140 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_VREFLPEN)
3142 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_RTCAPBLPEN)
3144 #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_DTSLPEN)
3159 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB5LPENR, RCC_APB5LPENR_LTDCLPEN)
3161 #define __HAL_RCC_DCMIPP_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB5LPENR, RCC_APB5LPENR_DCMIPPLPEN)
3163 #define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB5LPENR, RCC_APB5LPENR_GFXTIMLPEN)
3166 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB5LPENR, RCC_APB5LPENR_LTDCLPEN)
3168 #define __HAL_RCC_DCMIPP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB5LPENR, RCC_APB5LPENR_DCMIPPLPEN)
3170 #define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB5LPENR, RCC_APB5LPENR_GFXTIMLPEN)
3185 #define __HAL_RCC_GPDMA1_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN…
3187 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADC12LPEN)…
3189 #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1MACLPE…
3191 #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1TXLPEN…
3193 #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1RXLPEN…
3196 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGHSLP…
3198 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGFSLP…
3200 #define __HAL_RCC_USBPHYC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_USBPHYCLPE…
3202 #define __HAL_RCC_ADF1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADF1LPEN) …
3216 #define __HAL_RCC_PSSI_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PSSILPEN) …
3218 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SDMMC2LPEN…
3220 #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_CORDICLPEN…
3222 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM1LPEN)…
3224 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN)…
3239 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_RNGLPEN) !…
3241 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_HASHLPEN) …
3244 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_CRYPLPEN) …
3248 #define __HAL_RCC_SAES_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_SAESLPEN) …
3252 #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_PKALPEN) !…
3268 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOALPEN)…
3270 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOBLPEN)…
3272 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOCLPEN)…
3274 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIODLPEN)…
3276 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOELPEN)…
3278 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOFLPEN)…
3280 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOGLPEN)…
3282 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOHLPEN)…
3284 #define __HAL_RCC_GPIOM_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOMLPEN)…
3286 #define __HAL_RCC_GPION_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIONLPEN)…
3288 #define __HAL_RCC_GPIOO_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOOLPEN)…
3290 #define __HAL_RCC_GPIOP_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOPLPEN)…
3292 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_CRCLPEN) !…
3294 #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_BKPRAMLPEN…
3309 #define __HAL_RCC_HPDMA1_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_HPDMA1LPEN…
3311 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DMA2DLPEN)…
3313 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FLASHLPEN)…
3316 #define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_JPEGLPEN) …
3319 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FMCLPEN) !…
3321 #define __HAL_RCC_XSPI1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI1LPEN)…
3323 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_SDMMC1LPEN…
3325 #define __HAL_RCC_XSPI2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI2LPEN)…
3327 #define __HAL_RCC_XSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPIMLPEN) !…
3330 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GFXMMULPEN…
3334 #define __HAL_RCC_GPU2D_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GPU2DLPEN)…
3337 #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM1LPEN)…
3339 #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM2LPEN)…
3341 #define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_ITCMLPEN) …
3343 #define __HAL_RCC_AXISRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_AXISRAMLPE…
3358 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM2LPEN)…
3360 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM3LPEN)…
3362 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM4LPEN)…
3364 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM5LPEN)…
3366 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM6LPEN)…
3368 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM7LPEN)…
3370 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM12LPEN…
3372 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM13LPEN…
3374 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM14LPEN…
3376 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_LPTIM1LPE…
3378 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_WWDGLPEN)…
3380 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI2LPEN)…
3382 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI3LPEN)…
3384 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPDIFRXL…
3386 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART2LPE…
3388 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART3LPE…
3390 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART4LPEN…
3392 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART5LPEN…
3394 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1…
3396 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C2LPEN)…
3398 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C3LPEN)…
3400 #define __HAL_RCC_I3C1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1…
3402 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_CECLPEN) …
3404 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART7LPEN…
3406 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART8LPEN…
3408 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_CRSLPEN) …
3410 #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_MDIOSLPEN…
3412 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_FDCANLPEN…
3414 #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_UCPD1LPEN…
3429 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN) …
3431 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN…
3433 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN) …
3435 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN) …
3437 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN)…
3439 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN)…
3441 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN)…
3443 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM9LPEN) …
3445 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI5LPEN) …
3447 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN) …
3449 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) …
3464 #define __HAL_RCC_SBS_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SBSLPEN) !…
3466 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPUART1LPE…
3468 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SPI6LPEN) …
3470 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM2LPEN…
3472 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM3LPEN…
3474 #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM4LPEN…
3476 #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM5LPEN…
3478 #define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_VREFLPEN) …
3480 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_RTCAPBL…
3482 #define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_DTSLPEN) !…
3497 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->APB5LPENR, RCC_APB5LPENR_LTDCLPEN) …
3499 #define __HAL_RCC_DCMIPP_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB5LPENR, RCC_APB5LPENR_DCMIPPLPEN…
3501 #define __HAL_RCC_GFXTIM_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->APB5LPENR, RCC_APB5LPENR_GFXTIMLPEN…
3531   MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))
3541 #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
3558 #define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
3560 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
3571 …MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_HSICFGR_H…
3582 #define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)
3584 #define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
3602 #define __HAL_RCC_CSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_CSION)
3604 #define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)
3615 …MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICALIBRATIONVALUE__) << RCC_CSICFGR_C…
3626 #define __HAL_RCC_CSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_CSIKERON)
3628 #define __HAL_RCC_CSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)
3637 #define __HAL_RCC_HSI48_ENABLE()    SET_BIT(RCC->CR, RCC_CR_HSI48ON);
3639 #define __HAL_RCC_HSI48_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
3649 #define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)
3651 #define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
3677       SET_BIT(RCC->CR, RCC_CR_HSEON);                \
3681       CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \
3682       CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
3683       CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \
3687       SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \
3688       CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
3689       SET_BIT(RCC->CR, RCC_CR_HSEON);                \
3693       SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \
3694       SET_BIT(RCC->CR, RCC_CR_HSEEXT);               \
3695       SET_BIT(RCC->CR, RCC_CR_HSEON);                \
3699       CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \
3700       CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \
3701       CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
3731       SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
3735       CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \
3736       CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
3737       CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \
3741       SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \
3742       CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
3743       SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
3747       SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \
3748       SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);           \
3749       SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
3753       CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \
3754       CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \
3755       CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
3770 #define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
3772 #define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
3797    MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTC_CLKSOURCE__) & (~RCC_BDCR_RTCSEL)) >> 4U)) : \
3798    CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE))
3803     SET_BIT(RCC->BDCR, ((__RTC_CLKSOURCE__) & RCC_BDCR_RTCSEL)); \
3807   ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
3808 …((READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) << 4U) | RCC_BDCR_RTCSEL) : READ_BIT(RCC->BDCR, RCC_BDCR_RT…
3815 #define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST)
3817 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST)
3837   MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
3848   READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC)
3857 #define __HAL_RCC_PLL1_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL1ON)
3859 #define __HAL_RCC_PLL1_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
3873 #define __HAL_RCC_PLL1CLKOUT_ENABLE(__PLL_CLOCKOUT__)   SET_BIT(RCC->PLLCFGR, (__PLL_CLOCKOUT__))
3875 #define __HAL_RCC_PLL1CLKOUT_DISABLE(__PLL_CLOCKOUT__)  CLEAR_BIT(RCC->PLLCFGR, (__PLL_CLOCKOUT__))
3887 #define __HAL_RCC_GET_PLL1CLKOUT_CONFIG(__PLL_CLOCKOUT__)   READ_BIT(RCC->PLLCFGR, (__PLL_CLOCKOUT_…
3894 #define __HAL_RCC_PLL1_FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
3896 #define __HAL_RCC_PLL1_FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
3944 …MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__PLLSOURCE__) | ( (__…
3945     WRITE_REG(RCC->PLL1DIVR1, ((((__PLL1N__) - 1U) & RCC_PLL1DIVR1_DIVN) | \
3949     MODIFY_REG(RCC->PLL1DIVR2, RCC_PLL1DIVR2_DIVS, \
3968 …MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN, (uint32_t)(__PLL1FRACN__) << RCC_PLL1FRACR_FRACN_P…
3981   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__PLL_VCOINPUT_RANGE__))
3991   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__PLLVCORANGE__))
3999 #define __HAL_RCC_PLL2_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL2ON)
4000 #define __HAL_RCC_PLL2_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
4013 #define __HAL_RCC_PLL2CLKOUT_ENABLE(__PLL_CLOCKOUT__)   SET_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOUT__) <…
4015 #define __HAL_RCC_PLL2CLKOUT_DISABLE(__PLL_CLOCKOUT__)  CLEAR_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOUT__)…
4028 #define __HAL_RCC_GET_PLL2CLKOUT_CONFIG(__PLL_CLOCKOUT__)   (READ_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOU…
4036 #define __HAL_RCC_PLL2_FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
4038 #define __HAL_RCC_PLL2_FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
4083     MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_DIVM2 | RCC_PLLCKSELR_PLLSRC), \
4085     WRITE_REG(RCC->PLL2DIVR1,  ((((__PLL2N__) - 1U) & RCC_PLL2DIVR1_DIVN) | \
4089     MODIFY_REG(RCC->PLL2DIVR2, (RCC_PLL2DIVR2_DIVS | RCC_PLL2DIVR2_DIVT) , \
4111 …MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN,((uint32_t)(__PLL2FRACN__) << RCC_PLL2FRACR_FRACN_P…
4123 …MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, ((__PLL_VCOINPUT_RANGE__) << (RCC_PLLCFGR_PLL2RGE_Po…
4137 …MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, ((__PLLVCORANGE__) << (RCC_PLLCFGR_PLL2VCOSEL_Pos…
4145 #define __HAL_RCC_PLL3_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL3ON)
4146 #define __HAL_RCC_PLL3_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
4153 #define __HAL_RCC_PLL3_FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
4155 #define __HAL_RCC_PLL3_FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
4167 #define __HAL_RCC_PLL3CLKOUT_ENABLE(__PLL_CLOCKOUT__)   SET_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOUT__) <…
4169 #define __HAL_RCC_PLL3CLKOUT_DISABLE(__PLL_CLOCKOUT__)  CLEAR_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOUT__)…
4181 #define __HAL_RCC_GET_PLL3CLKOUT_CONFIG(__PLL_CLOCKOUT__)   (READ_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOU…
4223     MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_DIVM3 | RCC_PLLCKSELR_PLLSRC), \
4225     WRITE_REG(RCC->PLL3DIVR1,  ((((__PLL3N__) - 1U) & RCC_PLL3DIVR1_DIVN) | \
4229     MODIFY_REG(RCC->PLL3DIVR2, RCC_PLL3DIVR2_DIVS, \
4249 #define  __HAL_RCC_PLL3_FRACN_CONFIG(__PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN,…
4261 …MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, ((__PLL_VCOINPUT_RANGE__) << (RCC_PLLCFGR_PLL3RGE_Po…
4274 …MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, ((__PLLVCORANGE__) << (RCC_PLLCFGR_PLL3VCOSEL_Pos…
4295   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
4306   READ_BIT(RCC->CFGR, RCC_CFGR_SWS)
4332   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));
4350   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
4361   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__STOPKERWUCLK__))
4383   MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
4399 …MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7…
4423 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
4439 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
4456 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__))
4474 #define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__))
4480 #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->RSR, RCC_RSR_RMVF)
4505 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == RCC_CR_REG_INDEX)        ? RCC->CR …
4506 …                     ((((__FLAG__) >> 5U) == RCC_BDCR_REG_INDEX)     ? RCC->BDCR :                \
4507 …                      ((((__FLAG__) >> 5U) == RCC_CSR_REG_INDEX)     ? RCC->CSR :                 \
4508 …                       ((((__FLAG__) >> 5U) == RCC_RSR_REG_INDEX)    ? RCC->RSR : RCC->CIFR)))) & \