Lines Matching refs:RCC
734 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
736 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
742 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \
744 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \
751 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
753 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
761 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
763 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
770 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
772 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
778 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \
780 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \
786 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN); \
788 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN); \
795 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN);\
797 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN);\
803 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN);\
805 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN);\
811 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN);\
813 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN);\
820 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN); \
822 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN); \
828 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN); \
830 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN); \
837 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \
839 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \
846 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \
848 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \
852 #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN)
854 #define __HAL_RCC_GPDMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN)
857 #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN)
861 #define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN)
864 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN)
866 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
868 #define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN)
871 #define __HAL_RCC_ETH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN)
873 #define __HAL_RCC_ETHTX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN)
875 #define __HAL_RCC_ETHRX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN)
879 #define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN)
881 #define __HAL_RCC_BKPRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN)
884 #define __HAL_RCC_DCACHE1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN)
887 #define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN)
902 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
904 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
910 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
912 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
918 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
920 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
926 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
928 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
935 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
937 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
945 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
947 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
955 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
957 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
964 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
966 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
973 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
975 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
982 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
984 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
990 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
992 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
999 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
1001 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
1011 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
1013 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
1021 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
1023 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
1030 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
1032 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
1039 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \
1041 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \
1049 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \
1051 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \
1058 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \
1060 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \
1066 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN); \
1068 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN); \
1073 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
1075 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
1077 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
1079 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
1082 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
1086 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
1090 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
1093 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
1096 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN)
1099 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
1101 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN)
1104 #define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN)
1109 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
1113 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN)
1116 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
1119 #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN)
1123 #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN)
1127 #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN)
1130 #define __HAL_RCC_SRAM3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN)
1147 … SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN); \
1149 … tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN); \
1157 … SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN); \
1159 … tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN); \
1167 … SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN); \
1169 … tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN); \
1177 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN); \
1179 … tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN); \
1187 … SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN); \
1189 … tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN); \
1195 #define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN)
1199 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN)
1203 #define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN)
1207 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN)
1211 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN)
1229 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN); \
1231 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN); \
1237 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN); \
1239 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN); \
1246 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN); \
1248 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN); \
1256 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN); \
1258 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN); \
1265 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN); \
1267 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN); \
1273 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN); \
1275 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN); \
1282 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN); \
1284 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN); \
1293 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN); \
1295 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN); \
1303 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN); \
1305 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN); \
1312 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN); \
1314 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN); \
1321 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN); \
1323 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN); \
1330 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN); \
1332 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN); \
1338 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN); \
1340 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN); \
1347 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN); \
1349 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN); \
1356 … SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN); \
1358 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN); \
1364 … SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN); \
1366 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN); \
1373 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN); \
1375 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN); \
1383 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN); \
1385 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN); \
1392 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN); \
1394 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN); \
1400 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN); \
1402 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN); \
1408 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN); \
1410 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN); \
1416 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN); \
1418 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN); \
1425 … SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN); \
1427 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN); \
1435 … SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN); \
1437 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN); \
1445 … SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN); \
1447 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN); \
1455 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN); \
1457 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN); \
1465 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN); \
1467 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN); \
1475 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN); \
1477 … tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN); \
1485 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN); \
1487 … tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN); \
1495 … SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN); \
1497 … tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN); \
1504 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN); \
1506 … tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN); \
1512 … SET_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN); \
1514 … tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN); \
1520 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN); \
1522 … tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN); \
1529 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN); \
1531 … tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN); \
1536 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN)
1538 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN)
1541 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN)
1545 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN)
1548 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN)
1550 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN)
1553 #define __HAL_RCC_TIM12_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN)
1557 #define __HAL_RCC_TIM13_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN)
1561 #define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN)
1564 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN)
1567 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN)
1570 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN)
1572 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN)
1575 #define __HAL_RCC_COMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN)
1578 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN)
1580 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN)
1583 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN)
1587 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN)
1590 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN)
1592 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN)
1594 #define __HAL_RCC_I3C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN)
1596 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN)
1599 #define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN)
1603 #define __HAL_RCC_USART10_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN)
1607 #define __HAL_RCC_USART11_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN)
1611 #define __HAL_RCC_CEC_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN)
1615 #define __HAL_RCC_UART7_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN)
1619 #define __HAL_RCC_UART8_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN)
1624 #define __HAL_RCC_UART9_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN)
1628 #define __HAL_RCC_UART12_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN)
1631 #define __HAL_RCC_DTS_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR , RCC_APB1HENR_DTSEN)
1633 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN)
1635 #define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN)
1638 #define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN)
1654 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
1656 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
1662 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
1664 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
1671 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
1673 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
1680 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
1682 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
1689 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
1691 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
1699 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
1701 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
1709 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
1711 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
1719 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \
1721 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \
1729 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN); \
1731 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN); \
1739 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
1741 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
1749 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
1751 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
1759 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \
1761 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \
1767 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
1769 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
1772 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
1775 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
1778 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
1782 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
1786 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
1790 #define __HAL_RCC_SPI4_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN)
1794 #define __HAL_RCC_SPI6_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN)
1798 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
1802 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
1806 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN)
1821 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN); \
1823 … tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN); \
1830 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN); \
1832 … tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN); \
1839 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \
1841 … tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \
1848 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \
1850 … tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \
1858 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN); \
1860 … tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN); \
1868 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN); \
1870 … tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN); \
1877 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \
1879 … tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \
1886 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \
1888 … tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \
1896 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \
1898 … tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \
1906 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN); \
1908 … tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN); \
1916 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN); \
1918 … tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN); \
1926 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \
1928 … tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \
1935 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \
1937 … tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \
1941 #define __HAL_RCC_SBS_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN)
1944 #define __HAL_RCC_SPI5_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN)
1947 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN)
1950 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN)
1954 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN)
1958 #define __HAL_RCC_I3C2_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN)
1961 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN)
1964 #define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN)
1968 #define __HAL_RCC_LPTIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN)
1972 #define __HAL_RCC_LPTIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN)
1976 #define __HAL_RCC_LPTIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN)
1980 #define __HAL_RCC_VREF_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN)
1983 #define __HAL_RCC_RTC_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN)
2000 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \
2002 … tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \
2008 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS); \
2010 … tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS); \
2017 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS); \
2019 … tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS); \
2026 SET_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \
2028 … tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \
2034 SET_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \
2036 … tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \
2042 SET_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS); \
2044 … tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS); \
2049 #define __HAL_RCC_AHB1_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS)
2051 #define __HAL_RCC_AHB2_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS)
2054 #define __HAL_RCC_AHB4_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS)
2057 #define __HAL_RCC_APB1_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS)
2059 #define __HAL_RCC_APB2_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS)
2061 #define __HAL_RCC_APB3_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS)
2074 #define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U)
2076 #define __HAL_RCC_GPDMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN) != 0U)
2078 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN) != 0U)
2080 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)
2083 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U)
2087 #define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U)
2090 #define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U)
2093 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN) != 0U)
2095 #define __HAL_RCC_ETHTX_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) != 0U)
2097 #define __HAL_RCC_ETHRX_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) != 0U)
2100 #define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) != 0U)
2102 #define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN) != 0U)
2105 #define __HAL_RCC_DCACHE1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) != 0…
2108 #define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U)
2111 #define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U)
2113 #define __HAL_RCC_GPDMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN) == 0U)
2115 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN) == 0U)
2117 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)
2120 #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U)
2124 #define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U)
2127 #define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U)
2130 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN) == 0U)
2132 #define __HAL_RCC_ETHTX_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) == 0U)
2134 #define __HAL_RCC_ETHRX_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) == 0U)
2137 #define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) == 0U)
2139 #define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN) == 0U)
2142 #define __HAL_RCC_DCACHE1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) == 0…
2145 #define __HAL_RCC_SRAM1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) == 0U)
2158 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)
2160 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)
2162 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)
2164 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)
2167 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)
2171 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)
2175 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)
2178 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U)
2181 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U)
2184 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U)
2186 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U)
2189 #define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN) !=…
2194 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)
2198 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U)
2201 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)
2203 #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) != 0U)
2206 #define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) != 0U)
2209 #define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) != 0U)
2212 #define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN) != 0U)
2215 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)
2217 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)
2219 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)
2221 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)
2224 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)
2228 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)
2232 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)
2235 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U)
2238 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U)
2241 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U)
2243 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U)
2246 #define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN) ==…
2251 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)
2255 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U)
2258 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)
2260 #define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) == 0U)
2263 #define __HAL_RCC_SAES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) == 0U)
2266 #define __HAL_RCC_SRAM2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) == 0U)
2269 #define __HAL_RCC_SRAM3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN) == 0U)
2284 #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) !=…
2288 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) != …
2292 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN) != …
2296 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) != 0U)
2300 #define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) !…
2304 #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) ==…
2308 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) == …
2312 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN) == …
2316 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) == 0U)
2320 #define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) =…
2337 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN) != 0U)
2339 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN) != 0U)
2342 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN) != 0U)
2346 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN) != 0U)
2349 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN) != 0U)
2351 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN) != 0U)
2354 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN) != 0U)
2358 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN) != 0U)
2362 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN) != 0U)
2365 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN) != 0U)
2368 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN) != 0U)
2371 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN) != 0U)
2373 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN) != 0U)
2376 #define __HAL_RCC_COMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN) != 0U)
2379 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN) != 0…
2381 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN) != 0…
2384 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN) != 0U)
2388 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN) != 0U)
2391 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN) != 0U)
2393 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN) != 0U)
2395 #define __HAL_RCC_I3C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN) != 0U)
2397 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN) != 0U)
2400 #define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN) != 0…
2404 #define __HAL_RCC_USART10_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN) != …
2408 #define __HAL_RCC_USART11_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN) != …
2412 #define __HAL_RCC_CEC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN) != 0U)
2416 #define __HAL_RCC_UART7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN) != 0U)
2420 #define __HAL_RCC_UART8_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN) != 0U)
2425 #define __HAL_RCC_UART9_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN) != 0U)
2429 #define __HAL_RCC_UART12_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN) != 0…
2432 #define __HAL_RCC_DTS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN) != 0U)
2434 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN) != 0…
2436 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN) != 0U)
2439 #define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN) != 0U)
2443 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN) == 0U)
2445 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN) == 0U)
2448 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN) == 0U)
2452 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN) == 0U)
2455 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN) == 0U)
2457 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN) == 0U)
2460 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN) == 0…
2464 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN) == 0…
2468 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN) == 0…
2471 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN) == 0U)
2474 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN) == 0…
2477 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN) == 0U)
2479 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN) == 0U)
2482 #define __HAL_RCC_COMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN) == 0U)
2485 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN) == …
2487 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN) == …
2490 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN) == 0…
2494 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN) == 0…
2497 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN) == 0U)
2499 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN) == 0U)
2501 #define __HAL_RCC_I3C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN) == 0U)
2503 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN) == 0U)
2506 #define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN) == …
2510 #define __HAL_RCC_USART10_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN) ==…
2514 #define __HAL_RCC_USART11_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN) ==…
2518 #define __HAL_RCC_CEC_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN) == 0U)
2522 #define __HAL_RCC_UART7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN) == 0…
2526 #define __HAL_RCC_UART8_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN) == 0…
2531 #define __HAL_RCC_UART9_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN) == 0…
2535 #define __HAL_RCC_UART12_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN) == …
2538 #define __HAL_RCC_DTS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN) == 0U)
2540 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN) == …
2542 #define __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN) == 0…
2545 #define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN) == 0…
2559 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)
2561 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
2564 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)
2567 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
2570 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)
2574 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)
2578 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)
2582 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U)
2586 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN) != 0U)
2590 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)
2594 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U)
2598 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U)
2601 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)
2603 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)
2606 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)
2609 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)
2612 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)
2616 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)
2620 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)
2624 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U)
2628 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN) == 0U)
2632 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)
2636 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U)
2640 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) == 0U)
2654 #define __HAL_RCC_SBS_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) != 0U)
2657 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN) != 0U)
2660 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) !=…
2663 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) != 0U)
2667 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN) != 0U)
2671 #define __HAL_RCC_I3C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN) != 0U)
2674 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) != …
2677 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) != …
2681 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) != …
2685 #define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN) != …
2689 #define __HAL_RCC_LPTIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN) != …
2693 #define __HAL_RCC_VREF_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) != 0U)
2696 #define __HAL_RCC_RTC_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) != …
2698 #define __HAL_RCC_SBS_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) == 0U)
2701 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN) == 0U)
2704 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) ==…
2707 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) == 0U)
2711 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN) == 0U)
2715 #define __HAL_RCC_I3C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN) == 0U)
2718 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) == …
2721 #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) == …
2725 #define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) == …
2729 #define __HAL_RCC_LPTIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN) == …
2733 #define __HAL_RCC_LPTIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN) == …
2737 #define __HAL_RCC_VREF_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) == 0U)
2740 #define __HAL_RCC_RTC_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) == …
2755 #define __HAL_RCC_AHB1_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS) != 0U)
2757 #define __HAL_RCC_AHB2_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS) != 0U)
2760 #define __HAL_RCC_AHB4_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS) != 0U)
2763 #define __HAL_RCC_APB1_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS) != 0U)
2765 #define __HAL_RCC_APB2_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS) != 0U)
2767 #define __HAL_RCC_APB3_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS) != 0U)
2778 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x010AD003U)
2780 #define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST)
2782 #define __HAL_RCC_GPDMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA2RST)
2785 #define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
2789 #define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
2792 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
2794 #define __HAL_RCC_RAMCFG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST)
2797 #define __HAL_RCC_ETH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETHRST)
2800 #define __HAL_RCC_GTZC1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TZSC1RST)
2803 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
2805 #define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST)
2807 #define __HAL_RCC_GPDMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA2RST)
2810 #define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
2814 #define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
2817 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
2819 #define __HAL_RCC_RAMCFG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST)
2822 #define __HAL_RCC_ETH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETHRST)
2825 #define __HAL_RCC_GTZC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TZSC1RST)
2836 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x001F1DFFU)
2838 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
2840 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
2842 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
2844 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
2847 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
2851 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
2855 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
2858 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
2861 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
2864 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
2866 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
2869 #define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMI_PSSIRST)
2874 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
2878 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
2881 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
2884 #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST)
2888 #define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST)
2891 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
2893 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
2895 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
2897 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
2899 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
2902 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
2906 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
2910 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
2913 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
2916 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
2919 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
2921 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
2924 #define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMI_PSSIRST)
2929 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
2933 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
2936 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
2939 #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST)
2943 #define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST)
2956 #define __HAL_RCC_AHB4_FORCE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x00111880U)
2960 #define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC1RST)
2964 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC1RST)
2968 #define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC2RST)
2972 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_FMCRST)
2976 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI1RST)
2980 #define __HAL_RCC_AHB4_RELEASE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x00000000U)
2984 #define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC1RST)
2988 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC1RST)
2992 #define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC2RST)
2996 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_FMCRST)
3000 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI1RST)
3014 WRITE_REG(RCC->APB1LRSTR, 0xDFFEC1FFU); \
3015 WRITE_REG(RCC->APB1HRSTR, 0x4080062BU); \
3018 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM2RST)
3020 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM3RST)
3023 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM4RST)
3027 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM5RST)
3030 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM6RST)
3032 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM7RST)
3035 #define __HAL_RCC_TIM12_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM12RST)
3039 #define __HAL_RCC_TIM13_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM13RST)
3043 #define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM14RST)
3047 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_OPAMPRST)
3050 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI2RST)
3052 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI3RST)
3055 #define __HAL_RCC_COMP_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_COMPRST)
3058 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART2RST)
3060 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART3RST)
3063 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART4RST)
3067 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART5RST)
3070 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C1RST)
3072 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C2RST)
3074 #define __HAL_RCC_I3C1_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I3C1RST)
3076 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CRSRST)
3079 #define __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART6RST)
3083 #define __HAL_RCC_USART10_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART10RST)
3087 #define __HAL_RCC_USART11_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART11RST)
3091 #define __HAL_RCC_CEC_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CECRST)
3095 #define __HAL_RCC_UART7_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART7RST)
3099 #define __HAL_RCC_UART8_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART8RST)
3104 #define __HAL_RCC_UART9_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART9RST)
3108 #define __HAL_RCC_UART12_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART12RST)
3111 #define __HAL_RCC_DTS_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_DTSRST)
3113 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_LPTIM2RST)
3115 #define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_FDCANRST)
3118 #define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UCPD1RST)
3123 WRITE_REG(RCC->APB1LRSTR, 0x00000000U); \
3124 WRITE_REG(RCC->APB1HRSTR, 0x00000000U); \
3127 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM2RST)
3129 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM3RST)
3132 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM4RST)
3136 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM5RST)
3139 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM6RST)
3141 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM7RST)
3144 #define __HAL_RCC_TIM12_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM12RST)
3148 #define __HAL_RCC_TIM13_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM13RST)
3152 #define __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM14RST)
3156 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_OPAMPRST)
3159 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI2RST)
3161 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI3RST)
3164 #define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_COMPRST)
3167 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART2RST)
3169 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART3RST)
3172 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART4RST)
3176 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART5RST)
3179 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C1RST)
3181 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C2RST)
3183 #define __HAL_RCC_I3C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I3C1RST)
3185 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CRSRST)
3188 #define __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART6RST)
3192 #define __HAL_RCC_USART10_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART10RST)
3196 #define __HAL_RCC_USART11_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART11RST)
3200 #define __HAL_RCC_CEC_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CECRST)
3204 #define __HAL_RCC_UART7_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART7RST)
3208 #define __HAL_RCC_UART8_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART8RST)
3213 #define __HAL_RCC_UART9_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART9RST)
3217 #define __HAL_RCC_UART12_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART12RST)
3220 #define __HAL_RCC_DTS_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_DTSRST)
3222 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_LPTIM2RST)
3224 #define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_FDCANRST)
3227 #define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UCPD1RST)
3239 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0x017F7800U)
3241 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
3243 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
3246 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
3249 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
3252 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
3256 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
3260 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
3264 #define __HAL_RCC_SPI4_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
3268 #define __HAL_RCC_SPI6_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI6RST)
3272 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
3276 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
3280 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST)
3283 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
3285 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
3287 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
3290 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
3293 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
3296 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
3300 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
3304 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
3308 #define __HAL_RCC_SPI4_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
3312 #define __HAL_RCC_SPI6_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI6RST)
3316 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
3320 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
3324 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST)
3336 #define __HAL_RCC_APB3_FORCE_RESET() WRITE_REG(RCC->APB3RSTR, 0x001008E0U)
3339 #define __HAL_RCC_SPI5_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI5RST)
3342 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST)
3345 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST)
3349 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C4RST)
3353 #define __HAL_RCC_I3C2_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I3C2RST)
3356 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST)
3359 #define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST)
3363 #define __HAL_RCC_LPTIM4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST)
3367 #define __HAL_RCC_LPTIM5_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM5RST)
3371 #define __HAL_RCC_LPTIM6_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM6RST)
3375 #define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST)
3378 #define __HAL_RCC_APB3_RELEASE_RESET() WRITE_REG(RCC->APB3RSTR, 0x00000000U)
3381 #define __HAL_RCC_SPI5_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI5RST)
3384 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST)
3387 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST)
3391 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C4RST)
3395 #define __HAL_RCC_I3C2_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I3C2RST)
3398 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST)
3401 #define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST)
3405 #define __HAL_RCC_LPTIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST)
3409 #define __HAL_RCC_LPTIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM5RST)
3413 #define __HAL_RCC_LPTIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM6RST)
3417 #define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST)
3431 #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPE…
3433 #define __HAL_RCC_GPDMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA2LPE…
3435 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FLITFLPEN)
3437 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CRCLPEN)
3440 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CORDICLPE…
3444 #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FMACLPEN)
3447 #define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_RAMCFGLPE…
3450 #define __HAL_RCC_ETH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHLPEN)
3452 #define __HAL_RCC_ETHTX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHTXLPEN)
3454 #define __HAL_RCC_ETHRX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHRXLPEN)
3457 #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_TZSC1LPEN)
3459 #define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_BKPRAMLPE…
3461 #define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ICACHELPE…
3464 #define __HAL_RCC_DCACHE1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_DCACHE1LP…
3467 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_SRAM1LPEN)
3470 #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1L…
3472 #define __HAL_RCC_GPDMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA2L…
3474 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FLITFLP…
3476 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CRCLPEN)
3479 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CORDICL…
3483 #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FMACLPE…
3486 #define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_RAMCFGL…
3489 #define __HAL_RCC_ETH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHLPEN)
3491 #define __HAL_RCC_ETHTX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHTXLP…
3493 #define __HAL_RCC_ETHRX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHRXLP…
3496 #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_TZSC1LP…
3498 #define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_BKPRAML…
3500 #define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ICACHEL…
3503 #define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_DCACHE1…
3506 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_SRAM1LP…
3519 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOALPEN)
3521 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOBLPEN)
3523 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOCLPEN)
3525 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIODLPEN)
3528 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOELPEN)
3532 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOFLPEN)
3536 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOGLPEN)
3539 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOHLPEN)
3542 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOILPEN)
3545 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_ADCLPEN)
3547 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DAC1LPEN)
3550 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DCMI_PSSI…
3555 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_AESLPEN);
3559 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_HASHLPEN)
3562 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_RNGLPEN)
3565 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PKALPEN)
3569 #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SAESLPEN)
3572 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN)
3575 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM3LPEN)
3578 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOALP…
3580 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOBLP…
3582 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOCLP…
3584 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIODLP…
3587 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOELP…
3591 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOFLP…
3595 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOGLP…
3598 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOHLP…
3601 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOILP…
3604 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_ADCLPEN)
3606 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DAC1LPE…
3609 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DCMI_PS…
3614 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_AESLPEN…
3618 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_HASHLPE…
3621 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_RNGLPEN)
3624 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PKALPEN)
3627 #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SAESLPE…
3629 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LP…
3632 #define __HAL_RCC_SRAM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM3LP…
3646 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC1LP…
3650 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC1LPE…
3654 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC2LPE…
3658 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_FMCLPEN)
3662 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI1L…
3666 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC1…
3670 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC1L…
3674 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC2L…
3678 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_FMCLPEN)
3682 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI…
3696 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM2LPEN)
3698 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM3LPEN)
3701 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM4LPEN)
3705 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM5LPEN)
3708 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM6LPEN)
3710 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM7LPEN)
3713 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM12LPEN)
3717 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM13LPEN)
3721 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM14LPEN)
3724 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_WWDGLPEN)
3727 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_OPAMPLPEN)
3730 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI2LPEN)
3732 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI3LPEN)
3735 #define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_COMPLPEN)
3738 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART2LPEN)
3740 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART3LPEN)
3743 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART4LPEN)
3747 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART5LPEN)
3750 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C1LPEN)
3752 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C2LPEN)
3754 #define __HAL_RCC_I3C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I3C1LPEN)
3756 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CRSLPEN)
3759 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART6LPEN)
3763 #define __HAL_RCC_USART10_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART10LPE…
3767 #define __HAL_RCC_USART11_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART11LPE…
3771 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CECLPEN)
3775 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART7LPEN)
3779 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART8LPEN)
3784 #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART9LPEN)
3788 #define __HAL_RCC_UART12_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART12LPE…
3791 #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_DTSLPEN)
3793 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_LPTIM2LPEN)
3795 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_FDCANLPEN)
3798 #define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UCPD1LPEN)
3801 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM2LPEN)
3803 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM3LPEN)
3806 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM4LPEN)
3810 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM5LPEN)
3813 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM6LPEN)
3815 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM7LPEN)
3818 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM12LPE…
3822 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM13LPE…
3826 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM14LPE…
3829 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_WWDGLPEN)
3832 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_OPAMPLPE…
3835 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI2LPEN)
3837 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI3LPEN)
3840 #define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_COMPLPEN)
3843 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART2LP…
3845 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART3LP…
3848 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART4LPE…
3852 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART5LPE…
3855 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C1LPEN)
3857 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C2LPEN)
3859 #define __HAL_RCC_I3C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I3C1LPEN)
3861 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CRSLPEN)
3864 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART6LP…
3868 #define __HAL_RCC_USART10_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART10L…
3872 #define __HAL_RCC_USART11_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART11L…
3876 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CECLPEN)
3880 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART7LPE…
3884 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART8LPE…
3889 #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART9LPE…
3893 #define __HAL_RCC_UART12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART12LP…
3896 #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_DTSLPEN)
3898 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_LPTIM2LP…
3900 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_FDCANLPE…
3903 #define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UCPD1LPE…
3916 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN)
3918 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN)
3921 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM8LPEN)
3924 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPE…
3927 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN)
3931 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN)
3935 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN)
3939 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN)
3943 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI6LPEN)
3947 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN)
3951 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN)
3955 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN)
3958 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPE…
3960 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPE…
3963 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM8LPE…
3966 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1L…
3969 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LP…
3973 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LP…
3977 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LP…
3981 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPE…
3985 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI6LPE…
3989 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPE…
3993 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPE…
3997 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN)
4010 #define __HAL_RCC_SBS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SBSLPEN)
4013 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SPI5LPEN)
4016 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPUART1LP…
4019 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C3LPEN)
4023 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C4LPEN)
4027 #define __HAL_RCC_I3C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I3C2LPEN)
4030 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM1LPE…
4033 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM3LPE…
4037 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM4LPE…
4041 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM5LPE…
4045 #define __HAL_RCC_LPTIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM6LPE…
4049 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_VREFLPEN)
4052 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBLPE…
4054 #define __HAL_RCC_SBS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SBSLPEN)
4057 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SPI5LPE…
4060 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPUART1…
4063 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C3LPE…
4067 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C4LPE…
4071 #define __HAL_RCC_I3C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I3C2LPE…
4074 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM1L…
4077 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM3L…
4081 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM4L…
4085 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM5L…
4089 #define __HAL_RCC_LPTIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM6L…
4093 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_VREFLPE…
4096 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBL…
4113 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST)
4115 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST)
4133 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
4135 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
4150 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV , (uint32_t)(__HSIDIV__))
4161 #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
4179 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
4181 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
4192 …MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_HSICFGR_H…
4203 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
4205 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
4225 #define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION)
4227 #define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)
4237 …MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_C…
4249 #define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON)
4250 #define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)
4261 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSION)
4263 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION)
4290 SET_BIT(RCC->CR, RCC_CR_HSEON); \
4294 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
4295 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \
4296 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
4300 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
4301 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \
4302 SET_BIT(RCC->CR, RCC_CR_HSEON); \
4306 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
4307 SET_BIT(RCC->CR, RCC_CR_HSEEXT); \
4308 SET_BIT(RCC->CR, RCC_CR_HSEON); \
4312 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
4313 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
4314 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \
4344 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
4348 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
4349 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \
4350 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
4354 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
4355 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \
4356 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
4360 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
4361 SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \
4362 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
4366 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
4367 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
4368 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \
4379 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON)
4381 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON)
4405 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_RTCPRE, \
4406 (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR1, RCC_CFGR1_RTCPRE)
4409 … RCC->BDCR &= ~RCC_BDCR_RTCSEL; \
4410 … RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
4422 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
4492 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_RTCPRE)))
4501 #define __HAL_RCC_PLL1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON)
4502 #define __HAL_RCC_PLL1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
4518 #define __HAL_RCC_PLL1_CLKOUT_ENABLE(__PLL1_CLOCKOUT__) SET_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__…
4520 #define __HAL_RCC_PLL1_CLKOUT_DISABLE(__PLL1_CLOCKOUT__) CLEAR_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT…
4532 #define __HAL_RCC_GET_PLL1_CLKOUT_CONFIG(__PLL1_CLOCKOUT__) READ_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKO…
4539 #define __HAL_RCC_PLL1_FRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN)
4541 #define __HAL_RCC_PLL1_FRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN)
4578 do{ MODIFY_REG(RCC->PLL1CFGR, (RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M), \
4580 WRITE_REG(RCC->PLL1DIVR , ( (((__PLL1N__) - 1U ) & RCC_PLL1DIVR_PLL1N) | \
4596 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, (__PLL1SOURCE__))
4611 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (__PLL1M__) << RCC_PLL1CFGR_PLL1M_Pos)
4628 #define __HAL_RCC_PLL1_FRACN_CONFIG(__PLL1FRACN__) WRITE_REG(RCC->PLL1FRACR, \
4641 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, (__PLL1VCIRange__))
4653 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
4663 #define __HAL_RCC_GET_PLL1_OSCSOURCE() ((uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC))
4676 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, (__SYSCLKSOURCE__))
4686 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR1 & RCC_CFGR1_SWS))
4703 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
4715 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, (__STOPWUCLK__))
4728 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
4747 …MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCO1SEL | RCC_CFGR1_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)…
4763 …MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCO2SEL | RCC_CFGR1_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__…
4792 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
4812 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
4832 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__))
4851 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
4858 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)
4885 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
4886 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
4887 ((((__FLAG__) >> 5U) == 3U) ? RCC->RSR : RCC->CIFR))) & \