Lines Matching refs:RCC
947 #define RCC_FLAG_HSIRDY ( (RCC->OCRDYR & RCC_OCRDYR_HSIRDY) == RCC_OCRDYR_HSIRDY )
948 #define RCC_FLAG_HSIDIVRDY ( (RCC->OCRDYR & RCC_OCRDYR_HSIDIVRDY) == RCC_OCRDYR_HSIDIVRDY )
949 #define RCC_FLAG_CSIRDY ( (RCC->OCRDYR & RCC_OCRDYR_CSIRDY) == RCC_OCRDYR_CSIRDY )
950 #define RCC_FLAG_HSERDY ( (RCC->OCRDYR & RCC_OCRDYR_HSERDY) == RCC_OCRDYR_HSERDY )
951 #define RCC_FLAG_AXICKRDY ( (RCC->OCRDYR & RCC_OCRDYR_AXICKRDY) == RCC_OCRDYR_AXICKRDY )
952 #define RCC_FLAG_CKREST ( (RCC->OCRDYR & RCC_OCRDYR_CKREST) == RCC_OCRDYR_CKREST )
955 #define RCC_FLAG_MPUSRCRDY ( (RCC->MPCKSELR & RCC_MPCKSELR_MPUSRCRDY) == RCC_MPCKSELR_MP…
958 #define RCC_FLAG_AXISSRCRDY ( (RCC->ASSCKSELR & RCC_ASSCKSELR_AXISSRCRDY) == RCC_ASSCKSELR_A…
961 #define RCC_FLAG_MCUSSRCRDY ( (RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRCRDY) == RCC_MSSCKSELR_M…
964 #define RCC_FLAG_PLL12SRCRDY ( (RCC->RCK12SELR & RCC_RCK12SELR_PLL12SRCRDY) == RCC_RCK12SELR_P…
967 #define RCC_FLAG_PLL3SRCRDY ( (RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRCRDY) == RCC_RCK3SELR_PL…
970 #define RCC_FLAG_PLL4SRCRDY ( (RCC->RCK4SELR & RCC_RCK4SELR_PLL4SRCRDY) == RCC_RCK4SELR_PL…
973 #define RCC_FLAG_TIMG1PRERDY ( (RCC->TIMG1PRER & RCC_TIMG1PRER_TIMG1PRERDY) == RCC_TIMG1PRER_T…
976 #define RCC_FLAG_TIMG2PRERDY ( (RCC->TIMG2PRER & RCC_TIMG2PRER_TIMG2PRERDY) == RCC_TIMG2PRER_T…
979 #define RCC_FLAG_MPUDIVRDY ( (RCC->MPCKDIVR & RCC_MPCKDIVR_MPUDIVRDY) == RCC_MPCKDIVR_MP…
982 #define RCC_FLAG_AXIDIVRDY ( (RCC->AXIDIVR & RCC_AXIDIVR_AXIDIVRDY) == RCC_AXIDIVR_AXI…
985 #define RCC_FLAG_APB4DIVRDY ( (RCC->APB4DIVR & RCC_APB4DIVR_APB4DIVRDY) == RCC_APB4DIVR_AP…
988 #define RCC_FLAG_APB5DIVRDY ( (RCC->APB5DIVR & RCC_APB5DIVR_APB5DIVRDY) == RCC_APB5DIVR_AP…
991 #define RCC_FLAG_MCUDIVRDY ( (RCC->MCUDIVR & RCC_MCUDIVR_MCUDIVRDY) == RCC_MCUDIVR_MC…
994 #define RCC_FLAG_APB1DIVRDY ((RCC->APB1DIVR & RCC_APB1DIVR_APB1DIVRDY) == RCC_APB1DIVR_A…
997 #define RCC_FLAG_APB2DIVRDY ((RCC->APB2DIVR & RCC_APB2DIVR_APB2DIVRDY) == RCC_APB2DIVR_A…
1000 #define RCC_FLAG_APB3DIVRDY ((RCC->APB3DIVR & RCC_APB3DIVR_APB3DIVRDY) == RCC_APB3DIVR_A…
1003 #define RCC_FLAG_PLL1RDY ((RCC->PLL1CR & RCC_PLL1CR_PLL1RDY) == RCC_PLL1CR_PLL…
1006 #define RCC_FLAG_PLL2RDY ((RCC->PLL2CR & RCC_PLL2CR_PLL2RDY) == RCC_PLL2CR_PLL…
1009 #define RCC_FLAG_PLL3RDY ((RCC->PLL3CR & RCC_PLL3CR_PLL3RDY) == RCC_PLL3CR_PLL…
1012 #define RCC_FLAG_PLL4RDY ((RCC->PLL4CR & RCC_PLL4CR_PLL4RDY) == RCC_PLL4CR_PLL…
1015 #define RCC_FLAG_DDRPHYCSRCRDY ((RCC->DDRCKSELR & RCC_DDRCKSELR_DDRPHYCSRCRDY) == RCC_DDRCKSELR_…
1018 #define RCC_FLAG_LSERDY ((RCC->BDCR & RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY…
1021 #define RCC_FLAG_LSIRDY ((RCC->RDLSICR & RCC_RDLSICR_LSIRDY) == RCC_RDLSICR_LS…
1026 #define RCC_FLAG_PORRST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_PORRSTF) == RCC_MP_RSTSCLRR…
1027 #define RCC_FLAG_BORRST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_BORRSTF) == RCC_MP_RSTSCLRR…
1028 #define RCC_FLAG_PADRST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_PADRSTF) == RCC_MP_RSTSCLRR…
1029 #define RCC_FLAG_HCSSRST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_HCSSRSTF) == RCC_MP_RSTSCLRR…
1030 #define RCC_FLAG_VCORERST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_VCORERSTF) == RCC_MP_RSTSCL…
1031 #define RCC_FLAG_MPSYSRSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_MPSYSRSTF) == RCC_MP_RSTSCL…
1032 #define RCC_FLAG_MCSYSRSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_MCSYSRSTF) == RCC_MP_RSTSCL…
1033 #define RCC_FLAG_IWDG1RST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_IWDG1RSTF) == RCC_MP_RSTSCL…
1034 #define RCC_FLAG_IWDG2RST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_IWDG2RSTF) == RCC_MP_RSTSCL…
1035 #define RCC_FLAG_STDBYRSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_STDBYRSTF) == RCC_MP_RSTSCL…
1036 #define RCC_FLAG_CSTDBYRSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_CSTDBYRSTF) == RCC_MP_RSTSCL…
1037 #define RCC_FLAG_MPUP0RSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_MPUP0RSTF) == RCC_MP_RSTSCL…
1038 #define RCC_FLAG_MPUP1RSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_MPUP1RSTF) == RCC_MP_RSTSCL…
1042 #define RCC_FLAG_PORRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_PORRSTF) == RCC_MC_RSTSCLRR…
1043 #define RCC_FLAG_BORRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_BORRSTF) == RCC_MC_RSTSCLRR…
1044 #define RCC_FLAG_PADRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_PADRSTF) == RCC_MC_RSTSCLRR…
1045 #define RCC_FLAG_HCSSRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_HCSSRSTF) == RCC_MC_RSTSCLR…
1046 #define RCC_FLAG_VCORERST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_VCORERSTF) == RCC_MC_RSTSCL…
1047 #define RCC_FLAG_MCURST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_MCURSTF) == RCC_MC_RSTSCLRR…
1048 #define RCC_FLAG_MPSYSRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_MPSYSRSTF) == RCC_MC_RSTSCL…
1049 #define RCC_FLAG_MCSYSRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_MCSYSRSTF) == RCC_MC_RSTSCL…
1050 #define RCC_FLAG_IWDG1RST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_IWDG1RSTF) == RCC_MC_RSTSCL…
1051 #define RCC_FLAG_IWDG2RST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_IWDG2RSTF) == RCC_MC_RSTSCL…
1052 #define RCC_FLAG_WWDG1RST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_WWDG1RSTF) == RCC_MC_RSTSCL…
1059 #define __HAL_RCC_CLEAR_RESET_FLAGS() WRITE_REG(RCC->MP_RSTSCLRR, RCC_MASK_ALL_RESET_FLAGS)
1061 #define __HAL_RCC_CLEAR_RESET_FLAGS() WRITE_REG(RCC->MC_RSTSCLRR, RCC_MASK_ALL_RESET_FLAGS)
1188 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTSETR = 0xADEFDBFFU)
1189 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM2RST)
1190 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM3RST)
1191 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM4RST)
1192 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM5RST)
1193 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM6RST)
1194 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM7RST)
1195 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM12RST)
1196 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM13RST)
1197 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM14RST)
1198 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_LPTIM1RST)
1199 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_SPI2RST)
1200 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_SPI3RST)
1201 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_USART2RST)
1202 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_USART3RST)
1203 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_UART4RST)
1204 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_UART5RST)
1205 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_UART7RST)
1206 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_UART8RST)
1207 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_I2C1RST)
1208 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_I2C2RST)
1209 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_I2C3RST)
1210 #define __HAL_RCC_I2C5_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_I2C5RST)
1211 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_SPDIFRST)
1212 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_CECRST)
1213 #define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_DAC12RST)
1214 #define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_MDIOSRST)
1216 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTCLRR = 0xADEFDBFFU)
1217 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM2RST)
1218 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM3RST)
1219 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM4RST)
1220 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM5RST)
1221 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM6RST)
1222 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM7RST)
1223 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM12RST)
1224 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM13RST)
1225 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM14RST)
1226 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_LPTIM1RST)
1227 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_SPI2RST)
1228 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_SPI3RST)
1229 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_USART2RST)
1230 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_USART3RST)
1231 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_UART4RST)
1232 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_UART5RST)
1233 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_UART7RST)
1234 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_UART8RST)
1235 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_I2C1RST)
1236 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_I2C2RST)
1237 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_I2C3RST)
1238 #define __HAL_RCC_I2C5_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_I2C5RST)
1239 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_SPDIFRST)
1240 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_CECRST)
1241 #define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_DAC12RST)
1242 #define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_MDIOSRST)
1245 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTSETR = 0x117271FU)
1246 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM1RST)
1247 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM8RST)
1248 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM15RST)
1249 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM16RST)
1250 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM17RST)
1251 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SPI1RST)
1252 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SPI4RST)
1253 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SPI5RST)
1254 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_USART6RST)
1255 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SAI1RST)
1256 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SAI2RST)
1257 #define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SAI3RST)
1258 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_DFSDMRST)
1259 #define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_FDCANRST)
1261 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTCLRR = 0x117271FU)
1262 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM1RST)
1263 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM8RST)
1264 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM15RST)
1265 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM16RST)
1266 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM17RST)
1267 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SPI1RST)
1268 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SPI4RST)
1269 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SPI5RST)
1270 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_USART6RST)
1271 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SAI1RST)
1272 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SAI2RST)
1273 #define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SAI3RST)
1274 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_DFSDMRST)
1275 #define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_FDCANRST)
1278 #define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTSETR = 0x0003290FU)
1279 #define __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_LPTIM2RST)
1280 #define __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_LPTIM3RST)
1281 #define __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_LPTIM4RST)
1282 #define __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_LPTIM5RST)
1283 #define __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_SAI4RST)
1284 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_SYSCFGRST)
1285 #define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_VREFRST)
1286 #define __HAL_RCC_DTS_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_DTSRST)
1288 #define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTCLRR = 0x0003290FU)
1289 #define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM2RST)
1290 #define __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM3RST)
1291 #define __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM4RST)
1292 #define __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM5RST)
1293 #define __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_SAI4RST)
1294 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_SYSCFGRST)
1295 #define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_VREFRST)
1296 #define __HAL_RCC_DTS_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_DTSRST)
1299 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTSETR = 0x00010127U)
1300 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_DMA1RST)
1301 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_DMA2RST)
1302 #define __HAL_RCC_DMAMUX_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_DMAMUXRST)
1303 #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_ADC12RST)
1304 #define __HAL_RCC_USBO_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_USBORST)
1305 #define __HAL_RCC_SDMMC3_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_SDMMC3RST)
1307 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTCLRR = 0x00010127U)
1308 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_DMA1RST)
1309 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_DMA2RST)
1310 #define __HAL_RCC_DMAMUX_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_DMAMUXRST)
1311 #define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_ADC12RST)
1312 #define __HAL_RCC_USBO_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_USBORST)
1313 #define __HAL_RCC_SDMMC3_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_SDMMC3RST)
1316 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_DCMIRST)
1318 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTSETR = 0x000018F1U)
1319 #define __HAL_RCC_CRYP2_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_CRYP2RST)
1321 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTSETR = 0x000018E1U)
1323 #define __HAL_RCC_HASH2_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_HASH2RST)
1324 #define __HAL_RCC_RNG2_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_RNG2RST)
1325 #define __HAL_RCC_CRC2_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_CRC2RST)
1326 #define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_HSEMRST)
1327 #define __HAL_RCC_IPCC_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_IPCCRST)
1329 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_DCMIRST)
1331 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTCLRR = 0x000018F1U)
1332 #define __HAL_RCC_CRYP2_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_CRYP2RST)
1334 #define __HAL_RCC_AHB3_REALEASE_RESET() (RCC->AHB3RSTCLRR = 0x000018E1U)
1336 #define __HAL_RCC_HASH2_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_HASH2RST)
1337 #define __HAL_RCC_RNG2_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_RNG2RST)
1338 #define __HAL_RCC_CRC2_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_CRC2RST)
1339 #define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_HSEMRST)
1340 #define __HAL_RCC_IPCC_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_IPCCRST)
1343 #define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTSETR = 0x000007FFU)
1344 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOARST)
1345 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOBRST)
1346 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOCRST)
1347 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIODRST)
1348 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOERST)
1349 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOFRST)
1350 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOGRST)
1351 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOHRST)
1352 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOIRST)
1353 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOJRST)
1354 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOKRST)
1356 #define __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTCLRR = 0x000007FFU)
1357 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOARST)
1358 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOBRST)
1359 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOCRST)
1360 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIODRST)
1361 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOERST)
1362 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOFRST)
1363 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOGRST)
1364 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOHRST)
1365 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOIRST)
1366 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOJRST)
1367 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOKRST)
1370 #define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTSETR = 0x00010111U)
1371 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB4RSTSETR = RCC_APB4RSTSETR_LTDCRST)
1372 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB4RSTSETR = RCC_APB4RSTSETR_DSIRST)
1373 #define __HAL_RCC_DDRPERFM_FORCE_RESET() (RCC->APB4RSTSETR = RCC_APB4RSTSETR_DDRPERFMRST)
1374 #define __HAL_RCC_USBPHY_FORCE_RESET() (RCC->APB4RSTSETR = RCC_APB4RSTSETR_USBPHYRST)
1376 #define __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTCLRR = 0x00010111U)
1377 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB4RSTCLRR = RCC_APB4RSTCLRR_LTDCRST)
1378 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB4RSTCLRR = RCC_APB4RSTCLRR_DSIRST)
1379 #define __HAL_RCC_DDRPERFM_RELEASE_RESET() (RCC->APB4RSTCLRR = RCC_APB4RSTCLRR_DDRPERFMRST)
1380 #define __HAL_RCC_USBPHY_RELEASE_RESET() (RCC->APB4RSTCLRR = RCC_APB4RSTCLRR_USBPHYRST)
1386 #define __HAL_RCC_APB5_FORCE_RESET() (RCC->APB5RSTSETR = 0x0010001DU)
1387 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_SPI6RST)
1388 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_I2C4RST)
1389 #define __HAL_RCC_I2C6_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_I2C6RST)
1390 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_USART1RST)
1391 #define __HAL_RCC_STGEN_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_STGENRST)
1393 #define __HAL_RCC_APB5_RELEASE_RESET() (RCC->APB5RSTCLRR = 0x0010001DU)
1394 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_SPI6RST)
1395 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_I2C4RST)
1396 #define __HAL_RCC_I2C6_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_I2C6RST)
1397 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_USART1RST)
1398 #define __HAL_RCC_STGEN_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_STGENRST)
1401 #define __HAL_RCC_GPIOZ_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_GPIOZRST)
1403 #define __HAL_RCC_CRYP1_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_CRYP1RST)
1404 #define __HAL_RCC_AHB5_FORCE_RESET() (RCC->AHB5RSTSETR = 0x00010071U)
1406 #define __HAL_RCC_AHB5_FORCE_RESET() (RCC->AHB5RSTSETR = 0x00010061U)
1408 #define __HAL_RCC_HASH1_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_HASH1RST)
1409 #define __HAL_RCC_RNG1_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_RNG1RST)
1410 #define __HAL_RCC_AXIMC_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_AXIMCRST)
1412 #define __HAL_RCC_GPIOZ_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_GPIOZRST)
1414 #define __HAL_RCC_CRYP1_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_CRYP1RST)
1415 #define __HAL_RCC_AHB5_RELEASE_RESET() (RCC->AHB5RSTCLRR = 0x00010071U)
1417 #define __HAL_RCC_AHB5_RELEASE_RESET() (RCC->AHB5RSTCLRR = 0x00010061U)
1419 #define __HAL_RCC_HASH1_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_HASH1RST)
1420 #define __HAL_RCC_RNG1_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_RNG1RST)
1421 #define __HAL_RCC_AXIMC_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_AXIMCRST)
1424 #define __HAL_RCC_AHB6_FORCE_RESET() (RCC->AHB6RSTSETR = 0x01135420U)
1425 #define __HAL_RCC_GPU_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_GPURST)
1426 #define __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_ETHMACRST)
1427 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_FMCRST)
1428 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_QSPIRST)
1429 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_SDMMC1RST)
1430 #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_SDMMC2RST)
1431 #define __HAL_RCC_CRC1_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_CRC1RST)
1432 #define __HAL_RCC_USBH_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_USBHRST)
1440 #define __HAL_RCC_AHB6_RELEASE_RESET() (RCC->AHB6RSTCLRR = 0x01135400U)
1441 #define __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_ETHMACRST)
1442 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_FMCRST)
1443 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_QSPIRST)
1444 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_SDMMC1RST)
1445 #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_SDMMC2RST)
1446 #define __HAL_RCC_CRC1_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_CRC1RST)
1447 #define __HAL_RCC_USBH_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_USBHRST)
1450 #define __HAL_RCC_TZAHB6_FORCE_RESET() (RCC->TZAHB6RSTSETR = 0x00000001U)
1451 #define __HAL_RCC_MDMA_FORCE_RESET() (RCC->TZAHB6RSTSETR = RCC_TZAHB6RSTSETR_MDMARST)
1453 #define __HAL_RCC_TZAHB6_RELEASE_RESET() (RCC->TZAHB6RSTCLRR = 0x00000001U)
1454 #define __HAL_RCC_MDMA_RELEASE_RESET() (RCC->TZAHB6RSTCLRR = RCC_TZAHB6RSTCLRR_MDMARST)
1462 #define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM2EN)
1463 #define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM3EN)
1464 #define __HAL_RCC_TIM4_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM4EN)
1465 #define __HAL_RCC_TIM5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM5EN)
1466 #define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM6EN)
1467 #define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM7EN)
1468 #define __HAL_RCC_TIM12_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM12EN)
1469 #define __HAL_RCC_TIM13_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM13EN)
1470 #define __HAL_RCC_TIM14_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM14EN)
1471 #define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_LPTIM1EN)
1472 #define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_SPI2EN)
1473 #define __HAL_RCC_SPI3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_SPI3EN)
1474 #define __HAL_RCC_USART2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_USART2EN)
1475 #define __HAL_RCC_USART3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_USART3EN)
1476 #define __HAL_RCC_UART4_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_UART4EN)
1477 #define __HAL_RCC_UART5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_UART5EN)
1478 #define __HAL_RCC_UART7_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_UART7EN)
1479 #define __HAL_RCC_UART8_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_UART8EN)
1480 #define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_I2C1EN)
1481 #define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_I2C2EN)
1482 #define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_I2C3EN)
1483 #define __HAL_RCC_I2C5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_I2C5EN)
1484 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_SPDIFEN)
1485 #define __HAL_RCC_CEC_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_CECEN)
1486 #define __HAL_RCC_DAC12_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_DAC12EN)
1487 #define __HAL_RCC_MDIOS_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_MDIOSEN)
1489 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM2EN)
1490 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM3EN)
1491 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM4EN)
1492 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM5EN)
1493 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM6EN)
1494 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM7EN)
1495 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM12EN)
1496 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM13EN)
1497 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM14EN)
1498 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_LPTIM1EN)
1499 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_SPI2EN)
1500 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_SPI3EN)
1501 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_USART2EN)
1502 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_USART3EN)
1503 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART4EN)
1504 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART4EN)
1505 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART5EN)
1506 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART7EN)
1507 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART8EN)
1508 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_I2C1EN)
1509 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_I2C2EN)
1510 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_I2C3EN)
1511 #define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_I2C5EN)
1512 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_SPDIFEN)
1513 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_CECEN)
1514 #define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_DAC12EN)
1515 #define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_MDIOSEN)
1522 #define __HAL_RCC_TIM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM1EN)
1523 #define __HAL_RCC_TIM8_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM8EN)
1524 #define __HAL_RCC_TIM15_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM15EN)
1525 #define __HAL_RCC_TIM16_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM16EN)
1526 #define __HAL_RCC_TIM17_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM17EN)
1527 #define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SPI1EN)
1528 #define __HAL_RCC_SPI4_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SPI4EN)
1529 #define __HAL_RCC_SPI5_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SPI5EN)
1530 #define __HAL_RCC_USART6_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_USART6EN)
1531 #define __HAL_RCC_SAI1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SAI1EN)
1532 #define __HAL_RCC_SAI2_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SAI2EN)
1533 #define __HAL_RCC_SAI3_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SAI3EN)
1534 #define __HAL_RCC_DFSDM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_DFSDMEN)
1535 #define __HAL_RCC_ADFSDM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_ADFSDMEN)
1536 #define __HAL_RCC_FDCAN_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_FDCANEN)
1538 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM1EN)
1539 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM8EN)
1540 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM15EN)
1541 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM16EN)
1542 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM17EN)
1543 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SPI1EN)
1544 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SPI4EN)
1545 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SPI5EN)
1546 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_USART6EN)
1547 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SAI1EN)
1548 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SAI2EN)
1549 #define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SAI3EN)
1550 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_DFSDMEN)
1551 #define __HAL_RCC_ADFSDM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_ADFSDMEN)
1552 #define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_FDCANEN)
1559 #define __HAL_RCC_LPTIM2_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_LPTIM2EN)
1560 #define __HAL_RCC_LPTIM3_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_LPTIM3EN)
1561 #define __HAL_RCC_LPTIM4_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_LPTIM4EN)
1562 #define __HAL_RCC_LPTIM5_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_LPTIM5EN)
1563 #define __HAL_RCC_SAI4_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_SAI4EN)
1564 #define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_SYSCFGEN)
1565 #define __HAL_RCC_VREF_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_VREFEN)
1566 #define __HAL_RCC_DTS_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_DTSEN)
1567 #define __HAL_RCC_HDP_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_HDPEN)
1569 #define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_LPTIM2EN)
1570 #define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_LPTIM3EN)
1571 #define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_LPTIM4EN)
1572 #define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_LPTIM5EN)
1573 #define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_SAI4EN)
1574 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_SYSCFGEN)
1575 #define __HAL_RCC_VREF_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_VREFEN)
1576 #define __HAL_RCC_DTS_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_DTSEN)
1577 #define __HAL_RCC_HDP_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_HDPEN)
1584 #define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_LTDCEN)
1585 #define __HAL_RCC_DSI_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_DSIEN)
1586 #define __HAL_RCC_DDRPERFM_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_DDRPERFMEN)
1587 #define __HAL_RCC_IWDG2APB_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_IWDG2APBEN)
1588 #define __HAL_RCC_USBPHY_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_USBPHYEN)
1589 #define __HAL_RCC_STGENRO_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_STGENROEN)
1591 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_LTDCEN)
1592 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_DSIEN)
1593 #define __HAL_RCC_DDRPERFM_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_DDRPERFMEN)
1594 #define __HAL_RCC_IWDG2APB_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_IWDG2APBEN)
1595 #define __HAL_RCC_USBPHY_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_USBPHYEN)
1596 #define __HAL_RCC_STGENRO_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_STGENROEN)
1603 #define __HAL_RCC_SPI6_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_SPI6EN)
1604 #define __HAL_RCC_I2C4_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_I2C4EN)
1605 #define __HAL_RCC_I2C6_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_I2C6EN)
1606 #define __HAL_RCC_USART1_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_USART1EN)
1607 #define __HAL_RCC_RTCAPB_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_RTCAPBEN)
1608 #define __HAL_RCC_TZC1_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_TZC1EN)
1609 #define __HAL_RCC_TZC2_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_TZC2EN)
1610 #define __HAL_RCC_TZPC_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_TZPCEN)
1611 #define __HAL_RCC_IWDG1APB_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_IWDG1APBEN)
1612 #define __HAL_RCC_BSEC_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_BSECEN)
1613 #define __HAL_RCC_STGEN_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_STGENEN)
1615 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_SPI6EN)
1616 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_I2C4EN)
1617 #define __HAL_RCC_I2C6_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_I2C6EN)
1618 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_USART1EN)
1619 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_RTCAPBEN)
1620 #define __HAL_RCC_TZC1_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_TZC1EN)
1621 #define __HAL_RCC_TZC2_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_TZC2EN)
1622 #define __HAL_RCC_TZPC_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_TZPCEN)
1623 #define __HAL_RCC_IWDG1APB_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_IWDG1APBEN)
1624 #define __HAL_RCC_BSEC_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENSETR_BSECEN)
1625 #define __HAL_RCC_STGEN_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENSETR_STGENEN)
1632 #define __HAL_RCC_GPIOZ_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_GPIOZEN)
1634 #define __HAL_RCC_CRYP1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_CRYP1EN)
1636 #define __HAL_RCC_HASH1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_HASH1EN)
1637 #define __HAL_RCC_RNG1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_RNG1EN)
1638 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_BKPSRAMEN)
1640 #define __HAL_RCC_GPIOZ_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_GPIOZEN)
1642 #define __HAL_RCC_CRYP1_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_CRYP1EN)
1644 #define __HAL_RCC_HASH1_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_HASH1EN)
1645 #define __HAL_RCC_RNG1_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_RNG1EN)
1646 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_BKPSRAMEN)
1653 #define __HAL_RCC_MDMA_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_MDMAEN)
1654 #define __HAL_RCC_GPU_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_GPUEN)
1655 #define __HAL_RCC_ETH1CK_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_ETHCKEN)
1656 #define __HAL_RCC_ETH1TX_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_ETHTXEN)
1657 #define __HAL_RCC_ETH1RX_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_ETHRXEN)
1658 #define __HAL_RCC_ETH1MAC_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_ETHMACEN)
1659 #define __HAL_RCC_FMC_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_FMCEN)
1660 #define __HAL_RCC_QSPI_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_QSPIEN)
1661 #define __HAL_RCC_SDMMC1_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_SDMMC1EN)
1662 #define __HAL_RCC_SDMMC2_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_SDMMC2EN)
1663 #define __HAL_RCC_CRC1_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_CRC1EN)
1664 #define __HAL_RCC_USBH_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_USBHEN)
1666 #define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_MDMAEN)
1667 #define __HAL_RCC_GPU_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_GPUEN)
1668 #define __HAL_RCC_ETH1CK_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_ETHCKEN)
1669 #define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_ETHTXEN)
1670 #define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_ETHRXEN)
1671 #define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_ETHMACEN)
1672 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_FMCEN)
1673 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_QSPIEN)
1674 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_SDMMC1EN)
1675 #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_SDMMC2EN)
1676 #define __HAL_RCC_CRC1_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_CRC1EN)
1677 #define __HAL_RCC_USBH_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_USBHEN)
1684 #define __HAL_RCC_DMA1_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_DMA1EN)
1685 #define __HAL_RCC_DMA2_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_DMA2EN)
1686 #define __HAL_RCC_DMAMUX_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_DMAMUXEN)
1687 #define __HAL_RCC_ADC12_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_ADC12EN)
1688 #define __HAL_RCC_USBO_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_USBOEN)
1689 #define __HAL_RCC_SDMMC3_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_SDMMC3EN)
1691 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_DMA1EN)
1692 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_DMA2EN)
1693 #define __HAL_RCC_DMAMUX_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_DMAMUXEN)
1694 #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_ADC12EN)
1695 #define __HAL_RCC_USBO_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_USBOEN)
1696 #define __HAL_RCC_SDMMC3_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_SDMMC3EN)
1703 #define __HAL_RCC_DCMI_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_DCMIEN)
1705 #define __HAL_RCC_CRYP2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_CRYP2EN)
1707 #define __HAL_RCC_HASH2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_HASH2EN)
1708 #define __HAL_RCC_RNG2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_RNG2EN)
1709 #define __HAL_RCC_CRC2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_CRC2EN)
1710 #define __HAL_RCC_HSEM_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_HSEMEN)
1711 #define __HAL_RCC_IPCC_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_IPCCEN)
1713 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_DCMIEN)
1715 #define __HAL_RCC_CRYP2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_CRYP2EN)
1717 #define __HAL_RCC_HASH2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_HASH2EN)
1718 #define __HAL_RCC_RNG2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_RNG2EN)
1719 #define __HAL_RCC_CRC2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_CRC2EN)
1720 #define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_HSEMEN)
1721 #define __HAL_RCC_IPCC_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_IPCCEN)
1728 #define __HAL_RCC_GPIOA_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOAEN)
1729 #define __HAL_RCC_GPIOB_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOBEN)
1730 #define __HAL_RCC_GPIOC_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOCEN)
1731 #define __HAL_RCC_GPIOD_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIODEN)
1732 #define __HAL_RCC_GPIOE_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOEEN)
1733 #define __HAL_RCC_GPIOF_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOFEN)
1734 #define __HAL_RCC_GPIOG_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOGEN)
1735 #define __HAL_RCC_GPIOH_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOHEN)
1736 #define __HAL_RCC_GPIOI_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOIEN)
1737 #define __HAL_RCC_GPIOJ_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOJEN)
1738 #define __HAL_RCC_GPIOK_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOKEN)
1740 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOAEN)
1741 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOBEN)
1742 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOCEN)
1743 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIODEN)
1744 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOEEN)
1745 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOFEN)
1746 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOGEN)
1747 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOHEN)
1748 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOIEN)
1749 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOJEN)
1750 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOKEN)
1758 #define __HAL_RCC_RETRAM_CLK_ENABLE() (RCC->MP_MLAHBENSETR = RCC_MP_MLAHBENSETR_RETRAMEN)
1760 #define __HAL_RCC_RETRAM_CLK_DISABLE() (RCC->MP_MLAHBENCLRR = RCC_MP_MLAHBENCLRR_RETRAMEN)
1767 #define __HAL_RCC_MCU_RESET() (RCC->MP_GRSTCSETR = RCC_MP_GRSTCSETR_MCURST)
1773 #define __HAL_RCC_SYS_RESET() (RCC->MP_GRSTCSETR = RCC_MP_GRSTCSETR_MPSYSRST)
1784 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM2L…
1785 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM3L…
1786 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM4L…
1787 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM5L…
1788 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM6L…
1789 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM7L…
1790 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM12…
1791 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM13…
1792 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM14…
1793 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_LPTIM…
1794 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_SPI2L…
1795 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_SPI3L…
1796 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_USART…
1797 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_USART…
1798 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_UART4…
1799 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_UART5…
1800 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_UART7…
1801 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_UART8…
1802 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_I2C1L…
1803 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_I2C2L…
1804 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_I2C3L…
1805 #define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_I2C5L…
1806 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_SPDIF…
1807 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_CECLP…
1808 #define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_DAC12…
1809 #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_MDIOS…
1811 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM2L…
1812 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM3L…
1813 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM4L…
1814 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM5L…
1815 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM6L…
1816 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM7L…
1817 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM12…
1818 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM13…
1819 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM14…
1820 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_LPTIM…
1821 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_SPI2L…
1822 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_SPI3L…
1823 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_USART…
1824 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_USART…
1825 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_UART4…
1826 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_UART5…
1827 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_UART7…
1828 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_UART8…
1829 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_I2C1L…
1830 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_I2C2L…
1831 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_I2C3L…
1832 #define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_I2C5L…
1833 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_SPDIF…
1834 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_CECLP…
1835 #define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_DAC12…
1836 #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_MDIOS…
1845 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM1L…
1846 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM8L…
1847 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM15…
1848 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM16…
1849 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM17…
1850 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SPI1L…
1851 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SPI4L…
1852 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SPI5L…
1853 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_USART…
1854 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SAI1L…
1855 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SAI2L…
1856 #define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SAI3L…
1857 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_DFSDM…
1858 #define __HAL_RCC_ADFSDM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_ADFSD…
1859 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_FDCAN…
1861 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM1L…
1862 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM8L…
1863 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM15…
1864 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM16…
1865 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM17…
1866 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SPI1L…
1867 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SPI4L…
1868 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SPI5L…
1869 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_USART…
1870 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SAI1L…
1871 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SAI2L…
1872 #define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SAI3L…
1873 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_DFSDM…
1874 #define __HAL_RCC_ADFSDM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_ADFSD…
1875 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_FDCAN…
1884 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_LPTIM…
1885 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_LPTIM…
1886 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_LPTIM…
1887 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_LPTIM…
1888 #define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_SAI4L…
1889 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_SYSCF…
1890 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_VREFL…
1891 #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_DTSLP…
1893 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_LPTIM…
1894 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_LPTIM…
1895 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_LPTIM…
1896 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_LPTIM…
1897 #define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_SAI4L…
1898 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_SYSCF…
1899 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_VREFL…
1900 #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_DTSLP…
1908 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_LTDCL…
1909 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_DSILP…
1910 #define __HAL_RCC_DDRPERFM_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_DDRPE…
1911 #define __HAL_RCC_IWDG2APB_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_IWDG2…
1912 #define __HAL_RCC_USBPHY_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_USBPH…
1913 #define __HAL_RCC_STGENRO_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_STGEN…
1914 #define __HAL_RCC_STGENRO_CLK_STOP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_STGEN…
1916 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_LTDCL…
1917 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_DSILP…
1918 #define __HAL_RCC_DDRPERFM_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_DDRPE…
1919 #define __HAL_RCC_IWDG2APB_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_IWDG2…
1920 #define __HAL_RCC_USBPHY_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_USBPH…
1921 #define __HAL_RCC_STGENRO_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_STGEN…
1922 #define __HAL_RCC_STGENRO_CLK_STOP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_STGEN…
1930 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_SPI6L…
1931 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_I2C4L…
1932 #define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_I2C6L…
1933 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_USART…
1934 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_RTCAP…
1935 #define __HAL_RCC_TZC1_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_TZC1L…
1936 #define __HAL_RCC_TZC2_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_TZC2L…
1937 #define __HAL_RCC_TZPC_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_TZPCL…
1938 #define __HAL_RCC_BSEC_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_BSECL…
1939 #define __HAL_RCC_STGEN_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_STGEN…
1941 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_SPI6L…
1942 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_I2C4L…
1943 #define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_I2C6L…
1944 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_USART…
1945 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_RTCAP…
1946 #define __HAL_RCC_TZC1_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_TZC1L…
1947 #define __HAL_RCC_TZC2_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_TZC2L…
1948 #define __HAL_RCC_TZPC_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_TZPCL…
1949 #define __HAL_RCC_BSEC_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENSETR_BSECL…
1950 #define __HAL_RCC_STGEN_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENSETR_STGEN…
1959 #define __HAL_RCC_GPIOZ_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_GPIOZ…
1961 #define __HAL_RCC_CRYP1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_CRYP1…
1963 #define __HAL_RCC_HASH1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_HASH1…
1964 #define __HAL_RCC_RNG1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_RNG1L…
1965 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_BKPSR…
1967 #define __HAL_RCC_GPIOZ_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_GPIOZ…
1969 #define __HAL_RCC_CRYP1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_CRYP1…
1971 #define __HAL_RCC_HASH1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_HASH1…
1972 #define __HAL_RCC_RNG1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_RNG1L…
1973 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_BKPSR…
1982 #define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_MDMAL…
1983 #define __HAL_RCC_GPU_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_GPULP…
1984 #define __HAL_RCC_ETH1CK_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_ETHCK…
1985 #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_ETHTX…
1986 #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_ETHRX…
1987 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_ETHMA…
1988 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_FMCLP…
1989 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_QSPIL…
1990 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_SDMMC…
1991 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_SDMMC…
1992 #define __HAL_RCC_CRC1_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_CRC1L…
1993 #define __HAL_RCC_USBH_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_USBHL…
1995 #define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_MDMAL…
1996 #define __HAL_RCC_GPU_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_GPULP…
1997 #define __HAL_RCC_ETH1CK_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_ETHCK…
1998 #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_ETHTX…
1999 #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_ETHRX…
2000 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_ETHMA…
2001 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_FMCLP…
2002 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_QSPIL…
2003 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_SDMMC…
2004 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_SDMMC…
2005 #define __HAL_RCC_CRC1_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_CRC1L…
2006 #define __HAL_RCC_USBH_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_USBHL…
2015 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_DMA1L…
2016 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_DMA2L…
2017 #define __HAL_RCC_DMAMUX_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_DMAMU…
2018 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_ADC12…
2019 #define __HAL_RCC_USBO_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_USBOL…
2020 #define __HAL_RCC_SDMMC3_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_SDMMC…
2022 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_DMA1L…
2023 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_DMA2L…
2024 #define __HAL_RCC_DMAMUX_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_DMAMU…
2025 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_ADC12…
2026 #define __HAL_RCC_USBO_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_USBOL…
2027 #define __HAL_RCC_SDMMC3_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_SDMMC…
2035 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_DCMIL…
2037 #define __HAL_RCC_CRYP2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_CRYP2…
2039 #define __HAL_RCC_HASH2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_HASH2…
2040 #define __HAL_RCC_RNG2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_RNG2L…
2041 #define __HAL_RCC_CRC2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_CRC2L…
2042 #define __HAL_RCC_HSEM_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_HSEML…
2043 #define __HAL_RCC_IPCC_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_IPCCL…
2045 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_DCMIL…
2047 #define __HAL_RCC_CRYP2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_CRYP2…
2049 #define __HAL_RCC_HASH2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_HASH2…
2050 #define __HAL_RCC_RNG2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_RNG2L…
2051 #define __HAL_RCC_CRC2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_CRC2L…
2052 #define __HAL_RCC_HSEM_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_HSEML…
2053 #define __HAL_RCC_IPCC_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_IPCCL…
2062 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOA…
2063 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOB…
2064 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOC…
2065 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOD…
2066 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOE…
2067 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOF…
2068 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOG…
2069 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOH…
2070 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOI…
2071 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOJ…
2072 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOK…
2074 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOA…
2075 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOB…
2076 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOC…
2077 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOD…
2078 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOE…
2079 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOF…
2080 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOG…
2081 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOH…
2082 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOI…
2083 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOJ…
2084 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOK…
2092 #define __HAL_RCC_SYSRAM_CLK_SLEEP_ENABLE() (RCC->MP_AXIMLPENSETR = RCC_MP_AXIMLPENSETR_SYSRA…
2094 #define __HAL_RCC_SYSRAM_CLK_SLEEP_DISABLE() (RCC->MP_AXIMLPENCLRR = RCC_MP_AXIMLPENCLRR_SYSRA…
2103 #define __HAL_RCC_RETRAM_CLK_SLEEP_ENABLE() (RCC->MP_MLAHBLPENSETR = RCC_MP_MLAHBLPENSETR_RET…
2105 #define __HAL_RCC_RETRAM_CLK_SLEEP_DISABLE() (RCC->MP_MLAHBLPENCLRR = RCC_MP_MLAHBLPENCLRR_RET…
2121 #define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM2EN)
2122 #define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM3EN)
2123 #define __HAL_RCC_TIM4_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM4EN)
2124 #define __HAL_RCC_TIM5_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM5EN)
2125 #define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM6EN)
2126 #define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM7EN)
2127 #define __HAL_RCC_TIM12_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM12EN)
2128 #define __HAL_RCC_TIM13_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM13EN)
2129 #define __HAL_RCC_TIM14_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM14EN)
2130 #define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_LPTIM1EN)
2131 #define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_SPI2EN)
2132 #define __HAL_RCC_SPI3_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_SPI3EN)
2133 #define __HAL_RCC_USART2_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_USART2EN)
2134 #define __HAL_RCC_USART3_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_USART3EN)
2135 #define __HAL_RCC_UART4_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_UART4EN)
2136 #define __HAL_RCC_UART5_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_UART5EN)
2137 #define __HAL_RCC_UART7_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_UART7EN)
2138 #define __HAL_RCC_UART8_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_UART8EN)
2139 #define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_I2C1EN)
2140 #define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_I2C2EN)
2141 #define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_I2C3EN)
2142 #define __HAL_RCC_I2C5_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_I2C5EN)
2143 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_SPDIFEN)
2144 #define __HAL_RCC_CEC_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_CECEN)
2145 #define __HAL_RCC_WWDG1_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_WWDG1EN)
2146 #define __HAL_RCC_DAC12_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_DAC12EN)
2147 #define __HAL_RCC_MDIOS_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_MDIOSEN)
2149 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM2EN)
2150 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM3EN)
2151 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM4EN)
2152 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM5EN)
2153 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM6EN)
2154 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM7EN)
2155 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM12EN)
2156 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM13EN)
2157 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM14EN)
2158 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_LPTIM1EN)
2159 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPI2EN)
2160 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPI3EN)
2161 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_USART2EN)
2162 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_USART3EN)
2163 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART4EN)
2164 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART5EN)
2165 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART7EN)
2166 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART8EN)
2167 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C1EN)
2168 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C2EN)
2169 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C3EN)
2170 #define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C5EN)
2171 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPDIFEN)
2172 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_CECEN)
2173 #define __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_WWDG1EN)
2174 #define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_DAC12EN)
2175 #define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_MDIOSEN)
2182 #define __HAL_RCC_TIM1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM1EN)
2183 #define __HAL_RCC_TIM8_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM8EN)
2184 #define __HAL_RCC_TIM15_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM15EN)
2185 #define __HAL_RCC_TIM16_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM16EN)
2186 #define __HAL_RCC_TIM17_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM17EN)
2187 #define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SPI1EN)
2188 #define __HAL_RCC_SPI4_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SPI4EN)
2189 #define __HAL_RCC_SPI5_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SPI5EN)
2190 #define __HAL_RCC_USART6_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_USART6EN)
2191 #define __HAL_RCC_SAI1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SAI1EN)
2192 #define __HAL_RCC_SAI2_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SAI2EN)
2193 #define __HAL_RCC_SAI3_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SAI3EN)
2194 #define __HAL_RCC_DFSDM1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_DFSDMEN)
2195 #define __HAL_RCC_ADFSDM1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_ADFSDMEN)
2196 #define __HAL_RCC_FDCAN_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_FDCANEN)
2198 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM1EN)
2199 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM8EN)
2200 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM15EN)
2201 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM16EN)
2202 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM17EN)
2203 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI1EN)
2204 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI4EN)
2205 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI5EN)
2206 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_USART6EN)
2207 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI1EN)
2208 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI2EN)
2209 #define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI3EN)
2210 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_DFSDMEN)
2211 #define __HAL_RCC_ADFSDM1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_ADFSDMEN)
2212 #define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_FDCANEN)
2219 #define __HAL_RCC_LPTIM2_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM2EN)
2220 #define __HAL_RCC_LPTIM3_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM3EN)
2221 #define __HAL_RCC_LPTIM4_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM4EN)
2222 #define __HAL_RCC_LPTIM5_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM5EN)
2223 #define __HAL_RCC_SAI4_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_SAI4EN)
2224 #define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_SYSCFGEN)
2225 #define __HAL_RCC_VREF_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_VREFEN)
2226 #define __HAL_RCC_DTS_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_DTSEN)
2227 #define __HAL_RCC_HDP_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_HDPEN)
2229 #define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM2EN)
2230 #define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM3EN)
2231 #define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM4EN)
2232 #define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM5EN)
2233 #define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_SAI4EN)
2234 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_SYSCFGEN)
2235 #define __HAL_RCC_VREF_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_VREFEN)
2236 #define __HAL_RCC_DTS_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_DTSEN)
2237 #define __HAL_RCC_HDP_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_HDPEN)
2244 #define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_LTDCEN)
2245 #define __HAL_RCC_DSI_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_DSIEN)
2246 #define __HAL_RCC_DDRPERFM_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_DDRPERFMEN)
2247 #define __HAL_RCC_USBPHY_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_USBPHYEN)
2248 #define __HAL_RCC_STGENRO_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_STGENROEN)
2250 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_LTDCEN)
2251 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_DSIEN)
2252 #define __HAL_RCC_DDRPERFM_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_DDRPERFMEN)
2253 #define __HAL_RCC_USBPHY_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_USBPHYEN)
2254 #define __HAL_RCC_STGENRO_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_STGENROEN)
2261 #define __HAL_RCC_SPI6_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_SPI6EN)
2262 #define __HAL_RCC_I2C4_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_I2C4EN)
2263 #define __HAL_RCC_I2C6_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_I2C6EN)
2264 #define __HAL_RCC_USART1_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_USART1EN)
2265 #define __HAL_RCC_RTCAPB_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_RTCAPBEN)
2266 #define __HAL_RCC_TZC1_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_TZC1EN)
2267 #define __HAL_RCC_TZC2_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_TZC2EN)
2268 #define __HAL_RCC_TZPC_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_TZPCEN)
2269 #define __HAL_RCC_BSEC_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_BSECEN)
2270 #define __HAL_RCC_STGEN_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_STGENEN)
2272 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_SPI6EN)
2273 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_I2C4EN)
2274 #define __HAL_RCC_I2C6_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_I2C6EN)
2275 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_USART1EN)
2276 #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_RTCAPBEN)
2277 #define __HAL_RCC_TZC1_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZC1EN)
2278 #define __HAL_RCC_TZC2_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZC2EN)
2279 #define __HAL_RCC_TZPC_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZPCEN)
2280 #define __HAL_RCC_BSEC_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENSETR_BSECEN)
2281 #define __HAL_RCC_STGEN_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENSETR_STGENEN)
2288 #define __HAL_RCC_GPIOZ_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_GPIOZEN)
2290 #define __HAL_RCC_CRYP1_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_CRYP1EN)
2292 #define __HAL_RCC_HASH1_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_HASH1EN)
2293 #define __HAL_RCC_RNG1_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_RNG1EN)
2294 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_BKPSRAMEN)
2296 #define __HAL_RCC_GPIOZ_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_GPIOZEN)
2298 #define __HAL_RCC_CRYP1_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_CRYP1EN)
2300 #define __HAL_RCC_HASH1_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_HASH1EN)
2301 #define __HAL_RCC_RNG1_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_RNG1EN)
2302 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_BKPSRAMEN)
2309 #define __HAL_RCC_MDMA_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_MDMAEN)
2310 #define __HAL_RCC_GPU_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_GPUEN)
2311 #define __HAL_RCC_ETH1CK_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHCKEN)
2312 #define __HAL_RCC_ETH1TX_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHTXEN)
2313 #define __HAL_RCC_ETH1RX_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHRXEN)
2314 #define __HAL_RCC_ETH1MAC_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHMACEN)
2315 #define __HAL_RCC_FMC_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_FMCEN)
2316 #define __HAL_RCC_QSPI_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_QSPIEN)
2317 #define __HAL_RCC_SDMMC1_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_SDMMC1EN)
2318 #define __HAL_RCC_SDMMC2_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_SDMMC2EN)
2319 #define __HAL_RCC_CRC1_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_CRC1EN)
2320 #define __HAL_RCC_USBH_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_USBHEN)
2322 #define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_MDMAEN)
2323 #define __HAL_RCC_GPU_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_GPUEN)
2324 #define __HAL_RCC_ETH1CK_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHCKEN)
2325 #define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHTXEN)
2326 #define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHRXEN)
2327 #define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHMACEN)
2328 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_FMCEN)
2329 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_QSPIEN)
2330 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_SDMMC1EN)
2331 #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_SDMMC2EN)
2332 #define __HAL_RCC_CRC1_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_CRC1EN)
2333 #define __HAL_RCC_USBH_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_USBHEN)
2340 #define __HAL_RCC_DMA1_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMA1EN)
2341 #define __HAL_RCC_DMA2_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMA2EN)
2342 #define __HAL_RCC_DMAMUX_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMAMUXEN)
2343 #define __HAL_RCC_ADC12_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_ADC12EN)
2344 #define __HAL_RCC_USBO_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_USBOEN)
2345 #define __HAL_RCC_SDMMC3_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_SDMMC3EN)
2347 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMA1EN)
2348 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMA2EN)
2349 #define __HAL_RCC_DMAMUX_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMAMUXEN)
2350 #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_ADC12EN)
2351 #define __HAL_RCC_USBO_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_USBOEN)
2352 #define __HAL_RCC_SDMMC3_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_SDMMC3EN)
2359 #define __HAL_RCC_DCMI_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_DCMIEN)
2361 #define __HAL_RCC_CRYP2_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_CRYP2EN)
2363 #define __HAL_RCC_HASH2_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_HASH2EN)
2364 #define __HAL_RCC_RNG2_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_RNG2EN)
2365 #define __HAL_RCC_CRC2_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_CRC2EN)
2366 #define __HAL_RCC_HSEM_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_HSEMEN)
2367 #define __HAL_RCC_IPCC_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_IPCCEN)
2369 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_DCMIEN)
2371 #define __HAL_RCC_CRYP2_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_CRYP2EN)
2373 #define __HAL_RCC_HASH2_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_HASH2EN)
2374 #define __HAL_RCC_RNG2_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_RNG2EN)
2375 #define __HAL_RCC_CRC2_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_CRC2EN)
2376 #define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_HSEMEN)
2377 #define __HAL_RCC_IPCC_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_IPCCEN)
2384 #define __HAL_RCC_GPIOA_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOAEN)
2385 #define __HAL_RCC_GPIOB_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOBEN)
2386 #define __HAL_RCC_GPIOC_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOCEN)
2387 #define __HAL_RCC_GPIOD_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIODEN)
2388 #define __HAL_RCC_GPIOE_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOEEN)
2389 #define __HAL_RCC_GPIOF_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOFEN)
2390 #define __HAL_RCC_GPIOG_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOGEN)
2391 #define __HAL_RCC_GPIOH_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOHEN)
2392 #define __HAL_RCC_GPIOI_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOIEN)
2393 #define __HAL_RCC_GPIOJ_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOJEN)
2394 #define __HAL_RCC_GPIOK_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOKEN)
2396 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOAEN)
2397 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOBEN)
2398 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOCEN)
2399 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIODEN)
2400 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOEEN)
2401 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOFEN)
2402 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOGEN)
2403 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOHEN)
2404 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOIEN)
2405 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOJEN)
2406 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOKEN)
2413 #define __HAL_RCC_SYSRAM_CLK_ENABLE() (RCC->MC_AXIMENSETR = RCC_MC_AXIMENSETR_SYSRAMEN)
2415 #define __HAL_RCC_SYSRAM_CLK_DISABLE() (RCC->MC_AXIMENCLRR = RCC_MC_AXIMENCLRR_SYSRAMEN)
2422 #define __HAL_RCC_RETRAM_CLK_ENABLE() (RCC->MC_MLAHBENSETR = RCC_MC_MLAHBENSETR_RETRAMEN)
2424 #define __HAL_RCC_RETRAM_CLK_DISABLE() (RCC->MC_MLAHBENCLRR = RCC_MC_MLAHBENCLRR_RETRAMEN)
2438 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM2L…
2439 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM3L…
2440 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM4L…
2441 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM5L…
2442 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM6L…
2443 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM7L…
2444 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM12…
2445 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM13…
2446 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM14…
2447 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_LPTIM…
2448 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPI2L…
2449 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPI3L…
2450 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_USART…
2451 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_USART…
2452 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART4…
2453 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART5…
2454 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART7…
2455 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART8…
2456 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C1L…
2457 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C2L…
2458 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C3L…
2459 #define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C5L…
2460 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPDIF…
2461 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_CECLP…
2462 #define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_WWDG1…
2463 #define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_DAC12…
2464 #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_MDIOS…
2466 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM2L…
2467 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM3L…
2468 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM4L…
2469 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM5L…
2470 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM6L…
2471 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM7L…
2472 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM12…
2473 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM13…
2474 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM14…
2475 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_LPTIM…
2476 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPI2L…
2477 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPI3L…
2478 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_USART…
2479 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_USART…
2480 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART4…
2481 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART5…
2482 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART7…
2483 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART8…
2484 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C1L…
2485 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C2L…
2486 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C3L…
2487 #define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C5L…
2488 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPDIF…
2489 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_CECLP…
2490 #define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_WWDG1…
2491 #define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_DAC12…
2492 #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_MDIOS…
2501 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM1L…
2502 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM8L…
2503 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM15…
2504 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM16…
2505 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM17…
2506 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI1L…
2507 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI4L…
2508 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI5L…
2509 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_USART…
2510 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI1L…
2511 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI2L…
2512 #define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI3L…
2513 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_DFSDM…
2514 #define __HAL_RCC_ADFSDM1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_ADFSD…
2515 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_FDCAN…
2517 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM1L…
2518 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM8L…
2519 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM15…
2520 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM16…
2521 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM17…
2522 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI1L…
2523 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI4L…
2524 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI5L…
2525 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_USART…
2526 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI1L…
2527 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI2L…
2528 #define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI3L…
2529 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_DFSDM…
2530 #define __HAL_RCC_ADFSDM1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_ADFSD…
2531 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_FDCAN…
2540 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM…
2541 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM…
2542 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM…
2543 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM…
2544 #define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_SAI4L…
2545 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_SYSCF…
2546 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_VREFL…
2547 #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_DTSLP…
2549 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM…
2550 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM…
2551 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM…
2552 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM…
2553 #define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SAI4L…
2554 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SYSCF…
2555 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_VREFL…
2556 #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_DTSLP…
2564 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_LTDCL…
2565 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_DSILP…
2566 #define __HAL_RCC_DDRPERFM_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_DDRPE…
2567 #define __HAL_RCC_USBPHY_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_USBPH…
2568 #define __HAL_RCC_STGENRO_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_STGEN…
2569 #define __HAL_RCC_STGENRO_CLK_STOP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_STGEN…
2571 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_LTDCL…
2572 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_DSILP…
2573 #define __HAL_RCC_DDRPERFM_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_DDRPE…
2574 #define __HAL_RCC_USBPHY_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_USBPH…
2575 #define __HAL_RCC_STGENRO_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_STGEN…
2576 #define __HAL_RCC_STGENRO_CLK_STOP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_STGEN…
2584 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_SPI6L…
2585 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_I2C4L…
2586 #define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_I2C6L…
2587 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_USART…
2588 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_RTCAP…
2589 #define __HAL_RCC_TZC1_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZC1L…
2590 #define __HAL_RCC_TZC2_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZC2L…
2591 #define __HAL_RCC_TZPC_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZPCL…
2592 #define __HAL_RCC_BSEC_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_BSECL…
2593 #define __HAL_RCC_STGEN_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_STGEN…
2595 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_SPI6L…
2596 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_I2C4L…
2597 #define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_I2C6L…
2598 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_USART…
2599 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_RTCAP…
2600 #define __HAL_RCC_TZC1_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZC1L…
2601 #define __HAL_RCC_TZC2_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZC2L…
2602 #define __HAL_RCC_TZPC_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZPCL…
2603 #define __HAL_RCC_BSEC_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENSETR_BSECL…
2604 #define __HAL_RCC_STGEN_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENSETR_STGEN…
2613 #define __HAL_RCC_GPIOZ_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_GPIOZ…
2615 #define __HAL_RCC_CRYP1_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_CRYP1…
2617 #define __HAL_RCC_HASH1_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_HASH1…
2618 #define __HAL_RCC_RNG1_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_RNG1L…
2619 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_BKPSR…
2621 #define __HAL_RCC_GPIOZ_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_GPIOZ…
2623 #define __HAL_RCC_CRYP1_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_CRYP1…
2625 #define __HAL_RCC_HASH1_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_HASH1…
2626 #define __HAL_RCC_RNG1_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_RNG1L…
2627 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_BKPSR…
2636 #define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_MDMAL…
2637 #define __HAL_RCC_GPU_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_GPULP…
2638 #define __HAL_RCC_ETH1CK_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHCK…
2639 #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHTX…
2640 #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHRX…
2641 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHMA…
2642 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_FMCLP…
2643 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_QSPIL…
2644 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_SDMMC…
2645 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_SDMMC…
2646 #define __HAL_RCC_CRC1_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_CRC1L…
2647 #define __HAL_RCC_USBH_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_USBHL…
2649 #define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_MDMAL…
2650 #define __HAL_RCC_GPU_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_GPULP…
2651 #define __HAL_RCC_ETH1CK_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHCK…
2652 #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHTX…
2653 #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHRX…
2654 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHMA…
2655 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_FMCLP…
2656 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_QSPIL…
2657 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_SDMMC…
2658 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_SDMMC…
2659 #define __HAL_RCC_CRC1_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_CRC1L…
2660 #define __HAL_RCC_USBH_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_USBHL…
2669 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMA1L…
2670 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMA2L…
2671 #define __HAL_RCC_DMAMUX_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMAMU…
2672 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_ADC12…
2673 #define __HAL_RCC_USBO_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_USBOL…
2674 #define __HAL_RCC_SDMMC3_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_SDMMC…
2676 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMA1L…
2677 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMA2L…
2678 #define __HAL_RCC_DMAMUX_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMAMU…
2679 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_ADC12…
2680 #define __HAL_RCC_USBO_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_USBOL…
2681 #define __HAL_RCC_SDMMC3_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_SDMMC…
2689 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_DCMIL…
2691 #define __HAL_RCC_CRYP2_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_CRYP2…
2693 #define __HAL_RCC_HASH2_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_HASH2…
2694 #define __HAL_RCC_RNG2_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_RNG2L…
2695 #define __HAL_RCC_CRC2_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_CRC2L…
2696 #define __HAL_RCC_HSEM_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_HSEML…
2697 #define __HAL_RCC_IPCC_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_IPCCL…
2699 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_DCMIL…
2701 #define __HAL_RCC_CRYP2_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_CRYP2…
2703 #define __HAL_RCC_HASH2_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_HASH2…
2704 #define __HAL_RCC_RNG2_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_RNG2L…
2705 #define __HAL_RCC_CRC2_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_CRC2L…
2706 #define __HAL_RCC_HSEM_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_HSEML…
2707 #define __HAL_RCC_IPCC_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_IPCCL…
2716 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOA…
2717 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOB…
2718 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOC…
2719 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOD…
2720 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOE…
2721 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOF…
2722 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOG…
2723 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOH…
2724 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOI…
2725 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOJ…
2726 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOK…
2728 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOA…
2729 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOB…
2730 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOC…
2731 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOD…
2732 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOE…
2733 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOF…
2734 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOG…
2735 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOH…
2736 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOI…
2737 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOJ…
2738 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOK…
2746 #define __HAL_RCC_SYSRAM_CLK_SLEEP_ENABLE() (RCC->MC_AXIMLPENSETR = RCC_MC_AXIMLPENSETR_SYSRA…
2748 #define __HAL_RCC_SYSRAM_CLK_SLEEP_DISABLE() (RCC->MC_AXIMLPENCLRR = RCC_MC_AXIMLPENCLRR_SYSRA…
2757 #define __HAL_RCC_RETRAM_CLK_SLEEP_ENABLE() (RCC->MC_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_RET…
2758 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->MC_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_SRA…
2759 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->MC_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_SRA…
2760 #define __HAL_RCC_SRAM34_CLK_SLEEP_ENABLE() (RCC->MC_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_SRA…
2762 #define __HAL_RCC_RETRAM_CLK_SLEEP_DISABLE() (RCC->MC_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_RET…
2763 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->MC_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_SRA…
2764 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->MC_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_SRA…
2765 #define __HAL_RCC_SRAM34_CLK_SLEEP_DISABLE() (RCC->MC_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_SRA…
2773 #define __HAL_RCC_ETH1CK_CLK_STOP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHS…
2775 #define __HAL_RCC_ETH1CK_CLK_STOP_DISABLE() (RCC->MC_AHB6LPENSETR) = (RCC_MC_AHB6LPENCLRR_E…
2849 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSION)
2850 #define __HAL_RCC_HSI_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSION)
2870 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, \
2892 do{ MODIFY_REG( RCC->HSICFGR, RCC_HSICFGR_HSIDIV , (__RCC_HSIDIV__) );\
2903 #define __HAL_RCC_GET_HSI_DIV() ((uint32_t)(RCC->HSICFGR & RCC_HSICFGR_HSIDIV ))
2915 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSIKERON)
2916 #define __HAL_RCC_HSISTOP_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSIKERON)
2935 #define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_CSION)
2936 #define __HAL_RCC_CSI_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENSETR_CSION)
2947 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, \
2959 #define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_CSIKERON)
2960 #define __HAL_RCC_CSISTOP_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_CSIKERON)
2971 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->RDLSICR, RCC_RDLSICR_LSION)
2972 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->RDLSICR, RCC_RDLSICR_LSION)
2988 do { MODIFY_REG(RCC->RDLSICR, RCC_RDLSICR_MRD, \
3029 #define __HAL_RCC_HSESTOP_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSEKERON)
3030 #define __HAL_RCC_HSESTOP_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSEKERON)
3070 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
3081 #define __HAL_RCC_GET_LSEDRIVE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)))
3086 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCCKEN)
3087 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCCKEN)
3113 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSRC, (__RTCCLKSource__))
3124 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSRC)))
3132 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST)
3133 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST)
3144 #define __HAL_RCC_PLL1_ENABLE() SET_BIT(RCC->PLL1CR, RCC_PLL1CR_PLLON )
3145 #define __HAL_RCC_PLL1_DISABLE() CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_PLLON)
3159 #define __HAL_RCC_PLL1CLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLL1CR, (__RCC_PLL1Clo…
3161 #define __HAL_RCC_PLL1CLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLL1CR, (__RCC_PLL1C…
3170 #define __HAL_RCC_PLL1FRACV_ENABLE() SET_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACLE)
3172 #define __HAL_RCC_PLL1FRACV_DISABLE() CLEAR_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACLE)
3189 do{ MODIFY_REG( RCC->RCK12SELR, RCC_RCK12SELR_PLL12SRC, (__RCC_PLL12SOURCE__)); \
3199 #define __HAL_RCC_GET_PLL12_SOURCE() ((uint32_t)(RCC->RCK12SELR & RCC_RCK12SELR_PLL12SRC))
3222 do{ MODIFY_REG( RCC->PLL1CFGR1, (RCC_PLL1CFGR1_DIVN | RCC_PLL1CFGR1_DIVM1) , \
3224 … MODIFY_REG( RCC->PLL1CFGR2, (RCC_PLL1CFGR2_DIVP | RCC_PLL1CFGR2_DIVQ | RCC_PLL1CFGR2_DIVR), \
3242 MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACV,\
3248 #define __HAL_RCC_PLL1_SSMODE_ENABLE() SET_BIT(RCC->PLL1CR, RCC_PLL1CR_SSCG_CTRL)
3250 #define __HAL_RCC_PLL1_SSMODE_DISABLE() CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_SSCG_CTRL)
3280 …do{ MODIFY_REG( RCC->PLL1CSGR, (RCC_PLL1CSGR_MOD_PER | RCC_PLL1CSGR_TPDFN_DIS | RCC_PLL1CSGR_RPDF…
3295 #define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->PLL2CR, RCC_PLL2CR_PLLON )
3296 #define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_PLLON)
3309 #define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLL2CR, (__RCC_PLL2Clo…
3311 #define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLL2CR, (__RCC_PLL2C…
3319 #define __HAL_RCC_PLL2FRACV_ENABLE() SET_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACLE)
3321 #define __HAL_RCC_PLL2FRACV_DISABLE() CLEAR_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACLE)
3344 do{ MODIFY_REG( RCC->PLL2CFGR1, (RCC_PLL2CFGR1_DIVN | RCC_PLL2CFGR1_DIVM2) , \
3346 … MODIFY_REG( RCC->PLL2CFGR2, (RCC_PLL2CFGR2_DIVP | RCC_PLL2CFGR2_DIVQ | RCC_PLL2CFGR2_DIVR), \
3362 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACV, \
3368 #define __HAL_RCC_PLL2_SSMODE_ENABLE() SET_BIT(RCC->PLL2CR, RCC_PLL2CR_SSCG_CTRL)
3370 #define __HAL_RCC_PLL2_SSMODE_DISABLE() CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_SSCG_CTRL)
3401 …do{ MODIFY_REG( RCC->PLL2CSGR, (RCC_PLL2CSGR_MOD_PER | RCC_PLL2CSGR_TPDFN_DIS | RCC_PLL2CSGR_RPDF…
3414 #define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->PLL3CR, RCC_PLL3CR_PLLON )
3415 #define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_PLLON)
3428 #define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLL3CR, (__RCC_PLL3Clo…
3430 #define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLL3CR, (__RCC_PLL3C…
3439 #define __HAL_RCC_PLL3FRACV_ENABLE() SET_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACLE)
3441 #define __HAL_RCC_PLL3FRACV_DISABLE() CLEAR_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACLE)
3446 #define __HAL_RCC_PLL3_SSMODE_ENABLE() SET_BIT(RCC->PLL3CR, RCC_PLL3CR_SSCG_CTRL)
3448 #define __HAL_RCC_PLL3_SSMODE_DISABLE() CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_SSCG_CTRL)
3479 …do{ MODIFY_REG( RCC->PLL3CSGR, (RCC_PLL3CSGR_MOD_PER | RCC_PLL3CSGR_TPDFN_DIS | RCC_PLL3CSGR_RPDF…
3499 do{ MODIFY_REG( RCC->RCK3SELR, RCC_RCK3SELR_PLL3SRC, (__RCC_PLL3SOURCE__)); \
3510 #define __HAL_RCC_GET_PLL3_SOURCE() ((uint32_t)(RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRC))
3533 do{ MODIFY_REG( RCC->PLL3CFGR1, (RCC_PLL3CFGR1_DIVN | RCC_PLL3CFGR1_DIVM3) , \
3535 … MODIFY_REG( RCC->PLL3CFGR2, (RCC_PLL3CFGR2_DIVP | RCC_PLL3CFGR2_DIVQ | RCC_PLL3CFGR2_DIVR), \
3551 MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACV, \
3563 MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_IFRGE, (__RCC_PLL3IFRange__))
3573 #define __HAL_RCC_PLL4_ENABLE() SET_BIT(RCC->PLL4CR, RCC_PLL4CR_PLLON )
3574 #define __HAL_RCC_PLL4_DISABLE() CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_PLLON)
3587 #define __HAL_RCC_PLL4CLKOUT_ENABLE(__RCC_PLL4ClockOut__) SET_BIT(RCC->PLL4CR, (__RCC_PLL4Clo…
3589 #define __HAL_RCC_PLL4CLKOUT_DISABLE(__RCC_PLL4ClockOut__) CLEAR_BIT(RCC->PLL4CR, (__RCC_PLL4C…
3598 #define __HAL_RCC_PLL4FRACV_ENABLE() SET_BIT(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACLE)
3600 #define __HAL_RCC_PLL4FRACV_DISABLE() CLEAR_BIT(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACLE)
3605 #define __HAL_RCC_PLL4_SSMODE_ENABLE() SET_BIT(RCC->PLL4CR, RCC_PLL4CR_SSCG_CTRL)
3607 #define __HAL_RCC_PLL4_SSMODE_DISABLE() CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_SSCG_CTRL)
3638 …do{ MODIFY_REG( RCC->PLL4CSGR, (RCC_PLL4CSGR_MOD_PER | RCC_PLL4CSGR_TPDFN_DIS | RCC_PLL4CSGR_RPDF…
3658 do{ MODIFY_REG( RCC->RCK4SELR, RCC_RCK4SELR_PLL4SRC, (__RCC_PLL4SOURCE__)); \
3669 #define __HAL_RCC_GET_PLL4_SOURCE() ((uint32_t)(RCC->RCK4SELR & RCC_RCK4SELR_PLL4SRC))
3693 do{ MODIFY_REG( RCC->PLL4CFGR1, (RCC_PLL4CFGR1_DIVN | RCC_PLL4CFGR1_DIVM4) , \
3695 … MODIFY_REG( RCC->PLL4CFGR2, (RCC_PLL4CFGR2_DIVP | RCC_PLL4CFGR2_DIVQ | RCC_PLL4CFGR2_DIVR), \
3712 MODIFY_REG(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACV, \
3724 MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_IFRGE, (__RCC_PLL4IFRange__))
3730 #define __HAL_RCC_MCO1_ENABLE() SET_BIT(RCC->MCO1CFGR, RCC_MCO1CFGR_MCO1ON)
3731 #define __HAL_RCC_MCO1_DISABLE() CLEAR_BIT(RCC->MCO1CFGR, RCC_MCO1CFGR_MCO1ON)
3769 do{ MODIFY_REG( RCC->MCO1CFGR, (RCC_MCO1CFGR_MCO1SEL | RCC_MCO1CFGR_MCO1DIV) , \
3783 #define __HAL_RCC_GET_MCO1_SOURCE() ((uint32_t)(RCC->MCO1CFGR & RCC_MCO1CFGR_MCO1SEL))
3805 #define __HAL_RCC_GET_MCO1_DIV() ((uint32_t)(RCC->MCO1CFGR & RCC_MCO1CFGR_MCO1DIV))
3811 #define __HAL_RCC_MCO2_ENABLE() SET_BIT(RCC->MCO2CFGR, RCC_MCO2CFGR_MCO2ON)
3812 #define __HAL_RCC_MCO2_DISABLE() CLEAR_BIT(RCC->MCO2CFGR, RCC_MCO2CFGR_MCO2ON)
3851 do{ MODIFY_REG( RCC->MCO2CFGR, (RCC_MCO2CFGR_MCO2SEL | RCC_MCO2CFGR_MCO2DIV) , \
3866 #define __HAL_RCC_GET_MCO2_SOURCE() ((uint32_t)(RCC->MCO2CFGR & RCC_MCO2CFGR_MCO2SEL))
3888 #define __HAL_RCC_GET_MCO2_DIV() ((uint32_t)(RCC->MCO2CFGR & RCC_MCO2CFGR_MCO2DIV))
3905 do{ MODIFY_REG( RCC->MPCKSELR, RCC_MPCKSELR_MPUSRC , (__RCC_MPUSOURCE__));\
3916 #define __HAL_RCC_GET_MPU_SOURCE() ((uint32_t)(RCC->MPCKSELR & RCC_MPCKSELR_MPUSRC))
3933 do{ MODIFY_REG( RCC->ASSCKSELR, RCC_ASSCKSELR_AXISSRC , (__RCC_AXISSOURCE__));\
3944 #define __HAL_RCC_GET_AXIS_SOURCE() ((uint32_t)(RCC->ASSCKSELR & RCC_ASSCKSELR_AXISSRC))
3960 do{ MODIFY_REG( RCC->MSSCKSELR, RCC_MSSCKSELR_MCUSSRC , (__RCC_MCUSSOURCE__));\
3971 #define __HAL_RCC_GET_MCU_SOURCE() ((uint32_t)(RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRC))
3990 do{ MODIFY_REG( RCC->RTCDIVR, RCC_RTCDIVR_RTCDIV , ((__HSEDIV__) -1U )); \
3999 #define __HAL_RCC_GET_RTC_HSEDIV() ((uint32_t)((RCC->RTCDIVR & RCC_RTCDIVR_RTCDIV) + 1U ))
4021 do{ MODIFY_REG( RCC->MPCKDIVR, RCC_MPCKDIVR_MPUDIV , (__RCC_MPUDIV__));\
4033 #define __HAL_RCC_GET_MPU_DIV() ((uint32_t)(RCC->MPCKDIVR & RCC_MPCKDIVR_MPUDIV ))
4053 do{ MODIFY_REG( RCC->AXIDIVR, RCC_AXIDIVR_AXIDIV , (__RCC_AXIDIV__));\
4064 #define __HAL_RCC_GET_AXI_DIV() ((uint32_t)(RCC->AXIDIVR & RCC_AXIDIVR_AXIDIV ))
4084 do{ MODIFY_REG( RCC->APB4DIVR, RCC_APB4DIVR_APB4DIV , (__RCC_APB4DIV__));\
4096 #define __HAL_RCC_GET_APB4_DIV() ((uint32_t)(RCC->APB4DIVR & RCC_APB4DIVR_APB4DIV ))
4116 do{ MODIFY_REG( RCC->APB5DIVR, RCC_APB5DIVR_APB5DIV , (__RCC_APB5DIV__));\
4128 #define __HAL_RCC_GET_APB5_DIV() ((uint32_t)(RCC->APB5DIVR & RCC_APB5DIVR_APB5DIV ))
4153 do{ MODIFY_REG( RCC->MCUDIVR, RCC_MCUDIVR_MCUDIV , (__RCC_MCUDIV__));\
4170 #define __HAL_RCC_GET_MCU_DIV() ((uint32_t)(RCC->MCUDIVR & RCC_MCUDIVR_MCUDIV ))
4188 do{ MODIFY_REG( RCC->APB1DIVR, RCC_APB1DIVR_APB1DIV , (__RCC_APB1DIV__));\
4200 #define __HAL_RCC_GET_APB1_DIV() ((uint32_t)(RCC->APB1DIVR & RCC_APB1DIVR_APB1DIV ))
4220 do{ MODIFY_REG( RCC->APB2DIVR, RCC_APB2DIVR_APB2DIV , (__RCC_APB2DIV__));\
4232 #define __HAL_RCC_GET_APB2_DIV() ((uint32_t)(RCC->APB2DIVR & RCC_APB2DIVR_APB2DIV ))
4252 do{ MODIFY_REG( RCC->APB3DIVR, RCC_APB3DIVR_APB3DIV , (__RCC_APB3DIV__));\
4264 #define __HAL_RCC_GET_APB3_DIV() ((uint32_t)(RCC->APB3DIVR & RCC_APB3DIVR_APB3DIV ))
4285 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->MC_CIER, (__INTERRUPT__))
4288 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->MP_CIER, (__INTERRUPT__))
4309 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->MC_CIER, (__INTERRUPT__))
4312 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->MP_CIER, (__INTERRUPT__))
4334 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->MC_CIFR = (__INTERRUPT__))
4337 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->MP_CIFR = (__INTERRUPT__))
4358 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->MC_CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
4361 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->MP_CIFR & (__INTERRUPT__)) == (__INTERRUPT__))