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Searched refs:PWR_SCR_CWUF5_Pos (Results 1 – 25 of 52) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c071xx.h3940 #define PWR_SCR_CWUF5_Pos (4U) macro
3941 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g070xx.h3706 #define PWR_SCR_CWUF5_Pos (4U) macro
3707 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32g071xx.h4408 #define PWR_SCR_CWUF5_Pos (4U) macro
4409 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32g081xx.h4644 #define PWR_SCR_CWUF5_Pos (4U) macro
4645 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32g0b0xx.h4487 #define PWR_SCR_CWUF5_Pos (4U) macro
4488 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32g0c1xx.h5697 #define PWR_SCR_CWUF5_Pos (4U) macro
5698 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32g0b1xx.h5461 #define PWR_SCR_CWUF5_Pos (4U) macro
5462 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h4531 #define PWR_SCR_CWUF5_Pos (4U) macro
4532 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32u083xx.h5197 #define PWR_SCR_CWUF5_Pos (4U) macro
5198 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32u073xx.h4939 #define PWR_SCR_CWUF5_Pos (4U) macro
4940 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h6470 #define PWR_SCR_CWUF5_Pos (4U) macro
6471 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32g411xc.h6635 #define PWR_SCR_CWUF5_Pos (4U) macro
6636 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32g441xx.h6824 #define PWR_SCR_CWUF5_Pos (4U) macro
6825 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32gbk1cb.h6589 #define PWR_SCR_CWUF5_Pos (4U) macro
6590 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32g431xx.h6603 #define PWR_SCR_CWUF5_Pos (4U) macro
6604 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32g4a1xx.h6988 #define PWR_SCR_CWUF5_Pos (4U) macro
6989 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32g491xx.h6767 #define PWR_SCR_CWUF5_Pos (4U) macro
6768 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32g473xx.h7352 #define PWR_SCR_CWUF5_Pos (4U) macro
7353 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32g471xx.h6838 #define PWR_SCR_CWUF5_Pos (4U) macro
6839 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h5169 #define PWR_SCR_CWUF5_Pos (4U) macro
5170 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32l412xx.h4953 #define PWR_SCR_CWUF5_Pos (4U) macro
4954 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32l433xx.h8725 #define PWR_SCR_CWUF5_Pos (4U) macro
8726 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32l451xx.h8890 #define PWR_SCR_CWUF5_Pos (4U) macro
8891 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb55xx.h6498 #define PWR_SCR_CWUF5_Pos (4U) macro
6499 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
Dstm32wb5mxx.h6498 #define PWR_SCR_CWUF5_Pos (4U) macro
6499 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */

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