Home
last modified time | relevance | path

Searched refs:PWR_CR3_EWUP5_Pos (Results 1 – 25 of 52) sorted by relevance

123

/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c071xx.h3851 #define PWR_CR3_EWUP5_Pos (4U) macro
3852 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g070xx.h3614 #define PWR_CR3_EWUP5_Pos (4U) macro
3615 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32g071xx.h4307 #define PWR_CR3_EWUP5_Pos (4U) macro
4308 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32g081xx.h4543 #define PWR_CR3_EWUP5_Pos (4U) macro
4544 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32g0b0xx.h4386 #define PWR_CR3_EWUP5_Pos (4U) macro
4387 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32g0c1xx.h5584 #define PWR_CR3_EWUP5_Pos (4U) macro
5585 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32g0b1xx.h5348 #define PWR_CR3_EWUP5_Pos (4U) macro
5349 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h4415 #define PWR_CR3_EWUP5_Pos (4U) macro
4416 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32u083xx.h5078 #define PWR_CR3_EWUP5_Pos (4U) macro
5079 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32u073xx.h4820 #define PWR_CR3_EWUP5_Pos (4U) macro
4821 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h6369 #define PWR_CR3_EWUP5_Pos (4U) macro
6370 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32g411xc.h6534 #define PWR_CR3_EWUP5_Pos (4U) macro
6535 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32g441xx.h6723 #define PWR_CR3_EWUP5_Pos (4U) macro
6724 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32gbk1cb.h6488 #define PWR_CR3_EWUP5_Pos (4U) macro
6489 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32g431xx.h6502 #define PWR_CR3_EWUP5_Pos (4U) macro
6503 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32g4a1xx.h6887 #define PWR_CR3_EWUP5_Pos (4U) macro
6888 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32g491xx.h6666 #define PWR_CR3_EWUP5_Pos (4U) macro
6667 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32g473xx.h7251 #define PWR_CR3_EWUP5_Pos (4U) macro
7252 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32g471xx.h6737 #define PWR_CR3_EWUP5_Pos (4U) macro
6738 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h5059 #define PWR_CR3_EWUP5_Pos (4U) macro
5060 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32l412xx.h4843 #define PWR_CR3_EWUP5_Pos (4U) macro
4844 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32l433xx.h8621 #define PWR_CR3_EWUP5_Pos (4U) macro
8622 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32l451xx.h8789 #define PWR_CR3_EWUP5_Pos (4U) macro
8790 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb55xx.h6333 #define PWR_CR3_EWUP5_Pos (4U) macro
6334 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
Dstm32wb5mxx.h6333 #define PWR_CR3_EWUP5_Pos (4U) macro
6334 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */

123