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Searched refs:PWR_CR1_LPMS_Pos (Results 1 – 25 of 92) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h3529 #define PWR_CR1_LPMS_Pos (0U) macro
3530 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
3532 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
3533 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
3534 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
Dstm32c031xx.h3536 #define PWR_CR1_LPMS_Pos (0U) macro
3537 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
3539 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
3540 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
3541 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
Dstm32c071xx.h3816 #define PWR_CR1_LPMS_Pos (0U) macro
3817 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
3819 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
3820 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
3821 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g031xx.h3699 #define PWR_CR1_LPMS_Pos (0U) macro
3700 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
3702 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
3703 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
3704 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
Dstm32g041xx.h3935 #define PWR_CR1_LPMS_Pos (0U) macro
3936 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
3938 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
3939 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
3940 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
Dstm32g051xx.h4035 #define PWR_CR1_LPMS_Pos (0U) macro
4036 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
4038 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
4039 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
4040 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
Dstm32g061xx.h4271 #define PWR_CR1_LPMS_Pos (0U) macro
4272 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
4274 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
4275 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
4276 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
Dstm32g071xx.h4250 #define PWR_CR1_LPMS_Pos (0U) macro
4251 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
4253 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
4254 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
4255 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
Dstm32g081xx.h4486 #define PWR_CR1_LPMS_Pos (0U) macro
4487 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
4489 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
4490 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
4491 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
Dstm32g030xx.h3546 #define PWR_CR1_LPMS_Pos (0U) macro
3547 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
3549 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
3550 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
Dstm32g050xx.h3565 #define PWR_CR1_LPMS_Pos (0U) macro
3566 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
3568 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
3569 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
Dstm32g070xx.h3574 #define PWR_CR1_LPMS_Pos (0U) macro
3575 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
3577 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
3578 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h5302 #define PWR_CR1_LPMS_Pos (0U) macro
5303 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
5305 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
5306 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
5307 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
Dstm32wle5xx.h5302 #define PWR_CR1_LPMS_Pos (0U) macro
5303 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
5305 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
5306 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
5307 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
Dstm32wl5mxx.h6070 #define PWR_CR1_LPMS_Pos (0U) macro
6071 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
6073 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
6074 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
6075 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
Dstm32wl54xx.h6070 #define PWR_CR1_LPMS_Pos (0U) macro
6071 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
6073 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
6074 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
6075 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
Dstm32wl55xx.h6070 #define PWR_CR1_LPMS_Pos (0U) macro
6071 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
6073 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
6074 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
6075 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h5266 #define PWR_CR1_LPMS_Pos (0U) macro
5267 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007…
5269 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001…
5270 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002…
5271 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004…
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h4357 #define PWR_CR1_LPMS_Pos (0U) macro
4358 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
4360 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
4361 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
4362 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
Dstm32u083xx.h5014 #define PWR_CR1_LPMS_Pos (0U) macro
5015 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
5017 #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
5018 #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
5019 #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb50xx.h5833 #define PWR_CR1_LPMS_Pos (0U) macro
5834 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
5836 #define PWR_CR1_LPMS_0 (0x1U << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
5837 #define PWR_CR1_LPMS_1 (0x2U << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
5838 #define PWR_CR1_LPMS_2 (0x4U << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
Dstm32wb1mxx.h5490 #define PWR_CR1_LPMS_Pos (0U) macro
5491 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
5493 #define PWR_CR1_LPMS_0 (0x1U << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
5494 #define PWR_CR1_LPMS_1 (0x2U << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
5495 #define PWR_CR1_LPMS_2 (0x4U << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
Dstm32wb30xx.h5832 #define PWR_CR1_LPMS_Pos (0U) macro
5833 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
5835 #define PWR_CR1_LPMS_0 (0x1U << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
5836 #define PWR_CR1_LPMS_1 (0x2U << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
5837 #define PWR_CR1_LPMS_2 (0x4U << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h5394 #define PWR_CR1_LPMS_Pos (0U) macro
5395 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
5397 #define PWR_CR1_LPMS_0 (0x1U << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
5398 #define PWR_CR1_LPMS_1 (0x2U << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
5399 #define PWR_CR1_LPMS_2 (0x4U << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
Dstm32wb15xx.h5490 #define PWR_CR1_LPMS_Pos (0U) macro
5491 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
5493 #define PWR_CR1_LPMS_0 (0x1U << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
5494 #define PWR_CR1_LPMS_1 (0x2U << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
5495 #define PWR_CR1_LPMS_2 (0x4U << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */

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