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Searched refs:OCNState (Results 1 – 25 of 44) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_ll_tim.c356 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
809 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
817 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
888 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
896 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
967 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
975 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1047 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC4Config()
1054 MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U); in OC4Config()
1097 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_tim.c397 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
850 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
858 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
929 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
937 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
1008 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
1016 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1088 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC4Config()
1095 MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U); in OC4Config()
1138 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_tim.c393 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
846 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
854 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
925 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
933 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
1004 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
1012 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1084 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC4Config()
1091 MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U); in OC4Config()
1134 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_tim.c434 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
887 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
895 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
966 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
974 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
1045 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
1053 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1125 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC4Config()
1132 MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U); in OC4Config()
1175 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_tim.c391 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
844 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
852 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
923 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
931 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
1002 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
1010 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1082 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC4Config()
1089 MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U); in OC4Config()
1132 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_tim.c428 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
881 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
889 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
960 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
968 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
1039 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
1047 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1119 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC4Config()
1126 MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U); in OC4Config()
1169 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_ll_tim.c339 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
765 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
801 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
844 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
880 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
923 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
959 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1003 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC4Config()
1072 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
1133 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_ll_tim.c415 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
835 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
871 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
914 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
950 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
993 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
1029 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1073 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC4Config()
1142 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
1203 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/src/
Dstm32wb0x_ll_tim.c350 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
715 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
724 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
796 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
804 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
877 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
885 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
999 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
1062 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_tim.c407 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
854 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
862 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
933 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
941 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
1012 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
1020 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1130 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
1191 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/src/
Dstm32u0xx_ll_tim.c360 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
813 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
821 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
892 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
900 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
971 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
979 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1089 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
1150 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/src/
Dstm32c0xx_ll_tim.c351 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
804 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
812 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
883 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
891 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
962 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
970 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1080 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
1141 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/src/
Dstm32wbxx_ll_tim.c343 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
796 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
804 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
875 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
883 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
954 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
962 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1072 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
1133 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_tim.c374 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
827 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
835 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
906 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
914 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
985 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
993 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1103 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
1164 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_tim.c380 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
827 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
835 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
906 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
914 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
985 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
993 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1103 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
1164 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/src/
Dstm32g0xx_ll_tim.c383 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
836 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
844 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
915 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
923 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
994 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
1002 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1112 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
1173 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_tim.c451 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
915 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
923 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
994 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
1002 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
1076 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
1084 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1202 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
1266 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_tim.c419 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
884 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
892 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
963 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
971 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
1042 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
1050 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1160 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC5Config()
1221 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_ll_tim.c361 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
779 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
787 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
858 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
866 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
937 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
945 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_tim.c361 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
779 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
787 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
858 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
866 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
937 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
945 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/src/
Dstm32f0xx_ll_tim.c340 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
758 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
766 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
837 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
845 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
916 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
924 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_ll_tim.c381 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
797 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC1Config()
805 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
876 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC2Config()
884 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
955 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); in OC3Config()
963 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_ll_tim.h240 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. member
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_tim.h243 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. member
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_tim.h237 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. member

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