1 /**
2 ******************************************************************************
3 * @file stm32n6xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32n6xx_ll_tim.h"
22 #include "stm32n6xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32N6xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) \
35 || defined (TIM2) \
36 || defined (TIM3) \
37 || defined (TIM4) \
38 || defined (TIM5) \
39 || defined (TIM6) \
40 || defined (TIM7) \
41 || defined (TIM8) \
42 || defined (TIM9) \
43 || defined (TIM10) \
44 || defined (TIM11) \
45 || defined (TIM12) \
46 || defined (TIM13) \
47 || defined (TIM14) \
48 || defined (TIM15) \
49 || defined (TIM16) \
50 || defined (TIM17) \
51 || defined (TIM18)
52
53 /** @addtogroup TIM_LL
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /* Private constants ---------------------------------------------------------*/
60 /* Private macros ------------------------------------------------------------*/
61 /** @addtogroup TIM_LL_Private_Macros
62 * @{
63 */
64 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
65 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
66 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
67 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
68 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
69
70 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
71 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
72 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
73
74 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
75 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
76 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
77 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
78 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
79 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
80 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
81 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
82 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
83 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
84 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
85 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
86 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
87 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2) \
88 || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \
89 || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT))
90
91 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
92 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
93
94 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
95 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
96
97 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
98 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
99
100 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
101 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
102 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
103
104 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
105 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
106 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
107 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
108
109 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
110 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
111 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
112 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
113 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
114 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
115 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
116 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
117 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
118 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
119 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
120 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
121 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
122 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
123 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
124 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
125
126 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
127 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
128 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
129
130 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
131 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
132 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12) \
133 || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) \
134 || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) \
135 || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) \
136 || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) \
137 || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI1) \
138 || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI2))
139
140 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
141 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
142
143 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
144 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
145
146 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
147 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
148
149 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
150 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
151 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
152 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
153
154 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
155 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
156
157 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
158 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
159
160 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
161 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
162 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
163 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
164 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
165 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
166 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
167 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
168 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
169 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
170 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
171 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
172 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
173 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
174 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
175 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
176
177 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
178 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
179
180 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
181 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
182
183 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
184 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
185
186 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
187 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
188 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
189 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
190 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
191 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
192 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
193 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
194 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
195 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
196 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
197 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
198 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
199 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
200 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
201 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
202
203 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
204 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
205
206 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
207 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
208 /**
209 * @}
210 */
211
212
213 /* Private function prototypes -----------------------------------------------*/
214 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
215 * @{
216 */
217 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
218 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
219 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
220 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
221 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
222 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
223 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
224 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
225 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
226 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
227 /**
228 * @}
229 */
230
231 /* Exported functions --------------------------------------------------------*/
232 /** @addtogroup TIM_LL_Exported_Functions
233 * @{
234 */
235
236 /** @addtogroup TIM_LL_EF_Init
237 * @{
238 */
239
240 /**
241 * @brief Set TIMx registers to their reset values.
242 * @param TIMx Timer instance
243 * @retval An ErrorStatus enumeration value:
244 * - SUCCESS: TIMx registers are de-initialized
245 * - ERROR: invalid TIMx instance
246 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)247 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
248 {
249 ErrorStatus result = SUCCESS;
250
251 /* Check the parameters */
252 assert_param(IS_TIM_INSTANCE(TIMx));
253
254 if (TIMx == TIM1)
255 {
256 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
257 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
258 }
259 else if (TIMx == TIM2)
260 {
261 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
262 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
263 }
264 else if (TIMx == TIM3)
265 {
266 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
267 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
268 }
269 else if (TIMx == TIM4)
270 {
271 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
272 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
273 }
274 else if (TIMx == TIM5)
275 {
276 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
277 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
278 }
279 else if (TIMx == TIM6)
280 {
281 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
282 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
283 }
284 else if (TIMx == TIM7)
285 {
286 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
287 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
288 }
289 else if (TIMx == TIM8)
290 {
291 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
292 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
293 }
294 else if (TIMx == TIM9)
295 {
296 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
297 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
298 }
299 else if (TIMx == TIM10)
300 {
301 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM10);
302 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM10);
303 }
304 else if (TIMx == TIM11)
305 {
306 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM11);
307 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM11);
308 }
309 else if (TIMx == TIM12)
310 {
311 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
312 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
313 }
314 else if (TIMx == TIM13)
315 {
316 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
317 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
318 }
319 else if (TIMx == TIM14)
320 {
321 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
322 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
323 }
324 else if (TIMx == TIM15)
325 {
326 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
327 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
328 }
329 else if (TIMx == TIM16)
330 {
331 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
332 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
333 }
334 else if (TIMx == TIM17)
335 {
336 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
337 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
338 }
339 else if (TIMx == TIM18)
340 {
341 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM18);
342 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM18);
343 }
344 else
345 {
346 result = ERROR;
347 }
348
349 return result;
350 }
351
352 /**
353 * @brief Set the fields of the time base unit configuration data structure
354 * to their default values.
355 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
356 * @retval None
357 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)358 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
359 {
360 /* Set the default configuration */
361 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
362 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
363 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
364 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
365 TIM_InitStruct->RepetitionCounter = 0x00000000U;
366 }
367
368 /**
369 * @brief Configure the TIMx time base unit.
370 * @param TIMx Timer Instance
371 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
372 * (TIMx time base unit configuration data structure)
373 * @retval An ErrorStatus enumeration value:
374 * - SUCCESS: TIMx registers are de-initialized
375 * - ERROR: not applicable
376 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)377 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
378 {
379 uint32_t tmpcr1;
380
381 /* Check the parameters */
382 assert_param(IS_TIM_INSTANCE(TIMx));
383 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
384 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
385
386 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
387
388 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
389 {
390 /* Select the Counter Mode */
391 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
392 }
393
394 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
395 {
396 /* Set the clock division */
397 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
398 }
399
400 /* Write to TIMx CR1 */
401 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
402
403 /* Set the Autoreload value */
404 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
405
406 /* Set the Prescaler value */
407 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
408
409 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
410 {
411 /* Set the Repetition Counter value */
412 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
413 }
414
415 /* Generate an update event to reload the Prescaler
416 and the repetition counter value (if applicable) immediately */
417 LL_TIM_GenerateEvent_UPDATE(TIMx);
418
419 return SUCCESS;
420 }
421
422 /**
423 * @brief Set the fields of the TIMx output channel configuration data
424 * structure to their default values.
425 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
426 * (the output channel configuration data structure)
427 * @retval None
428 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)429 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
430 {
431 /* Set the default configuration */
432 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
433 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
434 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
435 TIM_OC_InitStruct->CompareValue = 0x00000000U;
436 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
437 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
438 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
439 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
440 }
441
442 /**
443 * @brief Configure the TIMx output channel.
444 * @param TIMx Timer Instance
445 * @param Channel This parameter can be one of the following values:
446 * @arg @ref LL_TIM_CHANNEL_CH1
447 * @arg @ref LL_TIM_CHANNEL_CH2
448 * @arg @ref LL_TIM_CHANNEL_CH3
449 * @arg @ref LL_TIM_CHANNEL_CH4
450 * @arg @ref LL_TIM_CHANNEL_CH5
451 * @arg @ref LL_TIM_CHANNEL_CH6
452 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
453 * data structure)
454 * @retval An ErrorStatus enumeration value:
455 * - SUCCESS: TIMx output channel is initialized
456 * - ERROR: TIMx output channel is not initialized
457 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)458 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
459 {
460 ErrorStatus result = ERROR;
461
462 switch (Channel)
463 {
464 case LL_TIM_CHANNEL_CH1:
465 result = OC1Config(TIMx, TIM_OC_InitStruct);
466 break;
467 case LL_TIM_CHANNEL_CH2:
468 result = OC2Config(TIMx, TIM_OC_InitStruct);
469 break;
470 case LL_TIM_CHANNEL_CH3:
471 result = OC3Config(TIMx, TIM_OC_InitStruct);
472 break;
473 case LL_TIM_CHANNEL_CH4:
474 result = OC4Config(TIMx, TIM_OC_InitStruct);
475 break;
476 case LL_TIM_CHANNEL_CH5:
477 result = OC5Config(TIMx, TIM_OC_InitStruct);
478 break;
479 case LL_TIM_CHANNEL_CH6:
480 result = OC6Config(TIMx, TIM_OC_InitStruct);
481 break;
482 default:
483 break;
484 }
485
486 return result;
487 }
488
489 /**
490 * @brief Set the fields of the TIMx input channel configuration data
491 * structure to their default values.
492 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
493 * data structure)
494 * @retval None
495 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)496 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
497 {
498 /* Set the default configuration */
499 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
500 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
501 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
502 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
503 }
504
505 /**
506 * @brief Configure the TIMx input channel.
507 * @param TIMx Timer Instance
508 * @param Channel This parameter can be one of the following values:
509 * @arg @ref LL_TIM_CHANNEL_CH1
510 * @arg @ref LL_TIM_CHANNEL_CH2
511 * @arg @ref LL_TIM_CHANNEL_CH3
512 * @arg @ref LL_TIM_CHANNEL_CH4
513 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
514 * structure)
515 * @retval An ErrorStatus enumeration value:
516 * - SUCCESS: TIMx output channel is initialized
517 * - ERROR: TIMx output channel is not initialized
518 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)519 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
520 {
521 ErrorStatus result = ERROR;
522
523 switch (Channel)
524 {
525 case LL_TIM_CHANNEL_CH1:
526 result = IC1Config(TIMx, TIM_IC_InitStruct);
527 break;
528 case LL_TIM_CHANNEL_CH2:
529 result = IC2Config(TIMx, TIM_IC_InitStruct);
530 break;
531 case LL_TIM_CHANNEL_CH3:
532 result = IC3Config(TIMx, TIM_IC_InitStruct);
533 break;
534 case LL_TIM_CHANNEL_CH4:
535 result = IC4Config(TIMx, TIM_IC_InitStruct);
536 break;
537 default:
538 break;
539 }
540
541 return result;
542 }
543
544 /**
545 * @brief Fills each TIM_EncoderInitStruct field with its default value
546 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
547 * configuration data structure)
548 * @retval None
549 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)550 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
551 {
552 /* Set the default configuration */
553 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
554 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
555 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
556 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
557 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
558 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
559 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
560 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
561 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
562 }
563
564 /**
565 * @brief Configure the encoder interface of the timer instance.
566 * @param TIMx Timer Instance
567 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
568 * configuration data structure)
569 * @retval An ErrorStatus enumeration value:
570 * - SUCCESS: TIMx registers are de-initialized
571 * - ERROR: not applicable
572 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)573 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
574 {
575 uint32_t tmpccmr1;
576 uint32_t tmpccer;
577
578 /* Check the parameters */
579 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
580 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
581 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
582 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
583 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
584 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
585 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
586 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
587 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
588 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
589
590 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
591 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
592
593 /* Get the TIMx CCMR1 register value */
594 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
595
596 /* Get the TIMx CCER register value */
597 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
598
599 /* Configure TI1 */
600 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
601 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
602 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
603 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
604
605 /* Configure TI2 */
606 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
607 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
608 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
609 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
610
611 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
612 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
613 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
614 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
615 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
616
617 /* Set encoder mode */
618 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
619
620 /* Write to TIMx CCMR1 */
621 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
622
623 /* Write to TIMx CCER */
624 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
625
626 return SUCCESS;
627 }
628
629 /**
630 * @brief Set the fields of the TIMx Hall sensor interface configuration data
631 * structure to their default values.
632 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
633 * configuration data structure)
634 * @retval None
635 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)636 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
637 {
638 /* Set the default configuration */
639 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
640 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
641 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
642 TIM_HallSensorInitStruct->CommutationDelay = 0U;
643 }
644
645 /**
646 * @brief Configure the Hall sensor interface of the timer instance.
647 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
648 * to the TI1 input channel
649 * @note TIMx slave mode controller is configured in reset mode.
650 Selected internal trigger is TI1F_ED.
651 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
652 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
653 * between 2 changes on the inputs. It gives information about motor speed.
654 * @note Channel 2 is configured in output PWM 2 mode.
655 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
656 * @note OC2REF is selected as trigger output on TRGO.
657 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
658 * when TIMx operates in Hall sensor interface mode.
659 * @param TIMx Timer Instance
660 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
661 * interface configuration data structure)
662 * @retval An ErrorStatus enumeration value:
663 * - SUCCESS: TIMx registers are de-initialized
664 * - ERROR: not applicable
665 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)666 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
667 {
668 uint32_t tmpcr2;
669 uint32_t tmpccmr1;
670 uint32_t tmpccer;
671 uint32_t tmpsmcr;
672
673 /* Check the parameters */
674 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
675 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
676 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
677 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
678
679 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
680 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
681
682 /* Get the TIMx CR2 register value */
683 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
684
685 /* Get the TIMx CCMR1 register value */
686 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
687
688 /* Get the TIMx CCER register value */
689 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
690
691 /* Get the TIMx SMCR register value */
692 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
693
694 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
695 tmpcr2 |= TIM_CR2_TI1S;
696
697 /* OC2REF signal is used as trigger output (TRGO) */
698 tmpcr2 |= LL_TIM_TRGO_OC2REF;
699
700 /* Configure the slave mode controller */
701 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
702 tmpsmcr |= LL_TIM_TS_TI1F_ED;
703 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
704
705 /* Configure input channel 1 */
706 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
707 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
708 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
709 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
710
711 /* Configure input channel 2 */
712 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
713 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
714
715 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
716 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
717 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
718 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
719
720 /* Write to TIMx CR2 */
721 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
722
723 /* Write to TIMx SMCR */
724 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
725
726 /* Write to TIMx CCMR1 */
727 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
728
729 /* Write to TIMx CCER */
730 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
731
732 /* Write to TIMx CCR2 */
733 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
734
735 return SUCCESS;
736 }
737
738 /**
739 * @brief Set the fields of the Break and Dead Time configuration data structure
740 * to their default values.
741 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
742 * data structure)
743 * @retval None
744 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)745 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
746 {
747 /* Set the default configuration */
748 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
749 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
750 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
751 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
752 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
753 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
754 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
755 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
756 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
757 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
758 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
759 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
760 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
761 }
762
763 /**
764 * @brief Configure the Break and Dead Time feature of the timer instance.
765 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
766 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
767 * can be necessary to configure all of them during the first write access to
768 * the TIMx_BDTR register.
769 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
770 * a timer instance provides a break input.
771 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
772 * a timer instance provides a second break input.
773 * @param TIMx Timer Instance
774 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
775 * data structure)
776 * @retval An ErrorStatus enumeration value:
777 * - SUCCESS: Break and Dead Time is initialized
778 * - ERROR: not applicable
779 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)780 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
781 {
782 uint32_t tmpbdtr = 0;
783
784 /* Check the parameters */
785 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
786 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
787 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
788 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
789 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
790 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
791 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
792 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
793 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
794
795 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
796 the OSSI State, the dead time value and the Automatic Output Enable Bit */
797
798 /* Set the BDTR bits */
799 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
800 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
801 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
802 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
803 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
804 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
805 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
806 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
807 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
808
809 if (IS_TIM_BKIN2_INSTANCE(TIMx))
810 {
811 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
812 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
813 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
814 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
815
816 /* Set the BREAK2 input related BDTR bit-fields */
817 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
818 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
819 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
820 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
821 }
822
823 /* Set TIMx_BDTR */
824 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
825
826 return SUCCESS;
827 }
828 /**
829 * @}
830 */
831
832 /**
833 * @}
834 */
835
836 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
837 * @brief Private functions
838 * @{
839 */
840 /**
841 * @brief Configure the TIMx output channel 1.
842 * @param TIMx Timer Instance
843 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
844 * @retval An ErrorStatus enumeration value:
845 * - SUCCESS: TIMx registers are de-initialized
846 * - ERROR: not applicable
847 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)848 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
849 {
850 uint32_t tmpccmr1;
851 uint32_t tmpccer;
852 uint32_t tmpcr2;
853
854 /* Check the parameters */
855 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
856 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
857 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
858 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
859
860 /* Disable the Channel 1: Reset the CC1E Bit */
861 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
862
863 /* Get the TIMx CCER register value */
864 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
865
866 /* Get the TIMx CR2 register value */
867 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
868
869 /* Get the TIMx CCMR1 register value */
870 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
871
872 /* Reset Capture/Compare selection Bits */
873 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
874
875 /* Set the Output Compare Mode */
876 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
877
878 /* Set the Output Compare Polarity */
879 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
880
881 /* Set the Output State */
882 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
883
884 if (IS_TIM_BREAK_INSTANCE(TIMx))
885 {
886 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
887 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
888 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
889 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
890
891 /* Set the complementary output Polarity */
892 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
893
894 /* Set the complementary output State */
895 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
896
897 /* Set the Output Idle state */
898 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
899
900 /* Set the complementary output Idle state */
901 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
902 }
903
904 /* Write to TIMx CR2 */
905 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
906
907 /* Write to TIMx CCMR1 */
908 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
909
910 /* Set the Capture Compare Register value */
911 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
912
913 /* Write to TIMx CCER */
914 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
915
916 return SUCCESS;
917 }
918
919 /**
920 * @brief Configure the TIMx output channel 2.
921 * @param TIMx Timer Instance
922 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
923 * @retval An ErrorStatus enumeration value:
924 * - SUCCESS: TIMx registers are de-initialized
925 * - ERROR: not applicable
926 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)927 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
928 {
929 uint32_t tmpccmr1;
930 uint32_t tmpccer;
931 uint32_t tmpcr2;
932
933 /* Check the parameters */
934 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
935 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
936 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
937 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
938
939 /* Disable the Channel 2: Reset the CC2E Bit */
940 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
941
942 /* Get the TIMx CCER register value */
943 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
944
945 /* Get the TIMx CR2 register value */
946 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
947
948 /* Get the TIMx CCMR1 register value */
949 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
950
951 /* Reset Capture/Compare selection Bits */
952 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
953
954 /* Select the Output Compare Mode */
955 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
956
957 /* Set the Output Compare Polarity */
958 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
959
960 /* Set the Output State */
961 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
962
963 if (IS_TIM_BREAK_INSTANCE(TIMx))
964 {
965 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
966 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
967 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
968 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
969
970 /* Set the complementary output Polarity */
971 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
972
973 /* Set the complementary output State */
974 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
975
976 /* Set the Output Idle state */
977 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
978
979 /* Set the complementary output Idle state */
980 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
981 }
982
983 /* Write to TIMx CR2 */
984 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
985
986 /* Write to TIMx CCMR1 */
987 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
988
989 /* Set the Capture Compare Register value */
990 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
991
992 /* Write to TIMx CCER */
993 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
994
995 return SUCCESS;
996 }
997
998 /**
999 * @brief Configure the TIMx output channel 3.
1000 * @param TIMx Timer Instance
1001 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
1002 * @retval An ErrorStatus enumeration value:
1003 * - SUCCESS: TIMx registers are de-initialized
1004 * - ERROR: not applicable
1005 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1006 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1007 {
1008 uint32_t tmpccmr2;
1009 uint32_t tmpccer;
1010 uint32_t tmpcr2;
1011
1012 /* Check the parameters */
1013 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1014 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1015 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1016 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1017
1018 /* Disable the Channel 3: Reset the CC3E Bit */
1019 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
1020
1021 /* Get the TIMx CCER register value */
1022 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1023
1024 /* Get the TIMx CR2 register value */
1025 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1026
1027 /* Get the TIMx CCMR2 register value */
1028 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1029
1030 /* Reset Capture/Compare selection Bits */
1031 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
1032
1033 /* Select the Output Compare Mode */
1034 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
1035
1036 /* Set the Output Compare Polarity */
1037 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
1038
1039 /* Set the Output State */
1040 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
1041
1042 if (IS_TIM_BREAK_INSTANCE(TIMx))
1043 {
1044 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1045 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1046 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1047 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1048
1049 /* Set the complementary output Polarity */
1050 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1051
1052 /* Set the complementary output State */
1053 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1054
1055 /* Set the Output Idle state */
1056 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1057
1058 /* Set the complementary output Idle state */
1059 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1060 }
1061
1062 /* Write to TIMx CR2 */
1063 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1064
1065 /* Write to TIMx CCMR2 */
1066 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1067
1068 /* Set the Capture Compare Register value */
1069 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1070
1071 /* Write to TIMx CCER */
1072 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1073
1074 return SUCCESS;
1075 }
1076
1077 /**
1078 * @brief Configure the TIMx output channel 4.
1079 * @param TIMx Timer Instance
1080 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1081 * @retval An ErrorStatus enumeration value:
1082 * - SUCCESS: TIMx registers are de-initialized
1083 * - ERROR: not applicable
1084 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1085 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1086 {
1087 uint32_t tmpccmr2;
1088 uint32_t tmpccer;
1089 uint32_t tmpcr2;
1090
1091 /* Check the parameters */
1092 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1093 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1094 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1095 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1096
1097 /* Disable the Channel 4: Reset the CC4E Bit */
1098 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1099
1100 /* Get the TIMx CCER register value */
1101 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1102
1103 /* Get the TIMx CR2 register value */
1104 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1105
1106 /* Get the TIMx CCMR2 register value */
1107 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1108
1109 /* Reset Capture/Compare selection Bits */
1110 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1111
1112 /* Select the Output Compare Mode */
1113 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1114
1115 /* Set the Output Compare Polarity */
1116 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1117
1118 /* Set the Output State */
1119 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1120
1121 if (IS_TIM_BREAK_INSTANCE(TIMx))
1122 {
1123 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1124 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1125 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1126 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1127
1128 /* Set the complementary output Polarity */
1129 MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U);
1130
1131 /* Set the complementary output State */
1132 MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U);
1133
1134 /* Set the Output Idle state */
1135 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1136
1137 /* Set the complementary output Idle state */
1138 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);
1139 }
1140
1141 /* Write to TIMx CR2 */
1142 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1143
1144 /* Write to TIMx CCMR2 */
1145 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1146
1147 /* Set the Capture Compare Register value */
1148 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1149
1150 /* Write to TIMx CCER */
1151 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1152
1153 return SUCCESS;
1154 }
1155
1156 /**
1157 * @brief Configure the TIMx output channel 5.
1158 * @param TIMx Timer Instance
1159 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1160 * @retval An ErrorStatus enumeration value:
1161 * - SUCCESS: TIMx registers are de-initialized
1162 * - ERROR: not applicable
1163 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1164 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1165 {
1166 uint32_t tmpccmr3;
1167 uint32_t tmpccer;
1168
1169 /* Check the parameters */
1170 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1171 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1172 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1173 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1174 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1175 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1176
1177 /* Disable the Channel 5: Reset the CC5E Bit */
1178 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1179
1180 /* Get the TIMx CCER register value */
1181 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1182
1183 /* Get the TIMx CCMR3 register value */
1184 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1185
1186 /* Select the Output Compare Mode */
1187 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1188
1189 /* Set the Output Compare Polarity */
1190 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1191
1192 /* Set the Output State */
1193 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1194
1195 if (IS_TIM_BREAK_INSTANCE(TIMx))
1196 {
1197 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1198 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1199
1200 /* Set the Output Idle state */
1201 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1202
1203 }
1204
1205 /* Write to TIMx CCMR3 */
1206 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1207
1208 /* Set the Capture Compare Register value */
1209 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1210
1211 /* Write to TIMx CCER */
1212 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1213
1214 return SUCCESS;
1215 }
1216
1217 /**
1218 * @brief Configure the TIMx output channel 6.
1219 * @param TIMx Timer Instance
1220 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1221 * @retval An ErrorStatus enumeration value:
1222 * - SUCCESS: TIMx registers are de-initialized
1223 * - ERROR: not applicable
1224 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1225 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1226 {
1227 uint32_t tmpccmr3;
1228 uint32_t tmpccer;
1229
1230 /* Check the parameters */
1231 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1232 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1233 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1234 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1235 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1236 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1237
1238 /* Disable the Channel 5: Reset the CC6E Bit */
1239 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1240
1241 /* Get the TIMx CCER register value */
1242 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1243
1244 /* Get the TIMx CCMR3 register value */
1245 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1246
1247 /* Select the Output Compare Mode */
1248 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1249
1250 /* Set the Output Compare Polarity */
1251 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1252
1253 /* Set the Output State */
1254 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1255
1256 if (IS_TIM_BREAK_INSTANCE(TIMx))
1257 {
1258 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1259 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1260
1261 /* Set the Output Idle state */
1262 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1263 }
1264
1265 /* Write to TIMx CCMR3 */
1266 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1267
1268 /* Set the Capture Compare Register value */
1269 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1270
1271 /* Write to TIMx CCER */
1272 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1273
1274 return SUCCESS;
1275 }
1276
1277 /**
1278 * @brief Configure the TIMx input channel 1.
1279 * @param TIMx Timer Instance
1280 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1281 * @retval An ErrorStatus enumeration value:
1282 * - SUCCESS: TIMx registers are de-initialized
1283 * - ERROR: not applicable
1284 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1285 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1286 {
1287 /* Check the parameters */
1288 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1289 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1290 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1291 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1292 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1293
1294 /* Disable the Channel 1: Reset the CC1E Bit */
1295 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1296
1297 /* Select the Input and set the filter and the prescaler value */
1298 MODIFY_REG(TIMx->CCMR1,
1299 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1300 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1301
1302 /* Select the Polarity and set the CC1E Bit */
1303 MODIFY_REG(TIMx->CCER,
1304 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1305 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1306
1307 return SUCCESS;
1308 }
1309
1310 /**
1311 * @brief Configure the TIMx input channel 2.
1312 * @param TIMx Timer Instance
1313 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1314 * @retval An ErrorStatus enumeration value:
1315 * - SUCCESS: TIMx registers are de-initialized
1316 * - ERROR: not applicable
1317 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1318 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1319 {
1320 /* Check the parameters */
1321 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1322 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1323 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1324 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1325 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1326
1327 /* Disable the Channel 2: Reset the CC2E Bit */
1328 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1329
1330 /* Select the Input and set the filter and the prescaler value */
1331 MODIFY_REG(TIMx->CCMR1,
1332 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1333 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1334
1335 /* Select the Polarity and set the CC2E Bit */
1336 MODIFY_REG(TIMx->CCER,
1337 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1338 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1339
1340 return SUCCESS;
1341 }
1342
1343 /**
1344 * @brief Configure the TIMx input channel 3.
1345 * @param TIMx Timer Instance
1346 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1347 * @retval An ErrorStatus enumeration value:
1348 * - SUCCESS: TIMx registers are de-initialized
1349 * - ERROR: not applicable
1350 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1351 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1352 {
1353 /* Check the parameters */
1354 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1355 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1356 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1357 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1358 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1359
1360 /* Disable the Channel 3: Reset the CC3E Bit */
1361 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1362
1363 /* Select the Input and set the filter and the prescaler value */
1364 MODIFY_REG(TIMx->CCMR2,
1365 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1366 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1367
1368 /* Select the Polarity and set the CC3E Bit */
1369 MODIFY_REG(TIMx->CCER,
1370 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1371 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1372
1373 return SUCCESS;
1374 }
1375
1376 /**
1377 * @brief Configure the TIMx input channel 4.
1378 * @param TIMx Timer Instance
1379 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1380 * @retval An ErrorStatus enumeration value:
1381 * - SUCCESS: TIMx registers are de-initialized
1382 * - ERROR: not applicable
1383 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1384 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1385 {
1386 /* Check the parameters */
1387 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1388 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1389 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1390 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1391 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1392
1393 /* Disable the Channel 4: Reset the CC4E Bit */
1394 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1395
1396 /* Select the Input and set the filter and the prescaler value */
1397 MODIFY_REG(TIMx->CCMR2,
1398 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1399 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1400
1401 /* Select the Polarity and set the CC4E Bit */
1402 MODIFY_REG(TIMx->CCER,
1403 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1404 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1405
1406 return SUCCESS;
1407 }
1408
1409
1410 /**
1411 * @}
1412 */
1413
1414 /**
1415 * @}
1416 */
1417
1418 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 */
1419
1420 /**
1421 * @}
1422 */
1423
1424 #endif /* USE_FULL_LL_DRIVER */
1425
1426
