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Searched refs:CORDIC_CSR_DMAWEN (Results 1 – 25 of 48) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_cordic.h643 SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN); in LL_CORDIC_EnableDMAReq_WR()
654 CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN); in LL_CORDIC_DisableDMAReq_WR()
665 return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN) == (CORDIC_CSR_DMAWEN)) ? 1U : 0U); in LL_CORDIC_IsEnabledDMAReq_WR()
Dstm32h5xx_hal_cordic.h260 #define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_cordic.h643 SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN); in LL_CORDIC_EnableDMAReq_WR()
654 CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN); in LL_CORDIC_DisableDMAReq_WR()
665 return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN) == (CORDIC_CSR_DMAWEN)) ? 1U : 0U); in LL_CORDIC_IsEnabledDMAReq_WR()
Dstm32u5xx_hal_cordic.h260 #define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_cordic.h643 SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN); in LL_CORDIC_EnableDMAReq_WR()
654 CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN); in LL_CORDIC_DisableDMAReq_WR()
665 return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN) == (CORDIC_CSR_DMAWEN)) ? 1U : 0U); in LL_CORDIC_IsEnabledDMAReq_WR()
Dstm32h7xx_hal_cordic.h260 #define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_cordic.h643 SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN); in LL_CORDIC_EnableDMAReq_WR()
654 CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN); in LL_CORDIC_DisableDMAReq_WR()
665 return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN) == (CORDIC_CSR_DMAWEN)) ? 1U : 0U); in LL_CORDIC_IsEnabledDMAReq_WR()
Dstm32h7rsxx_hal_cordic.h260 #define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_cordic.h643 SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN); in LL_CORDIC_EnableDMAReq_WR()
654 CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN); in LL_CORDIC_DisableDMAReq_WR()
665 return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN) == (CORDIC_CSR_DMAWEN)) ? 1U : 0U); in LL_CORDIC_IsEnabledDMAReq_WR()
Dstm32g4xx_hal_cordic.h260 #define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h2162 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write chann… macro
Dstm32g411xc.h2199 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write chann… macro
Dstm32g441xx.h2507 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write chann… macro
Dstm32gbk1cb.h2272 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write chann… macro
Dstm32g431xx.h2286 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write chann… macro
Dstm32g4a1xx.h2587 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write chann… macro
Dstm32g491xx.h2366 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write chann… macro
Dstm32g473xx.h2455 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write chann… macro
Dstm32g471xx.h2377 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write chann… macro
Dstm32g483xx.h2676 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write chann… macro
Dstm32g414xx.h2561 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write chann… macro
Dstm32g474xx.h2585 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write chann… macro
Dstm32g484xx.h2806 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write chann… macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h4713 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write … macro
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h3792 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write … macro

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