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Searched refs:COMP_CSR_COMP1INSEL_Pos (Results 1 – 9 of 9) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h1130 #define COMP_CSR_COMP1INSEL_Pos (4U) macro
1131 #define COMP_CSR_COMP1INSEL_Msk (0x7UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */
1133 #define COMP_CSR_COMP1INSEL_0 (0x1UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */
1134 #define COMP_CSR_COMP1INSEL_1 (0x2UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */
1135 #define COMP_CSR_COMP1INSEL_2 (0x4UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */
Dstm32f051x8.h1131 #define COMP_CSR_COMP1INSEL_Pos (4U) macro
1132 #define COMP_CSR_COMP1INSEL_Msk (0x7UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */
1134 #define COMP_CSR_COMP1INSEL_0 (0x1UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */
1135 #define COMP_CSR_COMP1INSEL_1 (0x2UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */
1136 #define COMP_CSR_COMP1INSEL_2 (0x4UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */
Dstm32f071xb.h1165 #define COMP_CSR_COMP1INSEL_Pos (4U) macro
1166 #define COMP_CSR_COMP1INSEL_Msk (0x7UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */
1168 #define COMP_CSR_COMP1INSEL_0 (0x1UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */
1169 #define COMP_CSR_COMP1INSEL_1 (0x2UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */
1170 #define COMP_CSR_COMP1INSEL_2 (0x4UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */
Dstm32f072xb.h4924 #define COMP_CSR_COMP1INSEL_Pos (4U) macro
4925 #define COMP_CSR_COMP1INSEL_Msk (0x7UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */
4927 #define COMP_CSR_COMP1INSEL_0 (0x1UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */
4928 #define COMP_CSR_COMP1INSEL_1 (0x2UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */
4929 #define COMP_CSR_COMP1INSEL_2 (0x4UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */
Dstm32f091xc.h4906 #define COMP_CSR_COMP1INSEL_Pos (4U) macro
4907 #define COMP_CSR_COMP1INSEL_Msk (0x7UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */
4909 #define COMP_CSR_COMP1INSEL_0 (0x1UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */
4910 #define COMP_CSR_COMP1INSEL_1 (0x2UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */
4911 #define COMP_CSR_COMP1INSEL_2 (0x4UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */
Dstm32f098xx.h4906 #define COMP_CSR_COMP1INSEL_Pos (4U) macro
4907 #define COMP_CSR_COMP1INSEL_Msk (0x7UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */
4909 #define COMP_CSR_COMP1INSEL_0 (0x1UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */
4910 #define COMP_CSR_COMP1INSEL_1 (0x2UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */
4911 #define COMP_CSR_COMP1INSEL_2 (0x4UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */
Dstm32f078xx.h4924 #define COMP_CSR_COMP1INSEL_Pos (4U) macro
4925 #define COMP_CSR_COMP1INSEL_Msk (0x7UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */
4927 #define COMP_CSR_COMP1INSEL_0 (0x1UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */
4928 #define COMP_CSR_COMP1INSEL_1 (0x2UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */
4929 #define COMP_CSR_COMP1INSEL_2 (0x4UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f378xx.h1363 #define COMP_CSR_COMP1INSEL_Pos (4U) macro
1364 #define COMP_CSR_COMP1INSEL_Msk (0x7UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */
1366 #define COMP_CSR_COMP1INSEL_0 (0x1UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */
1367 #define COMP_CSR_COMP1INSEL_1 (0x2UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */
1368 #define COMP_CSR_COMP1INSEL_2 (0x4UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */
Dstm32f373xc.h1404 #define COMP_CSR_COMP1INSEL_Pos (4U) macro
1405 #define COMP_CSR_COMP1INSEL_Msk (0x7UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000070 */
1407 #define COMP_CSR_COMP1INSEL_0 (0x1UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */
1408 #define COMP_CSR_COMP1INSEL_1 (0x2UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */
1409 #define COMP_CSR_COMP1INSEL_2 (0x4UL << COMP_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */