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Searched refs:AddressSetupTime (Results 1 – 25 of 32) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_fmc.c406 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
421 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
431 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
475 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
487 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
494 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/src/
Dstm32l1xx_ll_fsmc.c281 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Timing_Init()
291 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Timing_Init()
326 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Extended_Timing_Init()
334 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_ll_fmc.c341 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
352 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
394 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
405 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_ll_fsmc.c334 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Timing_Init()
345 (Timing->AddressSetupTime << FSMC_BTRx_ADDSET_Pos) | in FSMC_NORSRAM_Timing_Init()
380 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Extended_Timing_Init()
394 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Extended_Timing_Init()
400 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_fmc.c336 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
347 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
390 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
401 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
407 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_fmc.c368 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
380 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
424 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
433 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_fmc.c373 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
385 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
429 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
438 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_fmc.c373 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
385 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
429 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
438 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_ll_fsmc.c318 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Timing_Init()
329 (Timing->AddressSetupTime << FSMC_BTR1_ADDSET_Pos) | in FSMC_NORSRAM_Timing_Init()
364 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Extended_Timing_Init()
372 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_fmc.c333 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
344 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
387 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
394 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_fsmc.c388 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Timing_Init()
398 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Timing_Init()
443 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Extended_Timing_Init()
451 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Extended_Timing_Init()
Dstm32f4xx_ll_fmc.c407 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
417 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
462 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
470 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_fmc.c331 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
341 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
384 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
392 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_fmc.c324 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
336 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
380 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
389 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_fmc.c331 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
342 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
385 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
393 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_fmc.c392 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
404 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
448 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
457 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_ll_fsmc.h180 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure member
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_fmc.h188 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure member
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_fsmc.h195 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure member
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_fmc.h234 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure member
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_fmc.h243 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure member
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_fmc.h221 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure member
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_fmc.h235 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure member
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_fsmc.h222 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure member
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_fmc.h217 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure member

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