1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_ll_fsmc.h 4 * @author MCD Application Team 5 * @brief Header file of FSMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F1xx_LL_FSMC_H 21 #define STM32F1xx_LL_FSMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f1xx_hal_def.h" 29 30 /** @addtogroup STM32F1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FSMC_LL 35 * @{ 36 */ 37 38 /** @addtogroup FSMC_LL_Private_Macros 39 * @{ 40 */ 41 #if defined(FSMC_BANK1) 42 43 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ 44 ((__BANK__) == FSMC_NORSRAM_BANK2) || \ 45 ((__BANK__) == FSMC_NORSRAM_BANK3) || \ 46 ((__BANK__) == FSMC_NORSRAM_BANK4)) 47 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ 48 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) 49 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ 50 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ 51 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) 52 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 53 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 54 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) 55 #define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \ 56 ((__SIZE__) == FSMC_PAGE_SIZE_128) || \ 57 ((__SIZE__) == FSMC_PAGE_SIZE_256) || \ 58 ((__SIZE__) == FSMC_PAGE_SIZE_512) || \ 59 ((__SIZE__) == FSMC_PAGE_SIZE_1024)) 60 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ 61 ((__MODE__) == FSMC_ACCESS_MODE_B) || \ 62 ((__MODE__) == FSMC_ACCESS_MODE_C) || \ 63 ((__MODE__) == FSMC_ACCESS_MODE_D)) 64 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ 65 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) 66 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ 67 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) 68 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ 69 ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) 70 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ 71 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) 72 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ 73 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) 74 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ 75 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) 76 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ 77 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) 78 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 79 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) 80 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 81 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ 82 ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) 83 #define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 84 ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 85 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 86 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 87 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 88 #define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 89 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 90 #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 91 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) 92 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) 93 94 #endif /* FSMC_BANK1 */ 95 #if defined(FSMC_BANK3) 96 97 #define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3) 98 #define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ 99 ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) 100 #define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ 101 ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) 102 #define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \ 103 ((__STATE__) == FSMC_NAND_ECC_ENABLE)) 104 105 #define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 106 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 107 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 108 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 109 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 110 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 111 #define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) 112 #define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) 113 #define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) 114 #define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) 115 #define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) 116 #define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) 117 #define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE) 118 119 #endif /* FSMC_BANK3 */ 120 #if defined(FSMC_BANK4) 121 #define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE) 122 123 #endif /* FSMC_BANK4 */ 124 125 /** 126 * @} 127 */ 128 129 /* Exported typedef ----------------------------------------------------------*/ 130 131 /** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types 132 * @{ 133 */ 134 135 #if defined(FSMC_BANK1) 136 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef 137 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef 138 #endif /* FSMC_BANK1 */ 139 #if defined(FSMC_BANK3) 140 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef 141 #endif /* FSMC_BANK3 */ 142 #if defined(FSMC_BANK4) 143 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef 144 #endif /* FSMC_BANK4 */ 145 146 #if defined(FSMC_BANK1) 147 #define FSMC_NORSRAM_DEVICE FSMC_Bank1 148 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E 149 #endif /* FSMC_BANK1 */ 150 #if defined(FSMC_BANK3) 151 #define FSMC_NAND_DEVICE FSMC_Bank2_3 152 #endif /* FSMC_BANK3 */ 153 #if defined(FSMC_BANK4) 154 #define FSMC_PCCARD_DEVICE FSMC_Bank4 155 #endif /* FSMC_BANK4 */ 156 157 #if defined(FSMC_BANK1) 158 /** 159 * @brief FSMC NORSRAM Configuration Structure definition 160 */ 161 typedef struct 162 { 163 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 164 This parameter can be a value of @ref FSMC_NORSRAM_Bank */ 165 166 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 167 multiplexed on the data bus or not. 168 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing*/ 169 170 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 171 the corresponding memory device. 172 This parameter can be a value of @ref FSMC_Memory_Type */ 173 174 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 175 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ 176 177 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 178 valid only with synchronous burst Flash memories. 179 This parameter can be a value of @ref FSMC_Burst_Access_Mode */ 180 181 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 182 the Flash memory in burst mode. 183 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ 184 185 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash 186 memory, valid only when accessing Flash memories in burst mode. 187 This parameter can be a value of @ref FSMC_Wrap_Mode */ 188 189 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 190 clock cycle before the wait state or during the wait state, 191 valid only when accessing memories in burst mode. 192 This parameter can be a value of @ref FSMC_Wait_Timing */ 193 194 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device 195 by the FSMC. 196 This parameter can be a value of @ref FSMC_Write_Operation */ 197 198 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 199 signal, valid for Flash memory access in burst mode. 200 This parameter can be a value of @ref FSMC_Wait_Signal */ 201 202 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 203 This parameter can be a value of @ref FSMC_Extended_Mode */ 204 205 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 206 valid only with asynchronous Flash memories. 207 This parameter can be a value of @ref FSMC_AsynchronousWait */ 208 209 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 210 This parameter can be a value of @ref FSMC_Write_Burst */ 211 212 213 uint32_t PageSize; /*!< Specifies the memory page size. 214 This parameter can be a value of @ref FSMC_Page_Size */ 215 } FSMC_NORSRAM_InitTypeDef; 216 217 /** 218 * @brief FSMC NORSRAM Timing parameters structure definition 219 */ 220 typedef struct 221 { 222 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 223 the duration of the address setup time. 224 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 225 @note This parameter is not used with synchronous NOR Flash memories. */ 226 227 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 228 the duration of the address hold time. 229 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 230 @note This parameter is not used with synchronous NOR Flash memories. */ 231 232 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 233 the duration of the data setup time. 234 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 235 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 236 NOR Flash memories. */ 237 238 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 239 the duration of the bus turnaround. 240 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 241 @note This parameter is only used for multiplexed NOR Flash memories. */ 242 243 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 244 HCLK cycles. This parameter can be a value between Min_Data = 2 and 245 Max_Data = 16. 246 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 247 accesses. */ 248 249 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 250 to the memory before getting the first data. 251 The parameter value depends on the memory type as shown below: 252 - It must be set to 0 in case of a CRAM 253 - It is don't care in asynchronous NOR, SRAM or ROM accesses 254 - It may assume a value between Min_Data = 2 and Max_Data = 17 255 in NOR Flash memories with synchronous burst mode enable */ 256 257 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 258 This parameter can be a value of @ref FSMC_Access_Mode */ 259 } FSMC_NORSRAM_TimingTypeDef; 260 #endif /* FSMC_BANK1 */ 261 262 #if defined(FSMC_BANK3) 263 /** 264 * @brief FSMC NAND Configuration Structure definition 265 */ 266 typedef struct 267 { 268 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 269 This parameter can be a value of @ref FSMC_NAND_Bank */ 270 271 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 272 This parameter can be any value of @ref FSMC_Wait_feature */ 273 274 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 275 This parameter can be any value of @ref FSMC_NAND_Data_Width */ 276 277 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 278 This parameter can be any value of @ref FSMC_ECC */ 279 280 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 281 This parameter can be any value of @ref FSMC_ECC_Page_Size */ 282 283 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 284 delay between CLE low and RE low. 285 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 286 287 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 288 delay between ALE low and RE low. 289 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 290 } FSMC_NAND_InitTypeDef; 291 #endif /* FSMC_BANK3 */ 292 293 #if defined(FSMC_BANK3) || defined(FSMC_BANK4) 294 /** 295 * @brief FSMC NAND Timing parameters structure definition 296 */ 297 typedef struct 298 { 299 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 300 the command assertion for NAND-Flash read or write access 301 to common/Attribute or I/O memory space (depending on 302 the memory space timing to be configured). 303 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 304 305 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 306 command for NAND-Flash read or write access to 307 common/Attribute or I/O memory space (depending on the 308 memory space timing to be configured). 309 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 310 311 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 312 (and data for write access) after the command de-assertion 313 for NAND-Flash read or write access to common/Attribute 314 or I/O memory space (depending on the memory space timing 315 to be configured). 316 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 317 318 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 319 data bus is kept in HiZ after the start of a NAND-Flash 320 write access to common/Attribute or I/O memory space (depending 321 on the memory space timing to be configured). 322 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 323 } FSMC_NAND_PCC_TimingTypeDef; 324 #endif /* FSMC_BANK3 */ 325 326 #if defined(FSMC_BANK4) 327 /** 328 * @brief FSMC PCCARD Configuration Structure definition 329 */ 330 typedef struct 331 { 332 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. 333 This parameter can be any value of @ref FSMC_Wait_feature */ 334 335 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 336 delay between CLE low and RE low. 337 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 338 339 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 340 delay between ALE low and RE low. 341 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 342 } FSMC_PCCARD_InitTypeDef; 343 #endif /* FSMC_BANK4 */ 344 345 /** 346 * @} 347 */ 348 349 /* Exported constants --------------------------------------------------------*/ 350 /** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants 351 * @{ 352 */ 353 #if defined(FSMC_BANK1) 354 355 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller 356 * @{ 357 */ 358 359 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank 360 * @{ 361 */ 362 #define FSMC_NORSRAM_BANK1 (0x00000000U) 363 #define FSMC_NORSRAM_BANK2 (0x00000002U) 364 #define FSMC_NORSRAM_BANK3 (0x00000004U) 365 #define FSMC_NORSRAM_BANK4 (0x00000006U) 366 /** 367 * @} 368 */ 369 370 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing 371 * @{ 372 */ 373 #define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) 374 #define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) 375 /** 376 * @} 377 */ 378 379 /** @defgroup FSMC_Memory_Type FSMC Memory Type 380 * @{ 381 */ 382 #define FSMC_MEMORY_TYPE_SRAM (0x00000000U) 383 #define FSMC_MEMORY_TYPE_PSRAM (0x00000004U) 384 #define FSMC_MEMORY_TYPE_NOR (0x00000008U) 385 /** 386 * @} 387 */ 388 389 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width 390 * @{ 391 */ 392 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) 393 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) 394 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) 395 /** 396 * @} 397 */ 398 399 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access 400 * @{ 401 */ 402 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) 403 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) 404 /** 405 * @} 406 */ 407 408 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode 409 * @{ 410 */ 411 #define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) 412 #define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) 413 /** 414 * @} 415 */ 416 417 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity 418 * @{ 419 */ 420 #define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) 421 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) 422 /** 423 * @} 424 */ 425 426 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode 427 * @{ 428 */ 429 #define FSMC_WRAP_MODE_DISABLE (0x00000000U) 430 #define FSMC_WRAP_MODE_ENABLE (0x00000400U) 431 /** 432 * @} 433 */ 434 435 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing 436 * @{ 437 */ 438 #define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U) 439 #define FSMC_WAIT_TIMING_DURING_WS (0x00000800U) 440 /** 441 * @} 442 */ 443 444 /** @defgroup FSMC_Write_Operation FSMC Write Operation 445 * @{ 446 */ 447 #define FSMC_WRITE_OPERATION_DISABLE (0x00000000U) 448 #define FSMC_WRITE_OPERATION_ENABLE (0x00001000U) 449 /** 450 * @} 451 */ 452 453 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal 454 * @{ 455 */ 456 #define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U) 457 #define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U) 458 /** 459 * @} 460 */ 461 462 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode 463 * @{ 464 */ 465 #define FSMC_EXTENDED_MODE_DISABLE (0x00000000U) 466 #define FSMC_EXTENDED_MODE_ENABLE (0x00004000U) 467 /** 468 * @} 469 */ 470 471 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait 472 * @{ 473 */ 474 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) 475 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) 476 /** 477 * @} 478 */ 479 480 /** @defgroup FSMC_Page_Size FSMC Page Size 481 * @{ 482 */ 483 #define FSMC_PAGE_SIZE_NONE (0x00000000U) 484 #define FSMC_PAGE_SIZE_128 (0x00010000U) 485 #define FSMC_PAGE_SIZE_256 (0x00020000U) 486 #define FSMC_PAGE_SIZE_512 (0x00030000U) 487 #define FSMC_PAGE_SIZE_1024 (0x00040000U) 488 /** 489 * @} 490 */ 491 492 /** @defgroup FSMC_Write_Burst FSMC Write Burst 493 * @{ 494 */ 495 #define FSMC_WRITE_BURST_DISABLE (0x00000000U) 496 #define FSMC_WRITE_BURST_ENABLE (0x00080000U) 497 /** 498 * @} 499 */ 500 501 /** @defgroup FSMC_Continous_Clock FSMC Continuous Clock 502 * @{ 503 */ 504 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) 505 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) 506 /** 507 * @} 508 */ 509 510 /** @defgroup FSMC_Access_Mode FSMC Access Mode 511 * @{ 512 */ 513 #define FSMC_ACCESS_MODE_A (0x00000000U) 514 #define FSMC_ACCESS_MODE_B (0x10000000U) 515 #define FSMC_ACCESS_MODE_C (0x20000000U) 516 #define FSMC_ACCESS_MODE_D (0x30000000U) 517 /** 518 * @} 519 */ 520 521 /** 522 * @} 523 */ 524 #endif /* FSMC_BANK1 */ 525 526 #if defined(FSMC_BANK3) || defined(FSMC_BANK4) 527 528 /** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller 529 * @{ 530 */ 531 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank 532 * @{ 533 */ 534 #define FSMC_NAND_BANK2 (0x00000010U) 535 #define FSMC_NAND_BANK3 (0x00000100U) 536 /** 537 * @} 538 */ 539 540 /** @defgroup FSMC_Wait_feature FSMC Wait feature 541 * @{ 542 */ 543 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U) 544 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U) 545 /** 546 * @} 547 */ 548 549 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type 550 * @{ 551 */ 552 #if defined(FSMC_BANK4) 553 #define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U) 554 #endif /* FSMC_BANK4 */ 555 #define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U) 556 /** 557 * @} 558 */ 559 560 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width 561 * @{ 562 */ 563 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U) 564 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U) 565 /** 566 * @} 567 */ 568 569 /** @defgroup FSMC_ECC FSMC ECC 570 * @{ 571 */ 572 #define FSMC_NAND_ECC_DISABLE (0x00000000U) 573 #define FSMC_NAND_ECC_ENABLE (0x00000040U) 574 /** 575 * @} 576 */ 577 578 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size 579 * @{ 580 */ 581 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) 582 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) 583 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) 584 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) 585 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) 586 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) 587 /** 588 * @} 589 */ 590 591 /** 592 * @} 593 */ 594 #endif /* FSMC_BANK3 || FSMC_Bank4 */ 595 596 597 /** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition 598 * @{ 599 */ 600 #if defined(FSMC_BANK3) || defined(FSMC_BANK4) 601 #define FSMC_IT_RISING_EDGE (0x00000008U) 602 #define FSMC_IT_LEVEL (0x00000010U) 603 #define FSMC_IT_FALLING_EDGE (0x00000020U) 604 #endif /* FSMC_BANK3 || FSMC_Bank4 */ 605 /** 606 * @} 607 */ 608 609 /** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition 610 * @{ 611 */ 612 #if defined(FSMC_BANK3) || defined(FSMC_BANK4) 613 #define FSMC_FLAG_RISING_EDGE (0x00000001U) 614 #define FSMC_FLAG_LEVEL (0x00000002U) 615 #define FSMC_FLAG_FALLING_EDGE (0x00000004U) 616 #define FSMC_FLAG_FEMPT (0x00000040U) 617 #endif /* FSMC_BANK3 || FSMC_Bank4 */ 618 /** 619 * @} 620 */ 621 622 /** 623 * @} 624 */ 625 626 /** 627 * @} 628 */ 629 630 /* Private macro -------------------------------------------------------------*/ 631 /** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros 632 * @{ 633 */ 634 #if defined(FSMC_BANK1) 635 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros 636 * @brief macros to handle NOR device enable/disable and read/write operations 637 * @{ 638 */ 639 640 /** 641 * @brief Enable the NORSRAM device access. 642 * @param __INSTANCE__ FSMC_NORSRAM Instance 643 * @param __BANK__ FSMC_NORSRAM Bank 644 * @retval None 645 */ 646 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 647 |= FSMC_BCRx_MBKEN) 648 649 /** 650 * @brief Disable the NORSRAM device access. 651 * @param __INSTANCE__ FSMC_NORSRAM Instance 652 * @param __BANK__ FSMC_NORSRAM Bank 653 * @retval None 654 */ 655 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 656 &= ~FSMC_BCRx_MBKEN) 657 658 /** 659 * @} 660 */ 661 #endif /* FSMC_BANK1 */ 662 663 #if defined(FSMC_BANK3) 664 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros 665 * @brief macros to handle NAND device enable/disable 666 * @{ 667 */ 668 669 /** 670 * @brief Enable the NAND device access. 671 * @param __INSTANCE__ FSMC_NAND Instance 672 * @param __BANK__ FSMC_NAND Bank 673 * @retval None 674 */ 675 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2) ? \ 676 ((__INSTANCE__)->PCR2 |= FSMC_PCRx_PBKEN) : \ 677 ((__INSTANCE__)->PCR3 |= FSMC_PCRx_PBKEN)) 678 679 /** 680 * @brief Disable the NAND device access. 681 * @param __INSTANCE__ FSMC_NAND Instance 682 * @param __BANK__ FSMC_NAND Bank 683 * @retval None 684 */ 685 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2) ? \ 686 CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN) : \ 687 CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN)) 688 689 /** 690 * @} 691 */ 692 #endif /* FSMC_BANK3 */ 693 694 #if defined(FSMC_BANK4) 695 /** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros 696 * @brief macros to handle PCCARD read/write operations 697 * @{ 698 */ 699 /** 700 * @brief Enable the PCCARD device access. 701 * @param __INSTANCE__ FSMC_PCCARD Instance 702 * @retval None 703 */ 704 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCRx_PBKEN) 705 706 /** 707 * @brief Disable the PCCARD device access. 708 * @param __INSTANCE__ FSMC_PCCARD Instance 709 * @retval None 710 */ 711 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCRx_PBKEN) 712 /** 713 * @} 714 */ 715 716 #endif /* FSMC_BANK4 */ 717 #if defined(FSMC_BANK3) 718 /** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt 719 * @brief macros to handle NAND interrupts 720 * @{ 721 */ 722 723 /** 724 * @brief Enable the NAND device interrupt. 725 * @param __INSTANCE__ FSMC_NAND instance 726 * @param __BANK__ FSMC_NAND Bank 727 * @param __INTERRUPT__ FSMC_NAND interrupt 728 * This parameter can be any combination of the following values: 729 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. 730 * @arg FSMC_IT_LEVEL: Interrupt level. 731 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. 732 * @retval None 733 */ 734 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2) ? \ 735 ((__INSTANCE__)->SR2 |= (__INTERRUPT__)) : \ 736 ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) 737 738 /** 739 * @brief Disable the NAND device interrupt. 740 * @param __INSTANCE__ FSMC_NAND Instance 741 * @param __BANK__ FSMC_NAND Bank 742 * @param __INTERRUPT__ FSMC_NAND interrupt 743 * This parameter can be any combination of the following values: 744 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. 745 * @arg FSMC_IT_LEVEL: Interrupt level. 746 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. 747 * @retval None 748 */ 749 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2) ? \ 750 ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)) : \ 751 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) 752 753 /** 754 * @brief Get flag status of the NAND device. 755 * @param __INSTANCE__ FSMC_NAND Instance 756 * @param __BANK__ FSMC_NAND Bank 757 * @param __FLAG__ FSMC_NAND flag 758 * This parameter can be any combination of the following values: 759 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 760 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. 761 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 762 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. 763 * @retval The state of FLAG (SET or RESET). 764 */ 765 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2) ? \ 766 (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)) : \ 767 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) 768 769 /** 770 * @brief Clear flag status of the NAND device. 771 * @param __INSTANCE__ FSMC_NAND Instance 772 * @param __BANK__ FSMC_NAND Bank 773 * @param __FLAG__ FSMC_NAND flag 774 * This parameter can be any combination of the following values: 775 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 776 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. 777 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 778 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. 779 * @retval None 780 */ 781 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2) ? \ 782 ((__INSTANCE__)->SR2 &= ~(__FLAG__)) : \ 783 ((__INSTANCE__)->SR3 &= ~(__FLAG__))) 784 785 /** 786 * @} 787 */ 788 #endif /* FSMC_BANK3 */ 789 790 #if defined(FSMC_BANK4) 791 /** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt 792 * @brief macros to handle PCCARD interrupts 793 * @{ 794 */ 795 796 /** 797 * @brief Enable the PCCARD device interrupt. 798 * @param __INSTANCE__ FSMC_PCCARD instance 799 * @param __INTERRUPT__ FSMC_PCCARD interrupt 800 * This parameter can be any combination of the following values: 801 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. 802 * @arg FSMC_IT_LEVEL: Interrupt level. 803 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. 804 * @retval None 805 */ 806 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) 807 808 /** 809 * @brief Disable the PCCARD device interrupt. 810 * @param __INSTANCE__ FSMC_PCCARD instance 811 * @param __INTERRUPT__ FSMC_PCCARD interrupt 812 * This parameter can be any combination of the following values: 813 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. 814 * @arg FSMC_IT_LEVEL: Interrupt level. 815 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. 816 * @retval None 817 */ 818 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) 819 820 /** 821 * @brief Get flag status of the PCCARD device. 822 * @param __INSTANCE__ FSMC_PCCARD instance 823 * @param __FLAG__ FSMC_PCCARD flag 824 * This parameter can be any combination of the following values: 825 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 826 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. 827 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 828 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. 829 * @retval The state of FLAG (SET or RESET). 830 */ 831 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) 832 833 /** 834 * @brief Clear flag status of the PCCARD device. 835 * @param __INSTANCE__ FSMC_PCCARD instance 836 * @param __FLAG__ FSMC_PCCARD flag 837 * This parameter can be any combination of the following values: 838 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 839 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. 840 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 841 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. 842 * @retval None 843 */ 844 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) 845 846 /** 847 * @} 848 */ 849 #endif /* FSMC_BANK4 */ 850 851 /** 852 * @} 853 */ 854 855 /** 856 * @} 857 */ 858 859 /* Private functions ---------------------------------------------------------*/ 860 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions 861 * @{ 862 */ 863 864 #if defined(FSMC_BANK1) 865 /** @defgroup FSMC_LL_NORSRAM NOR SRAM 866 * @{ 867 */ 868 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 869 * @{ 870 */ 871 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, 872 const FSMC_NORSRAM_InitTypeDef *Init); 873 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, 874 const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 875 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, 876 const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, 877 uint32_t ExtendedMode); 878 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, 879 FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 880 /** 881 * @} 882 */ 883 884 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 885 * @{ 886 */ 887 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); 888 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); 889 /** 890 * @} 891 */ 892 /** 893 * @} 894 */ 895 #endif /* FSMC_BANK1 */ 896 897 #if defined(FSMC_BANK3) 898 /** @defgroup FSMC_LL_NAND NAND 899 * @{ 900 */ 901 /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 902 * @{ 903 */ 904 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, const FSMC_NAND_InitTypeDef *Init); 905 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, 906 const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 907 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, 908 const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 909 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); 910 /** 911 * @} 912 */ 913 914 /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions 915 * @{ 916 */ 917 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); 918 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); 919 HAL_StatusTypeDef FSMC_NAND_GetECC(const FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, 920 uint32_t Timeout); 921 /** 922 * @} 923 */ 924 /** 925 * @} 926 */ 927 #endif /* FSMC_BANK3 */ 928 929 #if defined(FSMC_BANK4) 930 /** @defgroup FSMC_LL_PCCARD PCCARD 931 * @{ 932 */ 933 /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions 934 * @{ 935 */ 936 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, const FSMC_PCCARD_InitTypeDef *Init); 937 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, 938 const FSMC_NAND_PCC_TimingTypeDef *Timing); 939 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, 940 const FSMC_NAND_PCC_TimingTypeDef *Timing); 941 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, 942 const FSMC_NAND_PCC_TimingTypeDef *Timing); 943 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); 944 /** 945 * @} 946 */ 947 /** 948 * @} 949 */ 950 #endif /* FSMC_BANK4 */ 951 952 953 /** 954 * @} 955 */ 956 957 /** 958 * @} 959 */ 960 961 /** 962 * @} 963 */ 964 965 #ifdef __cplusplus 966 } 967 #endif 968 969 #endif /* STM32F1xx_LL_FSMC_H */ 970
