Home
last modified time | relevance | path

Searched refs:ADC_CFGR1_AWD1SGL_Pos (Results 1 – 25 of 64) sorted by relevance

123

/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_adc.h470 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR1_AWD1SGL_Pos)
6753 …channel_monitored |= ((1UL - ((AWDChannelGroup & ADC_CFGR1_AWD1SGL) >> ADC_CFGR1_AWD1SGL_Pos)) * 0… in LL_ADC_SetAnalogWDMonitChannels()
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h669 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
670 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32f030x8.h685 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
686 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32f070x6.h714 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
715 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32f031x6.h679 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
680 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32f030xc.h701 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
702 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32f038xx.h678 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
679 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32f070xb.h737 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
738 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32f058xx.h784 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
785 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32f051x8.h785 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
786 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32f071xb.h819 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
820 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h793 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
794 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32c031xx.h797 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
798 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32c071xx.h874 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
875 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h1142 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
1143 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
1212 #define ADC_CFGR_AWD1SGL_Pos ADC_CFGR1_AWD1SGL_Pos
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h1127 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
1128 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
1197 #define ADC_CFGR_AWD1SGL_Pos ADC_CFGR1_AWD1SGL_Pos
Dstm32wb15xx.h1142 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
1143 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
1212 #define ADC_CFGR_AWD1SGL_Pos ADC_CFGR1_AWD1SGL_Pos
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h838 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
839 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32g050xx.h857 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
858 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32g070xx.h860 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
861 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32g031xx.h881 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
882 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32g041xx.h928 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
929 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32g051xx.h944 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
945 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Dstm32g061xx.h991 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
992 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h1173 #define ADC_CFGR1_AWD1SGL_Pos (22U) macro
1174 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */

123