Home
last modified time | relevance | path

Searched refs:ADC_AWD3TR_HT3_10 (Results 1 – 25 of 40) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h1218 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1247 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32c031xx.h1222 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1251 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32c071xx.h1299 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1328 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h1251 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1280 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32g050xx.h1270 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1299 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32g070xx.h1273 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1302 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32g031xx.h1294 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1323 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32g041xx.h1341 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1370 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32g051xx.h1357 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1386 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32g061xx.h1404 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1433 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32g071xx.h1406 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1435 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32g081xx.h1453 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1482 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32g0b0xx.h1355 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1384 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32g0c1xx.h1620 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1649 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32g0b1xx.h1573 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1602 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h1577 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1606 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32wle5xx.h1577 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1606 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32wl5mxx.h1759 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1788 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32wl54xx.h1759 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1788 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
Dstm32wl55xx.h1759 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
1788 #define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h1638 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
Dstm32wba52xx.h2119 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h1450 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
Dstm32u083xx.h1603 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro
Dstm32u073xx.h1567 #define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ macro

12