Home
last modified time | relevance | path

Searched refs:ADC_AWD3TR_HT3_1 (Results 1 – 25 of 40) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h1209 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1238 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32c031xx.h1213 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1242 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32c071xx.h1290 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1319 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h1242 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1271 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32g050xx.h1261 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1290 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32g070xx.h1264 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1293 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32g031xx.h1285 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1314 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32g041xx.h1332 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1361 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32g051xx.h1348 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1377 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32g061xx.h1395 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1424 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32g071xx.h1397 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1426 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32g081xx.h1444 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1473 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32g0b0xx.h1346 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1375 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32g0c1xx.h1611 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1640 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32g0b1xx.h1564 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1593 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h1568 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1597 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32wle5xx.h1568 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1597 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32wl5mxx.h1750 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1779 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32wl54xx.h1750 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1779 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
Dstm32wl55xx.h1750 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
1779 #define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h1629 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
Dstm32wba52xx.h2110 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h1441 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
Dstm32u083xx.h1594 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro
Dstm32u073xx.h1558 #define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ macro

12