Home
last modified time | relevance | path

Searched refs:ADC_AWD2TR_HT2_0 (Results 1 – 25 of 40) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h1004 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1033 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32c031xx.h1008 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1037 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32c071xx.h1085 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1114 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h1049 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1078 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32g050xx.h1068 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1097 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32g070xx.h1071 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1100 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32g031xx.h1092 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1121 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32g041xx.h1139 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1168 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32g051xx.h1155 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1184 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32g061xx.h1202 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1231 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32g071xx.h1204 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1233 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32g081xx.h1251 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1280 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32g0b0xx.h1153 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1182 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32g0c1xx.h1418 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1447 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32g0b1xx.h1371 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1400 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h1378 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1407 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32wle5xx.h1378 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1407 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32wl5mxx.h1560 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1589 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32wl54xx.h1560 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1589 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
Dstm32wl55xx.h1560 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
1589 #define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h1468 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
Dstm32wba52xx.h1949 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h1265 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
Dstm32u083xx.h1418 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro
Dstm32u073xx.h1382 #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ macro

12