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Searched refs:ADC_AWD1TR_LT1_5 (Results 1 – 25 of 40) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h931 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
962 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32c031xx.h935 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
966 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32c071xx.h1012 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1043 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h976 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1007 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32g050xx.h995 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1026 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32g070xx.h998 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1029 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32g031xx.h1019 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1050 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32g041xx.h1066 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1097 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32g051xx.h1082 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1113 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32g061xx.h1129 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1160 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32g071xx.h1131 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1162 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32g081xx.h1178 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1209 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32g0b0xx.h1080 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1111 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32g0c1xx.h1345 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1376 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32g0b1xx.h1298 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1329 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h1305 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1336 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32wle5xx.h1305 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1336 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32wl5mxx.h1487 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1518 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32wl54xx.h1487 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1518 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
Dstm32wl55xx.h1487 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
1518 #define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h1424 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
Dstm32wba52xx.h1905 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h1221 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
Dstm32u083xx.h1374 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro
Dstm32u073xx.h1338 #define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ macro

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