Home
last modified time | relevance | path

Searched refs:ADC_AWD1TR_LT1_2 (Results 1 – 25 of 40) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h928 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
959 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32c031xx.h932 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
963 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32c071xx.h1009 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1040 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g030xx.h973 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1004 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32g050xx.h992 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1023 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32g070xx.h995 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1026 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32g031xx.h1016 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1047 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32g041xx.h1063 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1094 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32g051xx.h1079 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1110 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32g061xx.h1126 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1157 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32g071xx.h1128 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1159 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32g081xx.h1175 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1206 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32g0b0xx.h1077 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1108 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32g0c1xx.h1342 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1373 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32g0b1xx.h1295 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1326 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h1302 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1333 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32wle5xx.h1302 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1333 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32wl5mxx.h1484 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1515 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32wl54xx.h1484 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1515 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
Dstm32wl55xx.h1484 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
1515 #define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h1421 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
Dstm32wba52xx.h1902 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h1218 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
Dstm32u083xx.h1371 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro
Dstm32u073xx.h1335 #define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ macro

12