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Searched refs:BDCR1 (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_rcc_ex.c336 tmpreg1 = (RCC->BDCR1 & ~RCC_BDCR1_RTCSEL); in HAL_RCCEx_PeriphCLKConfig()
353 RCC->BDCR1 = (tmpreg1 | PeriphClkInit->RTCClockSelection); in HAL_RCCEx_PeriphCLKConfig()
370 while (READ_BIT(RCC->BDCR1, (tmpreg2 << 1)) == 0x00u) in HAL_RCCEx_PeriphCLKConfig()
489 tmpreg = RCC->BDCR1; in HAL_RCCEx_GetPeriphCLKConfig()
554 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY)) in HAL_RCCEx_GetPeriphCLKFreq()
583 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY)) in HAL_RCCEx_GetPeriphCLKFreq()
633 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY)) in HAL_RCCEx_GetPeriphCLKFreq()
639 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV)) in HAL_RCCEx_GetPeriphCLKFreq()
645 else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY)) in HAL_RCCEx_GetPeriphCLKFreq()
664 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY)) in HAL_RCCEx_GetPeriphCLKFreq()
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Dstm32wbaxx_hal_rcc.c524 tmpreg1 = RCC->BDCR1; in HAL_RCC_OscConfig()
545 RCC->BDCR1 = tmpreg1; in HAL_RCC_OscConfig()
551 while (READ_BIT(RCC->BDCR1, RCC_BDCR1_LSI1RDY) != 0x00u) in HAL_RCC_OscConfig()
572 RCC->BDCR1 = tmpreg1; in HAL_RCC_OscConfig()
578 while (READ_BIT(RCC->BDCR1, (RCC_OscInitStruct->LSIState << 1)) == 0x00u) in HAL_RCC_OscConfig()
590 RCC->BDCR1 = tmpreg1; in HAL_RCC_OscConfig()
596 while (READ_BIT(RCC->BDCR1, (mask << 1)) != 0x00u) in HAL_RCC_OscConfig()
609 RCC->BDCR1 = tmpreg1; in HAL_RCC_OscConfig()
615 while (READ_BIT(RCC->BDCR1, (mask << 1)) != 0x00u) in HAL_RCC_OscConfig()
668 tmpreg1 = (RCC->BDCR1 & ~RCC_BDCR1_LSESYSEN); in HAL_RCC_OscConfig()
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Dstm32wbaxx_ll_rcc.c551 if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) in LL_RCC_GetLPTIMClockFreq()
591 if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) in LL_RCC_GetLPTIMClockFreq()
727 if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) in LL_RCC_GetRNGClockFreq()
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_rcc.h1022 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEON); in LL_RCC_LSE_Enable()
1032 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEON); in LL_RCC_LSE_Disable()
1042 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP); in LL_RCC_LSE_EnableBypass()
1052 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP); in LL_RCC_LSE_DisableBypass()
1062 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON); in LL_RCC_LSE_EnableGlitchFilter()
1072 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON); in LL_RCC_LSE_DisableGlitchFilter()
1087 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSETRIM, LSETrim); in LL_RCC_LSE_SetClockTrimming()
1102 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_LSETRIM)); in LL_RCC_LSE_GetClockTrimming()
1117 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSEDRV, LSEDrive); in LL_RCC_LSE_SetDriveCapability()
1130 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_LSEDRV)); in LL_RCC_LSE_GetDriveCapability()
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Dstm32wbaxx_hal_rcc.h1667 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR1, RCC_BDCR1_BDRST)
1668 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_BDRST)
1729 #define __HAL_RCC_LSI1_ENABLE() SET_BIT(RCC->BDCR1, RCC_BDCR1_LSI1ON)
1730 #define __HAL_RCC_LSI1_DISABLE() CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSI1ON)
1742 #define __HAL_RCC_LSI_DIV_CONFIG(__DIVIDER__) MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV, __DI…
1756 #define __HAL_RCC_LSI2_ENABLE() SET_BIT(RCC->BDCR1, RCC_BDCR1_LSI2ON)
1757 #define __HAL_RCC_LSI2_DISABLE() CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSI2ON)
1790 #define __HAL_RCC_LSESYS_ENABLE() SET_BIT(RCC->BDCR1,RCC_BDCR1_LSESYSEN)
1791 #define __HAL_RCC_LSESYS_DISABLE() CLEAR_BIT(RCC->BDCR1,RCC_BDCR1_LSESYSEN)
1799 #define __HAL_RCC_LSE_GlitchFilter_ENABLE() SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON )
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Dstm32wbaxx_hal_rcc_ex.h750 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_RADIOSTSEL, (__RADIOST_CLKSOURCE__))
759 #define __HAL_RCC_GET_RADIOSLPTIM_SOURCE() READ_BIT(RCC->BDCR1, RCC_BDCR1_RADIOSTSEL)
/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_pwr.h2367 SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN); in LL_PWR_EnableBkUpRegulator()
2377 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN); in LL_PWR_DisableBkUpRegulator()
2387 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_BREN) == (PWR_BDCR1_BREN)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpRegulator()
2397 SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); in LL_PWR_EnableMonitoring()
2407 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); in LL_PWR_DisableMonitoring()
2418 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_MONEN) == (PWR_BDCR1_MONEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledMonitoring()
/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_pwr_ex.c1371 SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); in HAL_PWREx_EnableMonitoring()
1380 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); in HAL_PWREx_DisableMonitoring()
2317 SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN); in HAL_PWREx_EnableBkupRAMRetention()
2337 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN); in HAL_PWREx_DisableBkupRAMRetention()
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h602 …__IO uint32_t BDCR1; /*!< Backup Domain Control Register 1 Address … member
Dstm32wba52xx.h694 …__IO uint32_t BDCR1; /*!< Backup Domain Control Register 1 Address … member
Dstm32wba54xx.h720 …__IO uint32_t BDCR1; /*!< Backup Domain Control Register 1 Address … member
Dstm32wba55xx.h720 …__IO uint32_t BDCR1; /*!< Backup Domain Control Register 1 Address … member
/hal_stm32-3.5.0/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h899 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u535xx.h833 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u575xx.h896 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u5a5xx.h1000 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u585xx.h963 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u5f7xx.h1094 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u595xx.h933 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u599xx.h1114 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u5g7xx.h1161 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u5a9xx.h1181 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u5g9xx.h1265 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u5f9xx.h1198 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member