1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBAxx_LL_RCC_H
21 #define STM32WBAxx_LL_RCC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbaxx.h"
29
30 /** @addtogroup STM32WBAxx_LL_Driver
31 * @{
32 */
33
34 #if defined(RCC)
35
36 /** @defgroup RCC_LL RCC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
44 * @{
45 */
46 /* Defines used to perform offsets*/
47 /* Offset used to access to RCC_CCIPR1, RCC_CCIPR2 and RCC_CCIPR3 registers */
48 #define RCC_OFFSET_CCIPR1 0U
49 #define RCC_OFFSET_CCIPR2 0x04U
50 #define RCC_OFFSET_CCIPR3 0x08U
51
52 /* Defines used for security configuration extension */
53 #define RCC_SECURE_MASK 0x10FBU
54 /**
55 * @}
56 */
57
58 /* Private macros ------------------------------------------------------------*/
59 /* Exported types ------------------------------------------------------------*/
60 #if defined(USE_FULL_LL_DRIVER)
61 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
62 * @{
63 */
64
65 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
66 * @{
67 */
68
69 /**
70 * @brief RCC Clocks Frequency Structure
71 */
72 typedef struct
73 {
74 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
75 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
76 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
77 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
78 uint32_t PCLK7_Frequency; /*!< PCLK7 clock frequency */
79 } LL_RCC_ClocksTypeDef;
80
81 /**
82 * @}
83 */
84
85 /**
86 * @}
87 */
88 #endif /* USE_FULL_LL_DRIVER */
89
90 /* Exported constants --------------------------------------------------------*/
91 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
92 * @{
93 */
94
95 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
96 * @brief Defines used to adapt values of different oscillators
97 * @note These values could be modified in the user environment according to
98 * HW set-up.
99 * @{
100 */
101 #if !defined (HSE_VALUE)
102 #define HSE_VALUE 32000000U /*!< Value of the HSE oscillator in Hz */
103 #endif /* HSE_VALUE */
104
105 #if !defined (HSI_VALUE)
106 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
107 #endif /* HSI_VALUE */
108
109 #if !defined (LSE_VALUE)
110 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
111 #endif /* LSE_VALUE */
112
113 #if !defined (LSI_VALUE)
114 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
115 #endif /* LSI_VALUE */
116
117 #if defined (RCC_LSI2_SUPPORT)
118 #if !defined (LSI2_VALUE)
119 #define LSI2_VALUE 32000U /*!< Value of the LSI2 oscillator in Hz */
120 #endif /* LSI_VALUE */
121 #endif
122
123 #if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
124 #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */
125 #endif /* EXTERNAL_SAI1_CLOCK_VALUE */
126
127 /**
128 * @}
129 */
130
131 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
132 * @brief Flags defines which can be used with LL_RCC_WriteReg function
133 * @{
134 */
135 #define LL_RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC /*!< LSI1 Ready Interrupt Clear */
136 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
137 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
138 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
139 #define LL_RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC /*!< PLL1 Ready Interrupt Clear */
140 #define LL_RCC_CICR_HSECSSC RCC_CICR_HSECSSC /*!< HSE Clock Security System Interrupt Clear */
141 #define LL_RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC /*!< LSI2 Ready Interrupt Clear */
142 /**
143 * @}
144 */
145
146 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
147 * @brief Flags defines which can be used with LL_RCC_ReadReg function
148 * @{
149 */
150 #define LL_RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF /*!< LSI1 Ready Interrupt flag */
151 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
152 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
153 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
154 #define LL_RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */
155 #define LL_RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF /*!< HSE Clock Security System Interrupt flag */
156 #define LL_RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF /*!< LSI2 Ready Interrupt flag */
157 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< Option byte loader reset flag */
158 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< NRST pin reset flag */
159 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
160 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software reset flag */
161 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent watchdog reset flag */
162 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
163 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-power reset flag */
164 /**
165 * @}
166 */
167
168 /** @defgroup RCC_LL_EC_IT IT Defines
169 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
170 * @{
171 */
172 #define LL_RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE /*!< LSI1 Ready Interrupt Enable */
173 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
174 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
175 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
176 #define LL_RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE /*!< PLL1 Ready Interrupt Enable */
177 #define LL_RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE /*!< LSI2 Ready Interrupt Enable */
178 /**
179 * @}
180 */
181
182 /** @defgroup RCC_LL_EC_LSIPRE LSI prescaler
183 * @{
184 */
185 #define LL_RCC_LSI_DIV_1 0U /*!< LSI1 divided by 1 */
186 #define LL_RCC_LSI_DIV_128 RCC_BDCR1_LSI1PREDIV /*!< LSI1 divided by 128 */
187 /**
188 * @}
189 */
190
191 #if defined(RCC_BDCR2_LSI2CFG)
192 /** @defgroup RCC_LL_EC_LSI2CFG LSI2 oscillator temperature sensitivity configuration
193 * @{
194 */
195 #define LL_RCC_LSI2_TEMP_SENSITIVITY_80 0U /*!< LSI2 frequency temperature sensitivity is close to zero at +80 degrees C */
196 #define LL_RCC_LSI2_TEMP_SENSITIVITY_50 RCC_BDCR2_LSI2CFG_0 /*!< LSI2 frequency temperature sensitivity is close to zero at +50 degrees C */
197 #define LL_RCC_LSI2_TEMP_SENSITIVITY_20 RCC_BDCR2_LSI2CFG_1 /*!< LSI2 frequency temperature sensitivity is close to zero at +20 degrees C */
198 /**
199 * @}
200 */
201 #endif /* RCC_BDCR2_LSI2CFG */
202
203 #if defined(RCC_BDCR2_LSI2MODE)
204 /** @defgroup RCC_LL_EC_LSI2MODE LSI2 oscillator operating mode configuration
205 * @{
206 */
207 #define LL_RCC_LSI2_NOMINAL_MODE 0U /*!< LSI2 nominal power, high accuracy */
208 #define LL_RCC_LSI2_LOWPOWER_MODE RCC_BDCR2_LSI2MODE_0 /*!< LSI2 low power, medium accuracy */
209 #define LL_RCC_LSI2_ULTRALOWPOWER_MODE RCC_BDCR2_LSI2MODE_1 /*!< LSI2 ultra low power, low accuracy */
210 /**
211 * @}
212 */
213 #endif /* RCC_BDCR2_LSI2MODE */
214
215 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
216 * @{
217 */
218 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR1_LSEDRV_0 /*!< Xtal mode medium low driving capability */
219 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR1_LSEDRV_1 /*!< Xtal mode medium high driving capability */
220 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR1_LSEDRV /*!< Xtal mode higher driving capability */
221 /**
222 * @}
223 */
224
225 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
226 * @{
227 */
228 #define LL_RCC_LSCO_CLKSOURCE_LSI 0U /*!< LSI selection for low speed clock */
229 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR1_LSCOSEL /*!< LSE selection for low speed clock */
230 /**
231 * @}
232 */
233
234
235 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
236 * @{
237 */
238 #define LL_RCC_SYS_CLKSOURCE_HSI 0U /*!< HSI selection as system clock */
239 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */
240 #define LL_RCC_SYS_CLKSOURCE_PLL1R (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0) /*!< PLL1R selection as system clock */
241 /**
242 * @}
243 */
244
245
246 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
247 * @{
248 */
249 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0U /*!< HSI used as system clock */
250 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */
251 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1R (RCC_CFGR1_SWS_1 | RCC_CFGR1_SWS_0) /*!< PLL1R used as system clock */
252 /**
253 * @}
254 */
255
256
257 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
258 * @{
259 */
260 #define LL_RCC_SYSCLK_DIV_1 0U /*!< SYSCLK not divided */
261 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR2_HPRE_2 /*!< SYSCLK divided by 2 */
262 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 4 */
263 #define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 8 */
264 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 16 */
265 /**
266 * @}
267 */
268
269
270 /** @defgroup RCC_LL_EC_SYSTICK_CLKSOURCE SYSTICK clock source selection
271 * @{
272 */
273 #define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0U /*!< HCLKDIV8 clock used as SYSTICK clock source */
274 #define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */
275 #define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */
276 /**
277 * @}
278 */
279
280 /** @defgroup RCC_LL_EC_APB1_DIV APB1 prescaler
281 * @{
282 */
283 #define LL_RCC_APB1_DIV_1 0U /*!< HCLK not divided */
284 #define LL_RCC_APB1_DIV_2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */
285 #define LL_RCC_APB1_DIV_4 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 4 */
286 #define LL_RCC_APB1_DIV_8 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1) /*!< HCLK divided by 8 */
287 #define LL_RCC_APB1_DIV_16 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 16 */
288 /**
289 * @}
290 */
291
292
293 /** @defgroup RCC_LL_EC_APB2_DIV APB2 prescaler
294 * @{
295 */
296 #define LL_RCC_APB2_DIV_1 0U /*!< HCLK not divided */
297 #define LL_RCC_APB2_DIV_2 RCC_CFGR2_PPRE2_2 /*!< HCLK divided by 2 */
298 #define LL_RCC_APB2_DIV_4 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 4 */
299 #define LL_RCC_APB2_DIV_8 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1) /*!< HCLK divided by 8 */
300 #define LL_RCC_APB2_DIV_16 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 16 */
301 /**
302 * @}
303 */
304
305 /** @defgroup RCC_LL_EC_APB7_DIV APB7 prescaler
306 * @{
307 */
308 #define LL_RCC_APB7_DIV_1 0U /*!< HCLK not divided */
309 #define LL_RCC_APB7_DIV_2 RCC_CFGR3_PPRE7_2 /*!< HCLK divided by 2 */
310 #define LL_RCC_APB7_DIV_4 (RCC_CFGR3_PPRE7_2 | RCC_CFGR3_PPRE7_0) /*!< HCLK divided by 4 */
311 #define LL_RCC_APB7_DIV_8 (RCC_CFGR3_PPRE7_2 | RCC_CFGR3_PPRE7_1) /*!< HCLK divided by 8 */
312 #define LL_RCC_APB7_DIV_16 (RCC_CFGR3_PPRE7_2 | RCC_CFGR3_PPRE7_1 | RCC_CFGR3_PPRE7_0) /*!< HCLK divided by 16 */
313 /**
314 * @}
315 */
316
317 /** @defgroup RCC_LL_EC_AHB5_DIV AHB5 prescaler when SYSCLK is PLL1R
318 * @{
319 */
320 #define LL_RCC_AHB5_DIV_1 0U /*!< SYSCLK not divided */
321 #define LL_RCC_AHB5_DIV_2 RCC_CFGR4_HPRE5_2 /*!< SYSCLK divided by 2 */
322 #define LL_RCC_AHB5_DIV_3 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_0) /*!< SYSCLK divided by 3 */
323 #define LL_RCC_AHB5_DIV_4 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_1) /*!< SYSCLK divided by 4 */
324 #define LL_RCC_AHB5_DIV_6 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_1 | RCC_CFGR4_HPRE5_0) /*!< SYSCLK divided by 6 */
325 /**
326 * @}
327 */
328
329 /** @defgroup RCC_LL_EC_AHB5_DIVIDER AHB5 divider when SYSCLK is HSI or HSE
330 * @{
331 */
332 #define LL_RCC_AHB5_DIVIDER_1 0U /*!< SYSCLK not divided */
333 #define LL_RCC_AHB5_DIVIDER_2 RCC_CFGR4_HDIV5 /*!< SYSCLK divided by 2 */
334 /**
335 * @}
336 */
337
338 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
339 * @{
340 */
341 #define LL_RCC_MCO1SOURCE_NOCLOCK 0U /*!< MCO output disabled, no clock on MCO */
342 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
343 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1) /*!< HSI selection as MCO1 source */
344 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE selection as MCO1 source */
345 #define LL_RCC_MCO1SOURCE_PLL1R (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_2) /*!< PLL1RCLK selection as MCO1 source */
346 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_2) /*!< LSI selection as MCO1 source */
347 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1| RCC_CFGR1_MCOSEL_2)/*!< LSE selection as MCO1 source */
348 #define LL_RCC_MCO1SOURCE_PLL1P RCC_CFGR1_MCOSEL_3 /*!< PLL1PCLK selection as MCO1 source */
349 #define LL_RCC_MCO1SOURCE_PLL1Q (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_3) /*!< PLL1QCLK selection as MCO1 source */
350 #define LL_RCC_MCO1SOURCE_HCLK5 (RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_3) /*!< HCLK5 selection as MCO1 source */
351 /**
352 * @}
353 */
354
355 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
356 * @{
357 */
358 #define LL_RCC_MCO1_DIV_1 0U /*!< MCO not divided */
359 #define LL_RCC_MCO1_DIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO divided by 2 */
360 #define LL_RCC_MCO1_DIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO divided by 4 */
361 #define LL_RCC_MCO1_DIV_8 (RCC_CFGR1_MCOPRE_1 | RCC_CFGR1_MCOPRE_0) /*!< MCO divided by 8 */
362 #define LL_RCC_MCO1_DIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO divided by 16 */
363 /**
364 * @}
365 */
366
367 #if defined(USE_FULL_LL_DRIVER)
368 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
369 * @{
370 */
371 #define LL_RCC_PERIPH_FREQUENCY_NO 0U /*!< No clock enabled for the peripheral */
372 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
373 /**
374 * @}
375 */
376 #endif /* USE_FULL_LL_DRIVER */
377
378 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
379 * @{
380 */
381 #define LL_RCC_RTC_CLKSOURCE_NONE 0U /*!< No clock used as RTC clock */
382 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR1_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
383 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR1_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
384 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR1_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
385 /**
386 * @}
387 */
388
389 /** @defgroup RCC_LL_EC_RADIO_SLEEPTIMER_CLKSOURCE RADIO Sleep Timer Clock source
390 * @{
391 */
392 #define LL_RCC_RADIOSLEEPSOURCE_NONE 0U /*!< No clock selected, 2.4 GHz RADIO sleep timer kernel clock disabled */
393 #define LL_RCC_RADIOSLEEPSOURCE_LSE RCC_BDCR1_RADIOSTSEL_0 /*!< LSE oscillator clock selected */
394 #define LL_RCC_RADIOSLEEPSOURCE_LSI RCC_BDCR1_RADIOSTSEL_1 /*!< LSI oscillator clock selected */
395 #define LL_RCC_RADIOSLEEPSOURCE_HSE_DIV1000 RCC_BDCR1_RADIOSTSEL /*!< HSE oscillator clock divided by 1000 selected */
396 /**
397 * @}
398 */
399
400 /** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USARTx clock source selection
401 * @{
402 */
403 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR1_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */
404 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
405 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
406 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL) /*!< LSE clock used as USART1 clock source */
407 #if defined(USART2)
408 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR1_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */
409 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
410 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
411 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL) /*!< LSE clock used as USART2 clock source */
412 #endif /* USART2 */
413 /**
414 * @}
415 */
416
417 /** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUARTx clock source selection
418 * @{
419 */
420 #define LL_RCC_LPUART1_CLKSOURCE_PCLK7 0U /*!< PCLK3 clock used as LPUART1 clock source */
421 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR3_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
422 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR3_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
423 #define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) /*!< LSE clock used as LPUART1 clock source */
424 /**
425 * @}
426 */
427
428 /** @defgroup RCC_LL_EC_I2C_CLKSOURCE Peripheral I2Cx clock source selection
429 * @{
430 */
431 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
432 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
433 #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_1 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
434 #define LL_RCC_I2C3_CLKSOURCE_PCLK7 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U)) /*!< PCLK7 clock used as I2C3 clock source */
435 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | (RCC_CCIPR3_I2C3SEL_0 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
436 #define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | (RCC_CCIPR3_I2C3SEL_1 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
437 /**
438 * @}
439 */
440
441 /** @defgroup RCC_LL_EC_SPI_CLKSOURCE Peripheral SPIx clock source selection
442 * @{
443 */
444 #if defined(SPI1)
445 #define LL_RCC_SPI1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U)) /*!< PCLK2 clock used as SPI1 clock source */
446 #define LL_RCC_SPI1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL_0 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SYSCLK clock used as SPI1 clock source */
447 #define LL_RCC_SPI1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL_1 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< HSI clock used as SPI1 clock source */
448 #endif /* SPI1 */
449 #define LL_RCC_SPI3_CLKSOURCE_PCLK7 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U)) /*!< PCLK3 clock used as SPI3 clock source */
450 #define LL_RCC_SPI3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL_0 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SYSCLK clock used as SPI3 clock source */
451 #define LL_RCC_SPI3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL_1 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< HSI clock used as SPI3 clock source */
452 /**
453 * @}
454 */
455
456 /** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIMx clock source selection
457 * @{
458 */
459 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK7 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U)) /*!< PCLK7 clock used as LPTIM1 clock source */
460 #define LL_RCC_LPTIM1_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | (RCC_CCIPR3_LPTIM1SEL_0 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSI clock used as LPTIM1 clock source */
461 #define LL_RCC_LPTIM1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | (RCC_CCIPR3_LPTIM1SEL_1 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< HSI clock used as LPTIM1 clock source */
462 #define LL_RCC_LPTIM1_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | (RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSE clock used as LPTIM1 clock source */
463 #if defined(LPTIM2)
464 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U)) /*!< PCLK1 clock used as LPTIM2 clock source */
465 #define LL_RCC_LPTIM2_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | (RCC_CCIPR1_LPTIM2SEL_0 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSI clock used as LPTIM2 clock source */
466 #define LL_RCC_LPTIM2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | (RCC_CCIPR1_LPTIM2SEL_1 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< HSI clock used as LPTIM2 clock source */
467 #define LL_RCC_LPTIM2_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | (RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSE clock used as LPTIM2 clock source */
468 #endif /* LPTIM2 */
469 /**
470 * @}
471 */
472
473 #if defined(SAI1)
474 /** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral SAIx clock source selection
475 * @{
476 */
477 #define LL_RCC_SAI1_CLKSOURCE_PLL1P (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLL1P clock used as SAI1 clock source */
478 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLL1Q clock used as SAI1 clock source */
479 #define LL_RCC_SAI1_CLKSOURCE_SYSCLK ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< System clock used as SAI1 clock source */
480 #define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */
481 #define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */
482 /**
483 * @}
484 */
485 #endif /* SAI1 */
486
487
488 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
489 * @{
490 */
491 #define LL_RCC_RNG_CLKSOURCE_LSE 0U /*!< LSE clock used as RNG clock source */
492 #define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR2_RNGSEL_0 /*!< LSI clock used as RNG clock source */
493 #define LL_RCC_RNG_CLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1 /*!< HSI clock used as RNG clock source */
494 #define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_CCIPR2_RNGSEL_1 | RCC_CCIPR2_RNGSEL_0) /*!< PLL1Q clock used as RNG clock source */
495 /**
496 * @}
497 */
498
499 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC4 clock source selection
500 * @{
501 */
502 #define LL_RCC_ADC_CLKSOURCE_HCLK 0U /*!< HCLK1 clock used as ADC4 clock source */
503 #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR3_ADCSEL_0 /*!< SYSCLK clock used as ADC4 clock source */
504 #define LL_RCC_ADC_CLKSOURCE_PLL1P RCC_CCIPR3_ADCSEL_1 /*!< PLL1P clock used as ADC4 clock source */
505 #define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR3_ADCSEL_2 /*!< HSI clock used as ADC4 clock source */
506 #define LL_RCC_ADC_CLKSOURCE_HSE (RCC_CCIPR3_ADCSEL_1 | RCC_CCIPR3_ADCSEL_0) /*!< HSE clock used as ADC4 clock source */
507 /**
508 * @}
509 */
510
511
512 /** @defgroup RCC_LL_EC_TIM_INPUT_CAPTURE_CLOCKSource TIM Input capture clock source selection
513 * @{
514 */
515 #define LL_RCC_TIMIC_CLKSOURCE_NONE 0U /*!< No clock available for TIM16/TIM17 and LPTIM2 input capture */
516 #define LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 RCC_CCIPR1_TIMICSEL /*!< HSI/256 selected for TIM16/TIM17 and LPTIM2 input capture */
517 /**
518 * @}
519 */
520
521 /** @defgroup RCC_LL_EC_USART Peripheral USARTx get clock source
522 * @{
523 */
524 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR1_USART1SEL /*!< USART1 Clock source selection */
525 #if defined(USART2)
526 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR1_USART2SEL /*!< USART2 Clock source selection */
527 #endif /* USART2 */
528 /**
529 * @}
530 */
531
532 /** @defgroup RCC_LL_EC_SPI Peripheral SPIx get clock source
533 * @{
534 */
535 #if defined(SPI1)
536 #define LL_RCC_SPI1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SPI1 Clock source selection */
537 #endif /* SPI1 */
538 #define LL_RCC_SPI3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SPI3 Clock source selection */
539 /**
540 * @}
541 */
542
543 /** @defgroup RCC_LL_EC_LPUART Peripheral LPUARTx get clock source
544 * @{
545 */
546 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR3_LPUART1SEL /*!< LPUART1 Clock source selection */
547 /**
548 * @}
549 */
550
551 /** @defgroup RCC_LL_EC_I2C Peripheral I2Cx get clock source
552 * @{
553 */
554 #if defined(I2C1)
555 #define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
556 #endif /* I2C1 */
557 #define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | (RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
558
559 /**
560 * @}
561 */
562
563 /** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIMx get clock source
564 * @{
565 */
566 #define LL_RCC_LPTIM1_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | (RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LPTIM1 Clock source selection */
567 #if defined(LPTIM2)
568 #define LL_RCC_LPTIM2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | (RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LPTIM2 Clock source selection */
569 #endif /* LPTIM2 */
570 /**
571 * @}
572 */
573
574 #if defined(SAI1)
575 /** @defgroup RCC_LL_EC_SAI Peripheral SAIx get clock source
576 * @{
577 */
578 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */
579 /**
580 * @}
581 */
582 #endif /* SAI1 */
583
584 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
585 * @{
586 */
587 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR2_RNGSEL /*!< RNG Clock source selection */
588 /**
589 * @}
590 */
591
592 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
593 * @{
594 */
595 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR3_ADCSEL /*!< ADCs Clock source selection */
596 /**
597 * @}
598 */
599
600 /** @defgroup RCC_LL_EC_PLL1SOURCE PLL1 entry clock source
601 * @{
602 */
603 #define LL_RCC_PLL1SOURCE_NONE 0U /*!< No clock selected as PLL1 entry clock source */
604 #define LL_RCC_PLL1SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 /*!< HSI clock selected as PLL1 entry clock source */
605 #define LL_RCC_PLL1SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) /*!< HSE clock selected as PLL1 entry clock source */
606 /**
607 * @}
608 */
609
610 /** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input ranges
611 * @{
612 */
613 #define LL_RCC_PLLINPUTRANGE_4_8 2U /*!< VCO input range: 4 to 8 MHz */
614 #define LL_RCC_PLLINPUTRANGE_8_16 3U /*!< VCO input range: 8 to 16 MHz */
615 /**
616 * @}
617 */
618
619 /** @defgroup RCC_LL_EC_PLL1RCLKPRESTEP PLL1RCLK prescaler steps division
620 * @{
621 */
622 #define LL_RCC_PLL1RCLK_2_STEP_DIV 0U /*!< PLL1RCLK 2-step division */
623 #define LL_RCC_PLL1RCLK_3_STEP_DIV RCC_PLL1CFGR_PLL1RCLKPRESTEP /*!< PLL1RCLK 3-step division */
624 /**
625 * @}
626 */
627
628 /** @defgroup RCC_LSE_Trimming LSE Trimming
629 * @{
630 */
631 #define LL_RCC_LSETRIMMING_R 0U /*!< Current source resistance R */
632 #define LL_RCC_LSETRIMMING_3_4_R RCC_BDCR1_LSETRIM_0 /*!< Current source resistance 3/4 * R */
633 #define LL_RCC_LSETRIMMING_2_3_R RCC_BDCR1_LSETRIM_1 /*!< Current source resistance 2/3 * R */
634 #define LL_RCC_LSETRIMMING_1_2_R RCC_BDCR1_LSETRIM /*!< Current source resistance 1/2 * R */
635 /**
636 * @}
637 */
638
639 /** @defgroup RCC_LL_EF_Security_Services Security Services
640 * @note Only available when system implements security (TZEN=1)
641 * @{
642 */
643 #define LL_RCC_ALL_NSEC 0U /*!< No security on RCC resources (default) */
644 #define LL_RCC_ALL_SEC RCC_SECURE_MASK /*!< Security on all RCC resources */
645
646 #define LL_RCC_HSI_SEC RCC_SECCFGR_HSISEC /*!< HSI clock configuration secure-only access */
647 #define LL_RCC_HSI_NSEC 0U /*!< HSI clock configuration secure/non-secure access */
648 #define LL_RCC_HSE_SEC RCC_SECCFGR_HSESEC /*!< HSE clock configuration secure-only access */
649 #define LL_RCC_HSE_NSEC 0U /*!< HSE clock configuration secure/non-secure access */
650 #define LL_RCC_LSE_SEC RCC_SECCFGR_LSESEC /*!< LSE clock configuration secure-only access */
651 #define LL_RCC_LSE_NSEC 0U /*!< LSE clock configuration secure/non-secure access */
652 #define LL_RCC_LSI_SEC RCC_SECCFGR_LSISEC /*!< LSI clock configuration secure-only access */
653 #define LL_RCC_LSI_NSEC 0U /*!< LSI clock configuration secure/non-secure access */
654 #define LL_RCC_SYSCLK_SEC RCC_SECCFGR_SYSCLKSEC /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure-only access */
655 #define LL_RCC_SYSCLK_NSEC 0U /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure/non-secure access */
656 #define LL_RCC_PRESCALERS_SEC RCC_SECCFGR_PRESCSEC /*!< AHBx/APBx prescaler configuration secure-only access */
657 #define LL_RCC_PRESCALERS_NSEC 0U /*!< AHBx/APBx prescaler configuration secure/non-secure access */
658 #define LL_RCC_PLL1_SEC RCC_SECCFGR_PLL1SEC /*!< PLL1 clock configuration secure-only access */
659 #define LL_RCC_PLL1_NSEC 0U /*!< PLL1 clock configuration secure/non-secure access */
660 #define LL_RCC_RESET_FLAGS_SEC RCC_SECCFGR_RMVFSEC /*!< Remove reset flag secure-only access */
661 #define LL_RCC_RESET_FLAGS_NSEC 0U /*!< Remove reset flag secure/non-secure access */
662 /**
663 * @}
664 */
665
666 /**
667 * @}
668 */
669
670 /* Exported macro ------------------------------------------------------------*/
671 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
672 * @{
673 */
674
675 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
676 * @{
677 */
678
679 /**
680 * @brief Write a value in RCC register
681 * @param __REG__ Register to be written
682 * @param __VALUE__ Value to be written in the register
683 * @retval None
684 */
685 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
686
687 /**
688 * @brief Read a value in RCC register
689 * @param __REG__ Register to be read
690 * @retval Register value
691 */
692 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
693 /**
694 * @}
695 */
696
697 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
698 * @{
699 */
700
701 /**
702 * @brief Helper macro to calculate the PLL1RCLK frequency on system domain
703 * @note ex: @ref __LL_RCC_CALC_PLL1RCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (),
704 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetR ());
705 * @param __INPUTFREQ__ PLL1 Input frequency (based on HSE/HSI)
706 * @param __PLL1M__ parameter can be a value between 1 and 16
707 * @param __PLL1N__ parameter can be a value between 4 and 512
708 * @param __PLL1R__ parameter can be a value between 1 and 128
709 * @retval PLL1R clock frequency (in Hz)
710 */
711
712 #define __LL_RCC_CALC_PLL1RCLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1R__) ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1R__))
713
714 /**
715 * @brief Helper macro to calculate the PLL1PCLK frequency
716 * @note ex: @ref __LL_RCC_CALC_PLL1PCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (),
717 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetP ());
718 * @param __INPUTFREQ__ PLL1 Input frequency (based on HSE/HSI)
719 * @param __PLL1M__ parameter can be a value between 1 and 16
720 * @param __PLL1N__ parameter can be a value between 4 and 512
721 * @param __PLL1P__ parameter can be a value between 2 and 128
722 * @retval PLL1P clock frequency (in Hz)
723 */
724 #define __LL_RCC_CALC_PLL1PCLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1P__) ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1P__))
725
726 /**
727 * @brief Helper macro to calculate the PLL1QCLK frequency
728 * @note ex: @ref __LL_RCC_CALC_PLL1QCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (),
729 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetQ ());
730 * @param __INPUTFREQ__ PLL1 Input frequency (based on HSE/HSI)
731 * @param __PLL1M__ parameter can be a value between 1 and 16
732 * @param __PLL1N__ parameter can be a value between 4 and 512
733 * @param __PLL1Q__ parameter can be a value between 1 and 128
734 * @retval PLL1 clock frequency (in Hz)
735 */
736 #define __LL_RCC_CALC_PLL1QCLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1Q__) ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1Q__))
737
738 /**
739 * @brief Helper macro to calculate the HCLK frequency
740 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
741 * @param __AHBPRESCALER__ This parameter can be one of the following values:
742 * @arg @ref LL_RCC_SYSCLK_DIV_1
743 * @arg @ref LL_RCC_SYSCLK_DIV_2
744 * @arg @ref LL_RCC_SYSCLK_DIV_4
745 * @arg @ref LL_RCC_SYSCLK_DIV_8
746 * @arg @ref LL_RCC_SYSCLK_DIV_16
747 * @retval HCLK clock frequency (in Hz)
748 */
749 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos])
750
751 /**
752 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
753 * @param __HCLKFREQ__ HCLK frequency
754 * @param __APB1PRESCALER__ This parameter can be one of the following values:
755 * @arg @ref LL_RCC_APB1_DIV_1
756 * @arg @ref LL_RCC_APB1_DIV_2
757 * @arg @ref LL_RCC_APB1_DIV_4
758 * @arg @ref LL_RCC_APB1_DIV_8
759 * @arg @ref LL_RCC_APB1_DIV_16
760 * @retval PCLK1 clock frequency (in Hz)
761 */
762 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[((__APB1PRESCALER__) & RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos]))
763
764 /**
765 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
766 * @param __HCLKFREQ__ HCLK frequency
767 * @param __APB2PRESCALER__ This parameter can be one of the following values:
768 * @arg @ref LL_RCC_APB2_DIV_1
769 * @arg @ref LL_RCC_APB2_DIV_2
770 * @arg @ref LL_RCC_APB2_DIV_4
771 * @arg @ref LL_RCC_APB2_DIV_8
772 * @arg @ref LL_RCC_APB2_DIV_16
773 * @retval PCLK2 clock frequency (in Hz)
774 */
775 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR2_PPRE2_Pos])
776
777
778 /**
779 * @brief Helper macro to calculate the PCLK7 frequency (ABP7)
780 * @param __HCLKFREQ__ HCLK frequency
781 * @param __APB7PRESCALER__ This parameter can be one of the following values:
782 * @arg @ref LL_RCC_APB7_DIV_1
783 * @arg @ref LL_RCC_APB7_DIV_2
784 * @arg @ref LL_RCC_APB7_DIV_4
785 * @arg @ref LL_RCC_APB7_DIV_8
786 * @arg @ref LL_RCC_APB7_DIV_16
787 * @retval PCLK3 clock frequency (in Hz)
788 */
789 #define __LL_RCC_CALC_PCLK7_FREQ(__HCLKFREQ__, __APB7PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB7PRESCALER__) >> RCC_CFGR3_PPRE7_Pos])
790
791 /**
792 * @}
793 */
794
795 /**
796 * @}
797 */
798
799 /* Exported functions --------------------------------------------------------*/
800 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
801 * @{
802 */
803
804 /** @defgroup RCC_LL_EF_HSE HSE
805 * @{
806 */
807
808 /**
809 * @brief Enable HSE crystal oscillator (HSE ON)
810 * @rmtoll CR HSEON LL_RCC_HSE_Enable
811 * @retval None
812 */
LL_RCC_HSE_Enable(void)813 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
814 {
815 SET_BIT(RCC->CR, RCC_CR_HSEON);
816 }
817
818 /**
819 * @brief Disable HSE crystal oscillator (HSE ON)
820 * @rmtoll CR HSEON LL_RCC_HSE_Disable
821 * @retval None
822 */
LL_RCC_HSE_Disable(void)823 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
824 {
825 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
826 }
827
828 /**
829 * @brief Check if HSE oscillator Ready
830 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
831 * @retval State of bit (1 or 0).
832 */
LL_RCC_HSE_IsReady(void)833 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
834 {
835 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
836 }
837
838 /**
839 * @brief Enable HSE clock prescaler for sysclk
840 * @rmtoll CR HSEPRE LL_RCC_HSE_EnablePrescaler
841 * @note Control the division factor of the HSE32 clock for sysclk
842 * @retval None
843 */
LL_RCC_HSE_EnablePrescaler(void)844 __STATIC_INLINE void LL_RCC_HSE_EnablePrescaler(void)
845 {
846 SET_BIT(RCC->CR, RCC_CR_HSEPRE);
847 }
848
849 /**
850 * @brief Check if HSE clock prescaler for sysclk is enabled
851 * @rmtoll CR HSEPRE LL_RCC_HSE_IsEnabledPrescaler
852 * @note Check if the HSE32 clock for sysclk is divided by 2 or not
853 * @retval State of bit (1 or 0).
854 */
LL_RCC_HSE_IsEnabledPrescaler(void)855 __STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabledPrescaler(void)
856 {
857 return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == RCC_CR_HSEPRE) ? 1UL : 0UL);
858 }
859
860 /**
861 * @brief Disable HSE clock prescaler for sysclk
862 * @rmtoll CR HSEPRE LL_RCC_HSE_DisablePrescaler
863 * @note Control the division factor of the HSE32 clock for sysclk
864 * @retval None
865 */
LL_RCC_HSE_DisablePrescaler(void)866 __STATIC_INLINE void LL_RCC_HSE_DisablePrescaler(void)
867 {
868 CLEAR_BIT(RCC->CR, RCC_CR_HSEPRE);
869 }
870
871 /**
872 * @brief Enable the Clock Security System.
873 * @rmtoll CR HSECSSON LL_RCC_HSE_EnableCSS
874 * @retval None
875 */
LL_RCC_HSE_EnableCSS(void)876 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
877 {
878 SET_BIT(RCC->CR, RCC_CR_HSECSSON);
879 }
880
881 /**
882 * @brief Set HSE clock trimming
883 * @note user-programmable capacitor trimming value.
884 * @rmtoll ECSCR1 HSETRIM LL_RCC_HSE_SetClockTrimming
885 * @param Value Between Min_Data = 0 and Max_Data = 63
886 * @retval None
887 */
LL_RCC_HSE_SetClockTrimming(uint32_t Value)888 __STATIC_INLINE void LL_RCC_HSE_SetClockTrimming(uint32_t Value)
889 {
890 MODIFY_REG(RCC->ECSCR1, RCC_ECSCR1_HSETRIM, Value << RCC_ECSCR1_HSETRIM_Pos);
891 }
892
893 /**
894 * @brief Get HSE clock trimming
895 * @rmtoll ECSCR1 HSETRIM LL_RCC_HSE_GetClockTrimming
896 * @retval Between Min_Data = 0 and Max_Data = 63
897 */
LL_RCC_HSE_GetClockTrimming(void)898 __STATIC_INLINE uint32_t LL_RCC_HSE_GetClockTrimming(void)
899 {
900 return (uint32_t)(READ_BIT(RCC->ECSCR1, RCC_ECSCR1_HSETRIM) >> RCC_ECSCR1_HSETRIM_Pos);
901 }
902 /**
903 * @}
904 */
905
906 /** @defgroup RCC_LL_EF_HSI HSI
907 * @{
908 */
909
910 /**
911 * @brief Enable HSI even in stop mode
912 * @note HSI oscillator is forced ON even in Stop mode
913 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
914 * @retval None
915 */
LL_RCC_HSI_EnableInStopMode(void)916 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
917 {
918 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
919 }
920
921 /**
922 * @brief Disable HSI in stop mode
923 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
924 * @retval None
925 */
LL_RCC_HSI_DisableInStopMode(void)926 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
927 {
928 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
929 }
930
931 /**
932 * @brief Check if HSI is enabled in stop mode
933 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
934 * @retval State of bit (1 or 0).
935 */
LL_RCC_HSI_IsEnabledInStopMode(void)936 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
937 {
938 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL);
939 }
940
941 /**
942 * @brief Enable HSI oscillator
943 * @rmtoll CR HSION LL_RCC_HSI_Enable
944 * @retval None
945 */
LL_RCC_HSI_Enable(void)946 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
947 {
948 SET_BIT(RCC->CR, RCC_CR_HSION);
949 }
950
951 /**
952 * @brief Disable HSI oscillator
953 * @rmtoll CR HSION LL_RCC_HSI_Disable
954 * @retval None
955 */
LL_RCC_HSI_Disable(void)956 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
957 {
958 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
959 }
960
961 /**
962 * @brief Check if HSI clock is ready
963 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
964 * @retval State of bit (1 or 0).
965 */
LL_RCC_HSI_IsReady(void)966 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
967 {
968 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
969 }
970
971 /**
972 * @brief Get HSI Calibration value
973 * @note When HSITRIM is written, HSICAL is updated with the sum of
974 * HSITRIM and the factory trim value
975 * @rmtoll ICSCR3 HSICAL LL_RCC_HSI_GetCalibration
976 * @retval Between Min_Data = 0 and Max_Data = 4095
977 */
LL_RCC_HSI_GetCalibration(void)978 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
979 {
980 return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSICAL) >> RCC_ICSCR3_HSICAL_Pos);
981 }
982
983 /**
984 * @brief Set HSI Calibration trimming
985 * @note user-programmable trimming value that is added to the HSICAL
986 * @note Default value is 16, which, when added to the HSICAL value,
987 * should trim the HSI to 16 MHz +/- 1 %
988 * @rmtoll ICSCR3 HSITRIM LL_RCC_HSI_SetCalibTrimming
989 * @param Value Between Min_Data = 0 and Max_Data = 31
990 * @retval None
991 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)992 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
993 {
994 MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, Value << RCC_ICSCR3_HSITRIM_Pos);
995 }
996
997 /**
998 * @brief Get HSI Calibration trimming
999 * @rmtoll ICSCR3 HSITRIM LL_RCC_HSI_GetCalibTrimming
1000 * @retval Between Min_Data = 0 and Max_Data = 31
1001 */
LL_RCC_HSI_GetCalibTrimming(void)1002 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1003 {
1004 return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos);
1005 }
1006
1007 /**
1008 * @}
1009 */
1010
1011 /** @defgroup RCC_LL_EF_LSE LSE
1012 * @{
1013 */
1014
1015 /**
1016 * @brief Enable Low Speed External (LSE) crystal.
1017 * @rmtoll BDCR1 LSEON LL_RCC_LSE_Enable
1018 * @retval None
1019 */
LL_RCC_LSE_Enable(void)1020 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1021 {
1022 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEON);
1023 }
1024
1025 /**
1026 * @brief Disable Low Speed External (LSE) crystal.
1027 * @rmtoll BDCR1 LSEON LL_RCC_LSE_Disable
1028 * @retval None
1029 */
LL_RCC_LSE_Disable(void)1030 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1031 {
1032 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEON);
1033 }
1034
1035 /**
1036 * @brief Enable external clock source (LSE bypass).
1037 * @rmtoll BDCR1 LSEBYP LL_RCC_LSE_EnableBypass
1038 * @retval None
1039 */
LL_RCC_LSE_EnableBypass(void)1040 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1041 {
1042 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP);
1043 }
1044
1045 /**
1046 * @brief Disable external clock source (LSE bypass).
1047 * @rmtoll BDCR1 LSEBYP LL_RCC_LSE_DisableBypass
1048 * @retval None
1049 */
LL_RCC_LSE_DisableBypass(void)1050 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1051 {
1052 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP);
1053 }
1054
1055 /**
1056 * @brief Enable LSE clock glitch filter.
1057 * @rmtoll BDCR1 LSEGFON LL_RCC_LSE_EnableGlitchFilter
1058 * @retval None
1059 */
LL_RCC_LSE_EnableGlitchFilter(void)1060 __STATIC_INLINE void LL_RCC_LSE_EnableGlitchFilter(void)
1061 {
1062 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON);
1063 }
1064
1065 /**
1066 * @brief Disable LSE clock glitch filter.
1067 * @rmtoll BDCR1 LSEGFON LL_RCC_LSE_DisableGlitchFilter
1068 * @retval None
1069 */
LL_RCC_LSE_DisableGlitchFilter(void)1070 __STATIC_INLINE void LL_RCC_LSE_DisableGlitchFilter(void)
1071 {
1072 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON);
1073 }
1074
1075 /**
1076 * @brief Set LSE trimming
1077 * @rmtoll BDCR1 LSETRIM LL_RCC_LSE_SetClockTrimming
1078 * @param LSETrim This parameter can be one of the following values:
1079 * @arg @ref LL_RCC_LSETRIMMING_R
1080 * @arg @ref LL_RCC_LSETRIMMING_3_4_R
1081 * @arg @ref LL_RCC_LSETRIMMING_2_3_R
1082 * @arg @ref LL_RCC_LSETRIMMING_1_2_R
1083 * @retval None
1084 */
LL_RCC_LSE_SetClockTrimming(uint32_t LSETrim)1085 __STATIC_INLINE void LL_RCC_LSE_SetClockTrimming(uint32_t LSETrim)
1086 {
1087 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSETRIM, LSETrim);
1088 }
1089
1090 /**
1091 * @brief Get LSE trimming
1092 * @rmtoll BDCR1 LSETRIM LL_RCC_LSE_GetClockTrimming
1093 * @retval Returned value can be one of the following values:
1094 * @arg @ref LL_RCC_LSETRIMMING_R
1095 * @arg @ref LL_RCC_LSETRIMMING_3_4_R
1096 * @arg @ref LL_RCC_LSETRIMMING_2_3_R
1097 * @arg @ref LL_RCC_LSETRIMMING_1_2_R
1098 * @retval None
1099 */
LL_RCC_LSE_GetClockTrimming(void)1100 __STATIC_INLINE uint32_t LL_RCC_LSE_GetClockTrimming(void)
1101 {
1102 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_LSETRIM));
1103 }
1104
1105 /**
1106 * @brief Set LSE oscillator drive capability
1107 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1108 * @rmtoll BDCR1 LSEDRV LL_RCC_LSE_SetDriveCapability
1109 * @param LSEDrive This parameter can be one of the following values:
1110 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1111 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1112 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1113 * @retval None
1114 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1115 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1116 {
1117 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSEDRV, LSEDrive);
1118 }
1119
1120 /**
1121 * @brief Get LSE oscillator drive capability
1122 * @rmtoll BDCR1 LSEDRV LL_RCC_LSE_GetDriveCapability
1123 * @retval Returned value can be one of the following values:
1124 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1125 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1126 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1127 */
LL_RCC_LSE_GetDriveCapability(void)1128 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1129 {
1130 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_LSEDRV));
1131 }
1132
1133 /**
1134 * @brief Enable Clock security system on LSE.
1135 * @rmtoll BDCR1 LSECSSON LL_RCC_LSE_EnableCSS
1136 * @retval None
1137 */
LL_RCC_LSE_EnableCSS(void)1138 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1139 {
1140 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSON);
1141 }
1142
1143 /**
1144 * @brief Disable Clock security system on LSE.
1145 * @note Clock security system can be disabled only after a LSE
1146 * failure detection. In that case it MUST be disabled by software.
1147 * @rmtoll BDCR1 LSECSSON LL_RCC_LSE_DisableCSS
1148 * @retval None
1149 */
LL_RCC_LSE_DisableCSS(void)1150 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1151 {
1152 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSON);
1153 }
1154
1155 /**
1156 * @brief Check if LSE oscillator Ready
1157 * @rmtoll BDCR1 LSERDY LL_RCC_LSE_IsReady
1158 * @retval State of bit (1 or 0).
1159 */
LL_RCC_LSE_IsReady(void)1160 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1161 {
1162 return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSERDY) == RCC_BDCR1_LSERDY) ? 1UL : 0UL);
1163 }
1164
1165 /**
1166 * @brief Enable LSE oscillator propagation for system clock
1167 * @rmtoll BDCR1 LSESYSEN LL_RCC_LSE_EnablePropagation
1168 * @retval None
1169 */
LL_RCC_LSE_EnablePropagation(void)1170 __STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void)
1171 {
1172 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSESYSEN);
1173 }
1174
1175 /**
1176 * @brief Disable LSE oscillator propagation for system clock
1177 * @rmtoll BDCR1 LSESYSEN LL_RCC_LSE_DisablePropagation
1178 * @retval None
1179 */
LL_RCC_LSE_DisablePropagation(void)1180 __STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void)
1181 {
1182 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSESYSEN);
1183 }
1184
1185 /**
1186 * @brief Check if LSE oscillator propagation for system clock Ready
1187 * @rmtoll BDCR1 LSESYSRDY LL_RCC_LSE_IsPropagationReady
1188 * @retval State of bit (1 or 0).
1189 */
LL_RCC_LSE_IsPropagationReady(void)1190 __STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationReady(void)
1191 {
1192 return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSESYSRDY) == RCC_BDCR1_LSESYSRDY) ? 1UL : 0UL);
1193 }
1194
1195 /**
1196 * @brief Check if CSS on LSE failure Detection
1197 * @rmtoll BDCR1 LSECSSD LL_RCC_LSE_IsCSSDetected
1198 * @retval State of bit (1 or 0).
1199 */
LL_RCC_LSE_IsCSSDetected(void)1200 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1201 {
1202 return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSD) == RCC_BDCR1_LSECSSD) ? 1UL : 0UL);
1203 }
1204
1205 /**
1206 * @}
1207 */
1208
1209 /** @defgroup RCC_LL_EF_LSI1 LSI1
1210 * @{
1211 */
1212
1213 /**
1214 * @brief Enable LSI1 Oscillator
1215 * @rmtoll BDCR1 LSI1ON LL_RCC_LSI1_Enable
1216 * @retval None
1217 */
LL_RCC_LSI1_Enable(void)1218 __STATIC_INLINE void LL_RCC_LSI1_Enable(void)
1219 {
1220 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSI1ON);
1221 }
1222
1223 /**
1224 * @brief Disable LSI1 Oscillator
1225 * @rmtoll BDCR1 LSI1ON LL_RCC_LSI1_Disable
1226 * @retval None
1227 */
LL_RCC_LSI1_Disable(void)1228 __STATIC_INLINE void LL_RCC_LSI1_Disable(void)
1229 {
1230 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSI1ON);
1231 }
1232
1233 /**
1234 * @brief Check if LSI1 is Ready
1235 * @rmtoll BDCR1 LSI1RDY LL_RCC_LSI1_IsReady
1236 * @retval State of bit (1 or 0).
1237 */
LL_RCC_LSI1_IsReady(void)1238 __STATIC_INLINE uint32_t LL_RCC_LSI1_IsReady(void)
1239 {
1240 return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSI1RDY) == RCC_BDCR1_LSI1RDY) ? 1UL : 0UL);
1241 }
1242
1243 /**
1244 * @brief Set LSI1 prescaler
1245 * @rmtoll BDCR1 LSI1PREDIV LL_RCC_LSI1_SetPrescaler
1246 * @param LSI1Prescaler This parameter can be one of the following values:
1247 * @arg @ref LL_RCC_LSI_DIV_1
1248 * @arg @ref LL_RCC_LSI_DIV_128
1249 * @retval None
1250 */
LL_RCC_LSI1_SetPrescaler(uint32_t LSI1Prescaler)1251 __STATIC_INLINE void LL_RCC_LSI1_SetPrescaler(uint32_t LSI1Prescaler)
1252 {
1253 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV, LSI1Prescaler);
1254 }
1255
1256 /**
1257 * @brief Get LSI1 prescaler
1258 * @rmtoll BDCR1 LSI1PREDIV LL_RCC_LSI1_GetPrescaler
1259 * @retval Returned value can be one of the following values:
1260 * @arg @ref LL_RCC_LSI_DIV_1
1261 * @arg @ref LL_RCC_LSI_DIV_128
1262 */
LL_RCC_LSI1_GetPrescaler(void)1263 __STATIC_INLINE uint32_t LL_RCC_LSI1_GetPrescaler(void)
1264 {
1265 return (READ_BIT(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV));
1266 }
1267
1268 /**
1269 * @}
1270 */
1271
1272 #if defined(RCC_LSI2_SUPPORT)
1273 /** @defgroup RCC_LL_EF_LSI2 LSI2
1274 * @{
1275 */
1276
1277 /**
1278 * @brief Enable LSI2 Oscillator
1279 * @rmtoll BDCR1 LSI2ON LL_RCC_LSI2_Enable
1280 * @retval None
1281 */
LL_RCC_LSI2_Enable(void)1282 __STATIC_INLINE void LL_RCC_LSI2_Enable(void)
1283 {
1284 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSI2ON);
1285 }
1286
1287 /**
1288 * @brief Disable LSI2 Oscillator
1289 * @rmtoll BDCR1 LSI2ON LL_RCC_LSI2_Disable
1290 * @retval None
1291 */
LL_RCC_LSI2_Disable(void)1292 __STATIC_INLINE void LL_RCC_LSI2_Disable(void)
1293 {
1294 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSI2ON);
1295 }
1296
1297 /**
1298 * @brief Check if LSI2 is Ready
1299 * @rmtoll BDCR1 LSI2RDY LL_RCC_LSI2_IsReady
1300 * @retval State of bit (1 or 0).
1301 */
LL_RCC_LSI2_IsReady(void)1302 __STATIC_INLINE uint32_t LL_RCC_LSI2_IsReady(void)
1303 {
1304 return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSI2RDY) == RCC_BDCR1_LSI2RDY) ? 1UL : 0UL);
1305 }
1306
1307 /**
1308 * @brief Configure LSI2 oscillator temperature sensitivity
1309 * @rmtoll BDCR2 LSI2CFG LL_RCC_LSI2_SetTempSensitivity
1310 * @param Sensitivity This parameter can be one of the following values:
1311 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_80
1312 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_50
1313 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_20
1314 * @retval None
1315 */
LL_RCC_LSI2_SetTempSensitivity(uint32_t Sensitivity)1316 __STATIC_INLINE void LL_RCC_LSI2_SetTempSensitivity(uint32_t Sensitivity)
1317 {
1318 MODIFY_REG(RCC->BDCR2, RCC_BDCR2_LSI2CFG, Sensitivity);
1319 }
1320
1321 /**
1322 * @brief Get LSI2 oscillator temperature sensitivity
1323 * @rmtoll BDCR2 LSI2CFG LL_RCC_LSI2_GetTempSensitivity
1324 * @retval Returned value can be one of the following values:
1325 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_80
1326 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_50
1327 * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_20
1328 */
LL_RCC_LSI2_GetTempSensitivity(void)1329 __STATIC_INLINE uint32_t LL_RCC_LSI2_GetTempSensitivity(void)
1330 {
1331 return (uint32_t)(READ_BIT(RCC->BDCR2, RCC_BDCR2_LSI2CFG));
1332 }
1333
1334 /**
1335 * @brief Configure LSI2 operating mode configuration
1336 * @rmtoll BDCR2 LSI2MODE LL_RCC_LSI2_SetOperatingMode
1337 * @param Mode This parameter can be one of the following values:
1338 * @arg @ref LL_RCC_LSI2_NOMINAL_MODE
1339 * @arg @ref LL_RCC_LSI2_LOWPOWER_MODE
1340 * @arg @ref LL_RCC_LSI2_ULTRALOWPOWER_MODE
1341 * @retval None
1342 */
LL_RCC_LSI2_SetOperatingMode(uint32_t Mode)1343 __STATIC_INLINE void LL_RCC_LSI2_SetOperatingMode(uint32_t Mode)
1344 {
1345 MODIFY_REG(RCC->BDCR2, RCC_BDCR2_LSI2MODE, Mode);
1346 }
1347
1348 /**
1349 * @brief Get LSI2 oscillator operating mode
1350 * @rmtoll BDCR2 LSI2MODE LL_RCC_LSI2_GetOperatingMode
1351 * @retval Returned value can be one of the following values:
1352 * @arg @ref LL_RCC_LSI2_NOMINAL_MODE
1353 * @arg @ref LL_RCC_LSI2_LOWPOWER_MODE
1354 * @arg @ref LL_RCC_LSI2_ULTRALOWPOWER_MODE
1355 */
LL_RCC_LSI2_GetOperatingMode(void)1356 __STATIC_INLINE uint32_t LL_RCC_LSI2_GetOperatingMode(void)
1357 {
1358 return (uint32_t)(READ_BIT(RCC->BDCR2, RCC_BDCR2_LSI2MODE));
1359 }
1360
1361 /**
1362 * @}
1363 */
1364 #endif /* LSI2 */
1365
1366 /** @defgroup RCC_LL_EF_LSCO LSCO
1367 * @{
1368 */
1369
1370 /**
1371 * @brief Enable Low speed clock
1372 * @rmtoll BDCR1 LSCOEN LL_RCC_LSCO_Enable
1373 * @retval None
1374 */
LL_RCC_LSCO_Enable(void)1375 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
1376 {
1377 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSCOEN);
1378 }
1379
1380 /**
1381 * @brief Disable Low speed clock
1382 * @rmtoll BDCR1 LSCOEN LL_RCC_LSCO_Disable
1383 * @retval None
1384 */
LL_RCC_LSCO_Disable(void)1385 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
1386 {
1387 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSCOEN);
1388 }
1389
1390 /**
1391 * @brief Configure Low speed clock selection
1392 * @rmtoll BDCR1 LSCOSEL LL_RCC_LSCO_SetSource
1393 * @param Source This parameter can be one of the following values:
1394 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1395 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1396 * @retval None
1397 */
LL_RCC_LSCO_SetSource(uint32_t Source)1398 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
1399 {
1400 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSCOSEL, Source);
1401 }
1402
1403 /**
1404 * @brief Get Low speed clock selection
1405 * @rmtoll BDCR1 LSCOSEL LL_RCC_LSCO_GetSource
1406 * @retval Returned value can be one of the following values:
1407 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1408 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1409 */
LL_RCC_LSCO_GetSource(void)1410 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
1411 {
1412 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_LSCOSEL));
1413 }
1414
1415 /**
1416 * @}
1417 */
1418
1419 /** @defgroup RCC_LL_EF_System System
1420 * @{
1421 */
1422
1423 /**
1424 * @brief Configure the system clock source
1425 * @rmtoll CFGR1 SW LL_RCC_SetSysClkSource
1426 * @param Source This parameter can be one of the following values:
1427 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1428 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1429 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1R
1430 * @retval None
1431 */
LL_RCC_SetSysClkSource(uint32_t Source)1432 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1433 {
1434 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, Source);
1435 }
1436
1437 /**
1438 * @brief Get the system clock source
1439 * @rmtoll CFGR1 SWS LL_RCC_GetSysClkSource
1440 * @retval Returned value can be one of the following values:
1441 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1442 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1443 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1R
1444 */
LL_RCC_GetSysClkSource(void)1445 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1446 {
1447 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS));
1448 }
1449
1450 /**
1451 * @brief Set AHB prescaler
1452 * @rmtoll CFGR2 HPRE LL_RCC_SetAHBPrescaler
1453 * @param Prescaler This parameter can be one of the following values:
1454 * @arg @ref LL_RCC_SYSCLK_DIV_1
1455 * @arg @ref LL_RCC_SYSCLK_DIV_2
1456 * @arg @ref LL_RCC_SYSCLK_DIV_4
1457 * @arg @ref LL_RCC_SYSCLK_DIV_8
1458 * @arg @ref LL_RCC_SYSCLK_DIV_16
1459 * @retval None
1460 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)1461 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1462 {
1463 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, Prescaler);
1464 }
1465
1466 /**
1467 * @brief Set Systick clock source
1468 * @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource
1469 * @param SystickSource This parameter can be one of the following values:
1470 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI
1471 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE
1472 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8
1473 * @retval None
1474 */
LL_RCC_SetSystickClockSource(uint32_t SystickSource)1475 __STATIC_INLINE void LL_RCC_SetSystickClockSource(uint32_t SystickSource)
1476 {
1477 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, SystickSource);
1478 }
1479
1480 /**
1481 * @brief Set APB1 prescaler
1482 * @rmtoll CFGR2 PPRE1 LL_RCC_SetAPB1Prescaler
1483 * @param Prescaler This parameter can be one of the following values:
1484 * @arg @ref LL_RCC_APB1_DIV_1
1485 * @arg @ref LL_RCC_APB1_DIV_2
1486 * @arg @ref LL_RCC_APB1_DIV_4
1487 * @arg @ref LL_RCC_APB1_DIV_8
1488 * @arg @ref LL_RCC_APB1_DIV_16
1489 * @retval None
1490 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)1491 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1492 {
1493 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, Prescaler);
1494 }
1495
1496 /**
1497 * @brief Set APB2 prescaler
1498 * @rmtoll CFGR2 PPRE2 LL_RCC_SetAPB2Prescaler
1499 * @param Prescaler This parameter can be one of the following values:
1500 * @arg @ref LL_RCC_APB2_DIV_1
1501 * @arg @ref LL_RCC_APB2_DIV_2
1502 * @arg @ref LL_RCC_APB2_DIV_4
1503 * @arg @ref LL_RCC_APB2_DIV_8
1504 * @arg @ref LL_RCC_APB2_DIV_16
1505 * @retval None
1506 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)1507 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
1508 {
1509 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, Prescaler);
1510 }
1511
1512 /**
1513 * @brief Set APB7 prescaler
1514 * @rmtoll CFGR3 PPRE7 LL_RCC_SetAPB7Prescaler
1515 * @param Prescaler This parameter can be one of the following values:
1516 * @arg @ref LL_RCC_APB7_DIV_1
1517 * @arg @ref LL_RCC_APB7_DIV_2
1518 * @arg @ref LL_RCC_APB7_DIV_4
1519 * @arg @ref LL_RCC_APB7_DIV_8
1520 * @arg @ref LL_RCC_APB7_DIV_16
1521 * @retval None
1522 */
LL_RCC_SetAPB7Prescaler(uint32_t Prescaler)1523 __STATIC_INLINE void LL_RCC_SetAPB7Prescaler(uint32_t Prescaler)
1524 {
1525 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE7, Prescaler);
1526 }
1527
1528 /**
1529 * @brief Set AHB5 prescaler when SYSCLK is PLL1R
1530 * @rmtoll CFGR4 HPRE5 LL_RCC_SetAHB5Prescaler
1531 * @param Prescaler This parameter can be one of the following values:
1532 * @arg @ref LL_RCC_AHB5_DIV_1
1533 * @arg @ref LL_RCC_AHB5_DIV_2
1534 * @arg @ref LL_RCC_AHB5_DIV_3
1535 * @arg @ref LL_RCC_AHB5_DIV_4
1536 * @arg @ref LL_RCC_AHB5_DIV_6
1537 * @retval None
1538 */
LL_RCC_SetAHB5Prescaler(uint32_t Prescaler)1539 __STATIC_INLINE void LL_RCC_SetAHB5Prescaler(uint32_t Prescaler)
1540 {
1541 MODIFY_REG(RCC->CFGR4, RCC_CFGR4_HPRE5, Prescaler);
1542 }
1543
1544 /**
1545 * @brief Set AHB5 divider when SYSCLK is HSI or HSE
1546 * @rmtoll CFGR4 HDIV5 LL_RCC_SetAHB5Divider
1547 * @param Divider This parameter can be one of the following values:
1548 * @arg @ref LL_RCC_AHB5_DIVIDER_1
1549 * @arg @ref LL_RCC_AHB5_DIVIDER_2
1550 * @retval None
1551 */
LL_RCC_SetAHB5Divider(uint32_t Divider)1552 __STATIC_INLINE void LL_RCC_SetAHB5Divider(uint32_t Divider)
1553 {
1554 MODIFY_REG(RCC->CFGR4, RCC_CFGR4_HDIV5, Divider);
1555 }
1556
1557 /**
1558 * @brief Get AHB prescaler
1559 * @rmtoll CFGR2 HPRE LL_RCC_GetAHBPrescaler
1560 * @retval Returned value can be one of the following values:
1561 * @arg @ref LL_RCC_SYSCLK_DIV_1
1562 * @arg @ref LL_RCC_SYSCLK_DIV_2
1563 * @arg @ref LL_RCC_SYSCLK_DIV_4
1564 * @arg @ref LL_RCC_SYSCLK_DIV_8
1565 * @arg @ref LL_RCC_SYSCLK_DIV_16
1566 */
LL_RCC_GetAHBPrescaler(void)1567 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1568 {
1569 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_HPRE));
1570 }
1571
1572 /**
1573 * @brief Get Sysctick clock source
1574 * @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource
1575 * @retval Returned value can be one of the following values:
1576 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI
1577 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE
1578 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8
1579 */
LL_RCC_GetSystickClockSource(void)1580 __STATIC_INLINE uint32_t LL_RCC_GetSystickClockSource(void)
1581 {
1582 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL));
1583 }
1584
1585 /**
1586 * @brief Get APB1 prescaler
1587 * @rmtoll CFGR2 PPRE1 LL_RCC_GetAPB1Prescaler
1588 * @retval Returned value can be one of the following values:
1589 * @arg @ref LL_RCC_APB1_DIV_1
1590 * @arg @ref LL_RCC_APB1_DIV_2
1591 * @arg @ref LL_RCC_APB1_DIV_4
1592 * @arg @ref LL_RCC_APB1_DIV_8
1593 * @arg @ref LL_RCC_APB1_DIV_16
1594 */
LL_RCC_GetAPB1Prescaler(void)1595 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1596 {
1597 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE1));
1598 }
1599
1600 /**
1601 * @brief Get APB2 prescaler
1602 * @rmtoll CFGR2 PPRE2 LL_RCC_GetAPB2Prescaler
1603 * @retval Returned value can be one of the following values:
1604 * @arg @ref LL_RCC_APB2_DIV_1
1605 * @arg @ref LL_RCC_APB2_DIV_2
1606 * @arg @ref LL_RCC_APB2_DIV_4
1607 * @arg @ref LL_RCC_APB2_DIV_8
1608 * @arg @ref LL_RCC_APB2_DIV_16
1609 */
LL_RCC_GetAPB2Prescaler(void)1610 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
1611 {
1612 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE2));
1613 }
1614
1615 /**
1616 * @brief Get APB7 prescaler
1617 * @rmtoll CFGR3 PPRE7 LL_RCC_GetAPB7Prescaler
1618 * @retval Returned value can be one of the following values:
1619 * @arg @ref LL_RCC_APB7_DIV_1
1620 * @arg @ref LL_RCC_APB7_DIV_2
1621 * @arg @ref LL_RCC_APB7_DIV_4
1622 * @arg @ref LL_RCC_APB7_DIV_8
1623 * @arg @ref LL_RCC_APB7_DIV_16
1624 */
LL_RCC_GetAPB7Prescaler(void)1625 __STATIC_INLINE uint32_t LL_RCC_GetAPB7Prescaler(void)
1626 {
1627 return (uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_PPRE7));
1628 }
1629
1630 /**
1631 * @brief Get AHB5 prescaler when SYSCLK is PLL1R
1632 * @rmtoll CFGR4 HPRE5 LL_RCC_GetAHB5Prescaler
1633 * @retval Returned value can be one of the following values:
1634 * @arg @ref LL_RCC_AHB5_DIV_1
1635 * @arg @ref LL_RCC_AHB5_DIV_2
1636 * @arg @ref LL_RCC_AHB5_DIV_3
1637 * @arg @ref LL_RCC_AHB5_DIV_4
1638 * @arg @ref LL_RCC_AHB5_DIV_6
1639 */
LL_RCC_GetAHB5Prescaler(void)1640 __STATIC_INLINE uint32_t LL_RCC_GetAHB5Prescaler(void)
1641 {
1642 return (uint32_t)(READ_BIT(RCC->CFGR4, RCC_CFGR4_HPRE5));
1643 }
1644
1645 /**
1646 * @brief Get AHB5 divider when SYSCLK is HSI or HSE
1647 * @rmtoll CFGR4 HDIV5 LL_RCC_GetAHB5Divider
1648 * @retval Returned value can be one of the following values:
1649 * @arg @ref LL_RCC_AHB5_DIVIDER_1
1650 * @arg @ref LL_RCC_AHB5_DIVIDER_2
1651 */
LL_RCC_GetAHB5Divider(void)1652 __STATIC_INLINE uint32_t LL_RCC_GetAHB5Divider(void)
1653 {
1654 return (uint32_t)(READ_BIT(RCC->CFGR4, RCC_CFGR4_HDIV5));
1655 }
1656 /**
1657 * @}
1658 */
1659
1660 /** @defgroup RCC_LL_EF_RADIO RADIO
1661 * @{
1662 */
1663
1664 /**
1665 * @brief Enable the 2.4 GHz RADIO baseband clock
1666 * @rmtoll RADIOENR BBCLKEN LL_RCC_RADIO_EnableBasebandClock
1667 * @retval None
1668 */
LL_RCC_RADIO_EnableBasebandClock(void)1669 __STATIC_INLINE void LL_RCC_RADIO_EnableBasebandClock(void)
1670 {
1671 SET_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN);
1672 }
1673
1674 /**
1675 * @brief Disable the 2.4 GHz RADIO baseband clock
1676 * @rmtoll RADIOENR BBCLKEN LL_RCC_RADIO_DisableBasebandClock
1677 * @retval None
1678 */
LL_RCC_RADIO_DisableBasebandClock(void)1679 __STATIC_INLINE void LL_RCC_RADIO_DisableBasebandClock(void)
1680 {
1681 CLEAR_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN);
1682 }
1683
1684 /**
1685 * @brief Check if 2.4 GHz RADIO baseband clock is enabled
1686 * @rmtoll RADIOENR BBCLKEN LL_RCC_RADIO_IsEnabledBasebandClock
1687 * @retval State of bit (1 or 0).
1688 */
LL_RCC_RADIO_IsEnabledBasebandClock(void)1689 __STATIC_INLINE uint32_t LL_RCC_RADIO_IsEnabledBasebandClock(void)
1690 {
1691 return ((READ_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN) == RCC_RADIOENR_BBCLKEN) ? 1UL : 0UL);
1692 }
1693
1694 /**
1695 * @brief Disable the 2.4 GHz RADIO bus clock and HSE32 oscillator by 2.4 GHz RADIO sleep timer wakeup event
1696 * @rmtoll RADIOENR STRADIOCLKON LL_RCC_RADIO_DisableSleepTimerClock
1697 * @retval None
1698 */
LL_RCC_RADIO_DisableSleepTimerClock(void)1699 __STATIC_INLINE void LL_RCC_RADIO_DisableSleepTimerClock(void)
1700 {
1701 CLEAR_BIT(RCC->RADIOENR, RCC_RADIOENR_STRADIOCLKON);
1702 }
1703
1704 /**
1705 * @brief Check if 2.4 GHz RADIO bus clock and HSE32 oscillator are enabled by 2.4 GHz RADIO sleep timer wakeup event
1706 * @rmtoll RADIOENR STRADIOCLKON LL_RCC_RADIO_IsEnabledSleepTimerClock
1707 * @retval State of bit (1 or 0).
1708 */
LL_RCC_RADIO_IsEnabledSleepTimerClock(void)1709 __STATIC_INLINE uint32_t LL_RCC_RADIO_IsEnabledSleepTimerClock(void)
1710 {
1711 return ((READ_BIT(RCC->RADIOENR, RCC_RADIOENR_STRADIOCLKON) == RCC_RADIOENR_STRADIOCLKON) ? 1UL : 0UL);
1712 }
1713
1714 /**
1715 * @brief Check if 2.4 GHz RADIO bus clock is ready
1716 * @rmtoll RADIOENR RADIOCLKRDY LL_RCC_RADIO_IsBusClockReady
1717 * @retval State of bit (1 or 0).
1718 */
LL_RCC_RADIO_IsBusClockReady(void)1719 __STATIC_INLINE uint32_t LL_RCC_RADIO_IsBusClockReady(void)
1720 {
1721 return ((READ_BIT(RCC->RADIOENR, RCC_RADIOENR_RADIOCLKRDY) == RCC_RADIOENR_RADIOCLKRDY) ? 1UL : 0UL);
1722 }
1723
1724 /**
1725 * @brief Set the 2.4 GHz RADIO sleep timer kernel clock
1726 * @rmtoll BDCR1 RADIOSTSEL LL_RCC_RADIO_SetSleepTimerClockSource
1727 * @param Source This parameter can be one of the following values:
1728 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_NONE
1729 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_LSE
1730 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_LSI (*)
1731 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_HSE_DIV1000
1732 *
1733 * (*) value not defined in all devices.
1734 * @retval None
1735 */
LL_RCC_RADIO_SetSleepTimerClockSource(uint32_t Source)1736 __STATIC_INLINE void LL_RCC_RADIO_SetSleepTimerClockSource(uint32_t Source)
1737 {
1738 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_RADIOSTSEL, Source);
1739 }
1740
1741 /**
1742 * @brief Get the 2.4 GHz RADIO sleep timer kernel clock
1743 * @rmtoll BDCR1 RADIOSTSEL LL_RCC_RADIO_GetSleepTimerClockSource
1744 * @retval Returned value can be one of the following values:
1745 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_NONE
1746 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_LSE
1747 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_LSI (*)
1748 * @arg @ref LL_RCC_RADIOSLEEPSOURCE_HSE_DIV1000
1749 *
1750 * (*) value not defined in all devices.
1751 */
LL_RCC_RADIO_GetSleepTimerClockSource(void)1752 __STATIC_INLINE uint32_t LL_RCC_RADIO_GetSleepTimerClockSource(void)
1753 {
1754 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_RADIOSTSEL));
1755 }
1756
1757 /**
1758 * @}
1759 */
1760
1761 /** @defgroup RCC_LL_EF_MCO MCO
1762 * @{
1763 */
1764
1765 /**
1766 * @brief Configure MCOx
1767 * @rmtoll CFGR1 MCOSEL LL_RCC_ConfigMCO\n
1768 * CFGR1 MCOPRE LL_RCC_ConfigMCO
1769 * @param MCOxSource This parameter can be one of the following values:
1770 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1771 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1772 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1773 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1774 * @arg @ref LL_RCC_MCO1SOURCE_PLL1R
1775 * @arg @ref LL_RCC_MCO1SOURCE_PLL1Q
1776 * @arg @ref LL_RCC_MCO1SOURCE_PLL1P
1777 * @arg @ref LL_RCC_MCO1SOURCE_LSI
1778 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1779 * @arg @ref LL_RCC_MCO1SOURCE_HCLK5
1780 * @param MCOxPrescaler This parameter can be one of the following values:
1781 * @arg @ref LL_RCC_MCO1_DIV_1
1782 * @arg @ref LL_RCC_MCO1_DIV_2
1783 * @arg @ref LL_RCC_MCO1_DIV_4
1784 * @arg @ref LL_RCC_MCO1_DIV_8
1785 * @arg @ref LL_RCC_MCO1_DIV_16
1786 * @retval None
1787 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)1788 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1789 {
1790 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE, MCOxSource | MCOxPrescaler);
1791 }
1792
1793 /**
1794 * @}
1795 */
1796
1797 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1798 * @{
1799 */
1800
1801 /**
1802 * @brief Configure USARTx clock source
1803 * @rmtoll CCIPR1 USART1SEL LL_RCC_SetUSARTClockSource\n
1804 * CCIPR1 USART2SEL LL_RCC_SetUSARTClockSource\n
1805 * @param USARTxSource This parameter can be one of the following values:
1806 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
1807 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1808 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1809 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1810 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
1811 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
1812 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
1813 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
1814 * @retval None
1815 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)1816 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
1817 {
1818 MODIFY_REG(RCC->CCIPR1, USARTxSource >> 16U, (USARTxSource & 0x0000FFFFU));
1819 }
1820
1821 /**
1822 * @brief Configure LPUARTx clock source
1823 * @rmtoll CCIPR3 LPUART1SEL LL_RCC_SetLPUARTClockSource
1824 * @param LPUARTxSource This parameter can be one of the following values:
1825 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK7
1826 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1827 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1828 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1829 * @retval None
1830 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)1831 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
1832 {
1833 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, LPUARTxSource);
1834 }
1835
1836 /**
1837 * @brief Configure I2Cx clock source
1838 * @rmtoll CCIPR1 I2C1SEL LL_RCC_SetI2CClockSource\n
1839 * CCIPR3 I2C3SEL LL_RCC_SetI2CClockSource\n
1840 * @param I2CxSource This parameter can be one of the following values:
1841 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1842 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1843 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1844 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK7
1845 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
1846 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
1847 * @retval None
1848 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)1849 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
1850 {
1851 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2CxSource >> 24U));
1852 MODIFY_REG(*reg, 3U << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((I2CxSource & 0x000000FFU) << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU)));
1853 }
1854
1855 /**
1856 * @brief Configure SPIx clock source
1857 * @rmtoll CCIPR1 SPI1SEL LL_RCC_SetSPIClockSource\n
1858 * CCIPR3 SPI3SEL LL_RCC_SetSPIClockSource\n
1859 * @param SPIxSource This parameter can be one of the following values:
1860 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
1861 * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK
1862 * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
1863 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK7
1864 * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK
1865 * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
1866 * @retval None
1867 */
LL_RCC_SetSPIClockSource(uint32_t SPIxSource)1868 __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource)
1869 {
1870 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIxSource >> 24U));
1871 MODIFY_REG(*reg, 3U << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((SPIxSource & 0x000000FFU) << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU)));
1872 }
1873
1874 /**
1875 * @brief Configure LPTIMx clock source
1876 * @rmtoll CCIPR3 LPTIM1SEL LL_RCC_SetLPTIMClockSource\n
1877 * CCIPR1 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n
1878 * @param LPTIMxSource This parameter can be one of the following values:
1879 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK7
1880 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
1881 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
1882 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
1883 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
1884 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
1885 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
1886 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
1887 * @retval None
1888 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)1889 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
1890 {
1891 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMxSource >> 24U));
1892 MODIFY_REG(*reg, 3U << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((LPTIMxSource & 0x000000FFU) << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU)));
1893 }
1894
1895
1896 /**
1897 * @brief Configure SAIx clock source
1898 * @rmtoll CCIPR2 SAI1SEL LL_RCC_SetSAIClockSource\n
1899 * @param SAIxSource This parameter can be one of the following values:
1900 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1P(*)
1901 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q(*)
1902 * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK(*)
1903 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN(*)
1904 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI(*)
1905 * (*) Feature not available on all devices of the family
1906 * @retval None
1907 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)1908 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
1909 {
1910 MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU));
1911 }
1912
1913 /**
1914 * @brief Configure RNG clock source
1915 * @rmtoll CCIPR2 RNGSEL LL_RCC_SetRNGClockSource
1916 * @param RNGxSource This parameter can be one of the following values:
1917 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
1918 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
1919 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI
1920 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
1921 * @retval None
1922 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)1923 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
1924 {
1925 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, RNGxSource);
1926 }
1927
1928 /**
1929 * @brief Configure ADC clock source
1930 * @rmtoll CCIPR3 ADCSEL LL_RCC_SetADCClockSource
1931 * @param ADC4Source This parameter can be one of the following values:
1932 * @arg @ref LL_RCC_ADC_CLKSOURCE_HCLK
1933 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
1934 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL1P
1935 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSE
1936 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
1937 * @retval None
1938 */
LL_RCC_SetADCClockSource(uint32_t ADC4Source)1939 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADC4Source)
1940 {
1941 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCSEL, ADC4Source);
1942 }
1943
1944
1945
1946 /**
1947 * @brief Get USARTx clock source
1948 * @rmtoll CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource\n
1949 * CCIPR1 USART2SEL LL_RCC_GetUSARTClockSource\n
1950 * @param USARTx This parameter can be one of the following values:
1951 * @arg @ref LL_RCC_USART1_CLKSOURCE
1952 * @arg @ref LL_RCC_USART2_CLKSOURCE
1953 * @retval Returned value can be one of the following values:
1954 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
1955 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1956 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1957 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1958 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
1959 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
1960 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
1961 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
1962 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)1963 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
1964 {
1965 return (uint32_t)(READ_BIT(RCC->CCIPR1, USARTx) | (USARTx << 16U));
1966 }
1967
1968 /**
1969 * @brief Get LPUARTx clock source
1970 * @rmtoll CCIPR3 LPUART1SEL LL_RCC_GetLPUARTClockSource
1971 * @param LPUARTx This parameter can be one of the following values:
1972 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
1973 * @retval Returned value can be one of the following values:
1974 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK7
1975 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1976 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1977 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1978 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)1979 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
1980 {
1981 return (uint32_t)(READ_BIT(RCC->CCIPR3, LPUARTx));
1982 }
1983
1984 /**
1985 * @brief Get I2Cx clock source
1986 * @rmtoll CCIPR1 I2C1SEL LL_RCC_GetI2CClockSource\n
1987 * CCIPR3 I2C3SEL LL_RCC_GetI2CClockSource\n
1988 * @param I2Cx This parameter can be one of the following values:
1989 * @arg @ref LL_RCC_I2C1_CLKSOURCE
1990 * @arg @ref LL_RCC_I2C3_CLKSOURCE
1991 * @retval Returned value can be one of the following values:
1992 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1993 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1994 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1995 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK7
1996 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
1997 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
1998 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)1999 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
2000 {
2001 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2Cx >> 24U));
2002 return (uint32_t)((READ_BIT(*reg, (3UL << (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (I2Cx & 0xFFFF0000UL));
2003 }
2004
2005 /**
2006 * @brief Get SPIx clock source
2007 * @rmtoll CCIPR1 SPI1SEL LL_RCC_GetSPIClockSource\n
2008 * CCIPR3 SPI3SEL LL_RCC_GetSPIClockSource
2009 * @param SPIx This parameter can be one of the following values:
2010 * @arg @ref LL_RCC_SPI1_CLKSOURCE
2011 * @arg @ref LL_RCC_SPI3_CLKSOURCE
2012 * @retval Returned value can be one of the following values:
2013 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
2014 * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK
2015 * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
2016 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK7
2017 * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK
2018 * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
2019 */
LL_RCC_GetSPIClockSource(uint32_t SPIx)2020 __STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t SPIx)
2021 {
2022 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIx >> 24U));
2023 return (uint32_t)((READ_BIT(*reg, (3UL << (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (SPIx & 0xFFFF0000UL));
2024 }
2025
2026 /**
2027 * @brief Get LPTIMx clock source
2028 * @rmtoll CCIPR3 LPTIM1SEL LL_RCC_GetLPTIMClockSource\n
2029 * CCIPR1 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n
2030 * @param LPTIMx This parameter can be one of the following values:
2031 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2032 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
2033 * @retval Returned value can be one of the following values:
2034 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK7
2035 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2036 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2037 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2038 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2039 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2040 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2041 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2042 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)2043 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
2044 {
2045 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMx >> 24U));
2046 return (uint32_t)((READ_BIT(*reg, (3UL << (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (LPTIMx & 0xFFFF0000UL));
2047 }
2048
2049 /**
2050 * @brief Set Tim Input capture clock source
2051 * @rmtoll CCIPR1 TIMICSEL LL_RCC_SetTIMICClockSource
2052 * @param TIMICSource This parameter can be one of the following combined values:
2053 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE
2054 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256
2055 * @note HSI clock without division is also available when TIMICSEL[2] is 1.
2056 * @retval None
2057 */
LL_RCC_SetTIMICClockSource(uint32_t TIMICSource)2058 __STATIC_INLINE void LL_RCC_SetTIMICClockSource(uint32_t TIMICSource)
2059 {
2060 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL, TIMICSource);
2061 }
2062
2063 /**
2064 * @brief Get Tim Input capture clock source
2065 * @rmtoll CCIPR1 TIMICSEL LL_RCC_GetTIMICClockSource
2066 * @retval Returned value can be one of the following combined values:
2067 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE
2068 * @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256
2069 */
LL_RCC_GetTIMICClockSource(void)2070 __STATIC_INLINE uint32_t LL_RCC_GetTIMICClockSource(void)
2071 {
2072 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL));
2073 }
2074
2075 /**
2076 * @brief Get SAIx clock source
2077 * @rmtoll CCIPR2 SAI1SEL LL_RCC_GetSAIClockSource\n
2078 * @param SAIx This parameter can be one of the following values:
2079 * @arg @ref LL_RCC_SAI1_CLKSOURCE(*)
2080 * @retval Returned value can be one of the following values:
2081 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1P(*)
2082 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q(*)
2083 * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK(*)
2084 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN(*)
2085 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI(*)
2086 * (*) Feature not available on all devices of the family
2087 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)2088 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
2089 {
2090 return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U));
2091 }
2092
2093 /**
2094 * @brief Get RNGx clock source
2095 * @rmtoll CCIPR2 RNGSEL LL_RCC_GetRNGClockSource
2096 * @param RNGx This parameter can be one of the following values:
2097 * @arg @ref LL_RCC_RNG_CLKSOURCE
2098 * @retval Returned value can be one of the following values:
2099 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
2100 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
2101 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI
2102 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
2103 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)2104 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
2105 {
2106 return (uint32_t)(READ_BIT(RCC->CCIPR2, RNGx));
2107 }
2108
2109 /**
2110 * @brief Get ADCx clock source
2111 * @rmtoll CCIPR3 ADCSEL LL_RCC_GetADCClockSource
2112 * @param ADCx This parameter can be one of the following values:
2113 * @arg @ref LL_RCC_ADC_CLKSOURCE
2114 * @retval Returned value can be one of the following values:
2115 * @arg @ref LL_RCC_ADC_CLKSOURCE_HCLK
2116 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2117 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL1P
2118 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSE
2119 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
2120 */
LL_RCC_GetADCClockSource(uint32_t ADCx)2121 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
2122 {
2123 return (uint32_t)(READ_BIT(RCC->CCIPR3, ADCx));
2124 }
2125
2126 /**
2127 * @}
2128 */
2129
2130 /** @defgroup RCC_LL_EF_RTC RTC
2131 * @{
2132 */
2133
2134 /**
2135 * @brief Set RTC Clock Source
2136 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
2137 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
2138 * set). The BDRST bit can be used to reset them.
2139 * @rmtoll BDCR1 RTCSEL LL_RCC_SetRTCClockSource
2140 * @param Source This parameter can be one of the following values:
2141 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2142 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2143 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2144 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2145 * @retval None
2146 */
LL_RCC_SetRTCClockSource(uint32_t Source)2147 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2148 {
2149 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_RTCSEL, Source);
2150 }
2151
2152 /**
2153 * @brief Get RTC Clock Source
2154 * @rmtoll BDCR1 RTCSEL LL_RCC_GetRTCClockSource
2155 * @retval Returned value can be one of the following values:
2156 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2157 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2158 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2159 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2160 */
LL_RCC_GetRTCClockSource(void)2161 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2162 {
2163 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_RTCSEL));
2164 }
2165
2166 /**
2167 * @brief Force the Backup domain reset
2168 * @rmtoll BDCR1 BDRST LL_RCC_ForceBackupDomainReset
2169 * @retval None
2170 */
LL_RCC_ForceBackupDomainReset(void)2171 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2172 {
2173 SET_BIT(RCC->BDCR1, RCC_BDCR1_BDRST);
2174 }
2175
2176 /**
2177 * @brief Release the Backup domain reset
2178 * @rmtoll BDCR1 BDRST LL_RCC_ReleaseBackupDomainReset
2179 * @retval None
2180 */
LL_RCC_ReleaseBackupDomainReset(void)2181 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2182 {
2183 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_BDRST);
2184 }
2185
2186 /**
2187 * @}
2188 */
2189
2190 /** @defgroup RCC_LL_EF_PLL1 PLL1
2191 * @{
2192 */
2193
2194 /**
2195 * @brief Enable PLL1
2196 * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable
2197 * @retval None
2198 */
LL_RCC_PLL1_Enable(void)2199 __STATIC_INLINE void LL_RCC_PLL1_Enable(void)
2200 {
2201 SET_BIT(RCC->CR, RCC_CR_PLL1ON);
2202 }
2203
2204 /**
2205 * @brief Disable PLL1
2206 * @note Cannot be disabled if the PLL1 clock is used as the system clock
2207 * @rmtoll CR PLL1ON LL_RCC_PLL1_Disable
2208 * @retval None
2209 */
LL_RCC_PLL1_Disable(void)2210 __STATIC_INLINE void LL_RCC_PLL1_Disable(void)
2211 {
2212 CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
2213 }
2214
2215 /**
2216 * @brief Check if PLL1 Ready
2217 * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady
2218 * @retval State of bit (1 or 0).
2219 */
LL_RCC_PLL1_IsReady(void)2220 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
2221 {
2222 return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == RCC_CR_PLL1RDY) ? 1UL : 0UL);
2223 }
2224
2225 /**
2226 * @brief Enable prescaler division on PLL1RCLK for SYSCLK
2227 * @rmtoll PLL1CFGR PLL1RCLKPRE LL_RCC_PLL1_EnablePLL1RCLKDivision
2228 * @retval None
2229 */
LL_RCC_PLL1_EnablePLL1RCLKDivision(void)2230 __STATIC_INLINE void LL_RCC_PLL1_EnablePLL1RCLKDivision(void)
2231 {
2232 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRE);
2233 }
2234
2235 /**
2236 * @brief Disable PLL1RCLK for SYSCLK prescaler division
2237 * @rmtoll PLL1CFGR PLL1RCLKPRE LL_RCC_PLL1_DisablePLL1RCLKDivision
2238 * @retval None
2239 */
LL_RCC_PLL1_DisablePLL1RCLKDivision(void)2240 __STATIC_INLINE void LL_RCC_PLL1_DisablePLL1RCLKDivision(void)
2241 {
2242 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRE);
2243 }
2244
2245 /**
2246 * @brief Set the division step of PLL1RCLK clock for SYSCLK
2247 * @rmtoll PLL1CFGR PLL1RCLKPRESTEP LL_RCC_PLL1_SetPLL1RCLKDivisionStep
2248 * @param Step This parameter can be one of the following values:
2249 * @arg @ref LL_RCC_PLL1RCLK_2_STEP_DIV
2250 * @arg @ref LL_RCC_PLL1RCLK_3_STEP_DIV
2251 * @retval None
2252 */
LL_RCC_PLL1_SetPLL1RCLKDivisionStep(uint32_t Step)2253 __STATIC_INLINE void LL_RCC_PLL1_SetPLL1RCLKDivisionStep(uint32_t Step)
2254 {
2255 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRESTEP, Step);
2256 }
2257
2258 /**
2259 * @brief Get the division step of PLL1RCLK clock for SYSCLK
2260 * @rmtoll PLL1CFGR PLL1RCLKPRESTEP LL_RCC_PLL1_GetPLL1RCLKDivisionStep
2261 * @retval Returned value can be one of the following values:
2262 * @arg @ref LL_RCC_PLL1RCLK_2_STEP_DIV
2263 * @arg @ref LL_RCC_PLL1RCLK_3_STEP_DIV
2264 */
LL_RCC_PLL1_GetPLL1RCLKDivisionStep(void)2265 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetPLL1RCLKDivisionStep(void)
2266 {
2267 return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRESTEP));
2268 }
2269
2270 /**
2271 * @brief Check if prescaler division on PLL1RCLK for SYSCLK is ready
2272 * @rmtoll PLL1CFGR PLL1RCLKPRERDY LL_RCC_PLL1_IsPLL1RCLKDivisionReady
2273 * @retval State of bit (1 or 0).
2274 */
LL_RCC_PLL1_IsPLL1RCLKDivisionReady(void)2275 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsPLL1RCLKDivisionReady(void)
2276 {
2277 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRERDY) == RCC_PLL1CFGR_PLL1RCLKPRERDY) ? 1UL : 0UL);
2278 }
2279
2280 /**
2281 * @brief Configure PLL1R used for SYSCLK Domain
2282 * @note PLL1 Source, PLLM, PLLN and PLLR can be written only when PLL1 is disabled.
2283 * @note PLLN/PLLR can be written only when PLL1 is disabled.
2284 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_PLL1R\n
2285 * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_PLL1R\n
2286 * PLL1DIVR PLL1N LL_RCC_PLL1_ConfigDomain_PLL1R\n
2287 * PLL1DIVR PLL1R LL_RCC_PLL1_ConfigDomain_PLL1R
2288 * @param Source This parameter can be one of the following values:
2289 * @arg @ref LL_RCC_PLL1SOURCE_NONE
2290 * @arg @ref LL_RCC_PLL1SOURCE_HSI
2291 * @arg @ref LL_RCC_PLL1SOURCE_HSE
2292 * @param PLLM parameter can be a value between 1 and 16
2293 * @param PLLR parameter can be a value between 1 and 128
2294 * @param PLLN parameter can be a value between 4 and 512
2295 * @retval None
2296 */
LL_RCC_PLL1_ConfigDomain_PLL1R(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)2297 __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_PLL1R(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
2298 {
2299 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos));
2300 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1R, ((PLLN - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLLR - 1UL) << RCC_PLL1DIVR_PLL1R_Pos));
2301 }
2302
2303 /**
2304 * @brief Configure PLL1P
2305 * @note PLL1 Source, PLLM, PLLN and PLLPDIV can be written only when PLL1 is disabled.
2306 * @note This can be selected for ADC and SAI
2307 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_PLL1P\n
2308 * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_PLL1P\n
2309 * PLL1DIVR PLL1N LL_RCC_PLL1_ConfigDomain_PLL1P\n
2310 * PLL1DIVR PLL1P LL_RCC_PLL1_ConfigDomain_PLL1P
2311 * @param Source This parameter can be one of the following values:
2312 * @arg @ref LL_RCC_PLL1SOURCE_NONE
2313 * @arg @ref LL_RCC_PLL1SOURCE_HSI
2314 * @arg @ref LL_RCC_PLL1SOURCE_HSE
2315 * @param PLLM parameter can be a value between 1 and 16
2316 * @param PLLN parameter can be a value between 4 and 512
2317 * @param PLLP parameter can be a value between 2 and 128
2318 * @retval None
2319 */
LL_RCC_PLL1_ConfigDomain_PLL1P(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)2320 __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_PLL1P(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
2321 {
2322 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos));
2323 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P, ((PLLN - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLLP - 1UL) << RCC_PLL1DIVR_PLL1P_Pos));
2324 }
2325
2326 /**
2327 * @brief Configure PLL1Q
2328 * @note PLL1 Source, PLLM, PLLN and PLLQ can be written only when PLL1 is disabled.
2329 * @note This can be selected for RNG and SAI
2330 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_PLL1Q\n
2331 * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_PLL1Q\n
2332 * PLL1DIVR PLL1N LL_RCC_PLL1_ConfigDomain_PLL1Q\n
2333 * PLL1DIVR PLL1Q LL_RCC_PLL1_ConfigDomain_PLL1Q
2334 * @param Source This parameter can be one of the following values:
2335 * @arg @ref LL_RCC_PLL1SOURCE_NONE
2336 * @arg @ref LL_RCC_PLL1SOURCE_HSI
2337 * @arg @ref LL_RCC_PLL1SOURCE_HSE
2338 * @param PLLM parameter can be a value between 1 and 16
2339 * @param PLLN parameter can be a value between 4 and 512
2340 * @param PLLQ parameter can be a value between 1 and 128
2341 * @retval None
2342 */
LL_RCC_PLL1_ConfigDomain_PLL1Q(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2343 __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_PLL1Q(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2344 {
2345 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos));
2346 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1Q, ((PLLN - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLLQ - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos));
2347 }
2348
2349 /**
2350 * @brief Configure PLL1 clock source
2351 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_SetMainSource
2352 * @param PLL1Source This parameter can be one of the following values:
2353 * @arg @ref LL_RCC_PLL1SOURCE_NONE
2354 * @arg @ref LL_RCC_PLL1SOURCE_HSI
2355 * @arg @ref LL_RCC_PLL1SOURCE_HSE
2356 * @retval None
2357 */
LL_RCC_PLL1_SetMainSource(uint32_t PLL1Source)2358 __STATIC_INLINE void LL_RCC_PLL1_SetMainSource(uint32_t PLL1Source)
2359 {
2360 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, PLL1Source);
2361 }
2362
2363 /**
2364 * @brief Get the oscillator used as PLL1 clock source.
2365 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_GetMainSource
2366 * @retval Returned value can be one of the following values:
2367 * @arg @ref LL_RCC_PLL1SOURCE_NONE
2368 * @arg @ref LL_RCC_PLL1SOURCE_HSI
2369 * @arg @ref LL_RCC_PLL1SOURCE_HSE
2370 */
LL_RCC_PLL1_GetMainSource(void)2371 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetMainSource(void)
2372 {
2373 return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC));
2374 }
2375
2376 /**
2377 * @brief Set PLL1 multiplication factor for VCO
2378 * @rmtoll PLL1DIVR PLL1N LL_RCC_PLL1_SetN
2379 * @param PLL1N parameter can be a value between 4 and 512
2380 */
LL_RCC_PLL1_SetN(uint32_t PLL1N)2381 __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t PLL1N)
2382 {
2383 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N, (PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos);
2384 }
2385
2386 /**
2387 * @brief Get PLL1 multiplication factor for VCO
2388 * @rmtoll PLL1DIVR PLL1N LL_RCC_PLL1_GetN
2389 * @retval Between 4 and 512
2390 */
LL_RCC_PLL1_GetN(void)2391 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
2392 {
2393 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1UL);
2394 }
2395
2396
2397 /**
2398 * @brief Set PLL1 division factor for PLL1P
2399 * @note Used for PLL1PCLK selected ADC and SAI
2400 * @rmtoll PLL1DIVR PLL1P LL_RCC_PLL1_SetP
2401 * @param PLL1P parameter can be a value between 2 and 128
2402 */
LL_RCC_PLL1_SetP(uint32_t PLL1P)2403 __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t PLL1P)
2404 {
2405 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P, (PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos);
2406 }
2407
2408 /**
2409 * @brief Get PLL1 division factor for PLL1P
2410 * @note Used for PLL1PCLK selected ADC and SAI
2411 * @rmtoll PLL1DIVR PLL1P LL_RCC_PLL1_GetP
2412 * @retval Between 2 and 128
2413 */
LL_RCC_PLL1_GetP(void)2414 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
2415 {
2416 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1UL);
2417 }
2418
2419
2420 /**
2421 * @brief Set PLL1 division factor for PLL1Q
2422 * @note Used for PLL1QCLK selected for RNG and SAI
2423 * @rmtoll PLL1DIVR PLL1Q LL_RCC_PLL1_SetQ
2424 * @param PLL1Q parameter can be a value between 1 and 128
2425 */
LL_RCC_PLL1_SetQ(uint32_t PLL1Q)2426 __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t PLL1Q)
2427 {
2428 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q, (PLL1Q - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos);
2429 }
2430
2431 /**
2432 * @brief Get PLL1 division factor for PLL1Q
2433 * @note Used for PLL1QCLK selected for RNG and SAI
2434 * @rmtoll PLL1DIVR PLL1Q LL_RCC_PLL1_GetQ
2435 * @retval Between 1 and 128
2436 */
LL_RCC_PLL1_GetQ(void)2437 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
2438 {
2439 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1UL);
2440 }
2441
2442 /**
2443 * @brief Set PLL1 division factor for PLL1R
2444 * @note Used for PLL1RCLK selected for system clock
2445 * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_SetR
2446 * @param PLL1R parameter can be a value between 1 and 128
2447 */
LL_RCC_PLL1_SetR(uint32_t PLL1R)2448 __STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t PLL1R)
2449 {
2450 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos);
2451 }
2452
2453 /**
2454 * @brief Get PLL1 division factor for PLL1R
2455 * @note Used for PLL1RCLK selected for system clock
2456 * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_GetR
2457 * @retval Between 1 and 128
2458 */
LL_RCC_PLL1_GetR(void)2459 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
2460 {
2461 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL);
2462 }
2463
2464 /**
2465 * @brief Set Division factor for PLL1
2466 * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_SetDivider
2467 * @param PLL1M parameter can be a value between 1 and 8
2468 */
LL_RCC_PLL1_SetDivider(uint32_t PLL1M)2469 __STATIC_INLINE void LL_RCC_PLL1_SetDivider(uint32_t PLL1M)
2470 {
2471 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (PLL1M - 1UL) << RCC_PLL1CFGR_PLL1M_Pos);
2472 }
2473
2474 /**
2475 * @brief Get Division factor for PLL1
2476 * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_GetDivider
2477 * @retval Between 1 and 8
2478 */
LL_RCC_PLL1_GetDivider(void)2479 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetDivider(void)
2480 {
2481 return (uint32_t)((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1UL);
2482 }
2483
2484 /**
2485 * @brief Enable PLL1P output
2486 * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_EnableDomain_PLL1P
2487 * @retval None
2488 */
LL_RCC_PLL1_EnableDomain_PLL1P(void)2489 __STATIC_INLINE void LL_RCC_PLL1_EnableDomain_PLL1P(void)
2490 {
2491 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN);
2492 }
2493
2494 /**
2495 * @brief Disable PLL1P output
2496 * @note In order to save power, when the PLL1PCLK of the PLL1 is
2497 * not used, should be 0
2498 * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_DisableDomain_PLL1P
2499 * @retval None
2500 */
LL_RCC_PLL1_DisableDomain_PLL1P(void)2501 __STATIC_INLINE void LL_RCC_PLL1_DisableDomain_PLL1P(void)
2502 {
2503 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN);
2504 }
2505
2506 /**
2507 * @brief Check if PLL1P output is enabled
2508 * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_IsEnabledDomain_PLL1P
2509 * @retval State of bit (1 or 0).
2510 */
LL_RCC_PLL1_IsEnabledDomain_PLL1P(void)2511 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_PLL1P(void)
2512 {
2513 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN) == RCC_PLL1CFGR_PLL1PEN) ? 1UL : 0UL);
2514 }
2515
2516 /**
2517 * @brief Enable PLL1Q output
2518 * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_EnableDomain_PLL1Q
2519 * @retval None
2520 */
LL_RCC_PLL1_EnableDomain_PLL1Q(void)2521 __STATIC_INLINE void LL_RCC_PLL1_EnableDomain_PLL1Q(void)
2522 {
2523 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN);
2524 }
2525
2526 /**
2527 * @brief Disable PLL1Q output
2528 * @note In order to save power, when the PLL1QCLK of the PLL1 is
2529 * not used, should be 0
2530 * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_DisableDomain_PLL1Q
2531 * @retval None
2532 */
LL_RCC_PLL1_DisableDomain_PLL1Q(void)2533 __STATIC_INLINE void LL_RCC_PLL1_DisableDomain_PLL1Q(void)
2534 {
2535 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN);
2536 }
2537
2538 /**
2539 * @brief Check if PLL1Q output is enabled
2540 * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_IsEnabledDomain_PLL1Q
2541 * @retval State of bit (1 or 0).
2542 */
LL_RCC_PLL1_IsEnabledDomain_PLL1Q(void)2543 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_PLL1Q(void)
2544 {
2545 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN) == RCC_PLL1CFGR_PLL1QEN) ? 1UL : 0UL);
2546 }
2547
2548 /**
2549 * @brief Enable PLL1R output mapped on SYSCLK domain
2550 * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_EnableDomain_PLL1R
2551 * @retval None
2552 */
LL_RCC_PLL1_EnableDomain_PLL1R(void)2553 __STATIC_INLINE void LL_RCC_PLL1_EnableDomain_PLL1R(void)
2554 {
2555 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN);
2556 }
2557
2558 /**
2559 * @brief Disable PLL1 output mapped on SYSCLK domain
2560 * @note Cannot be disabled if the PLL1 clock is used as the system
2561 * clock
2562 * @note In order to save power, when the PLL1RCLK of the PLL1 is
2563 * not used, PLL1 should be 0
2564 * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_DisableDomain_PLL1R
2565 * @retval None
2566 */
LL_RCC_PLL1_DisableDomain_PLL1R(void)2567 __STATIC_INLINE void LL_RCC_PLL1_DisableDomain_PLL1R(void)
2568 {
2569 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN);
2570 }
2571
2572 /**
2573 * @brief Check if PLL1R output mapped on SYSCLK domain clock is enabled
2574 * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_IsEnabledDomain_PLL1R
2575 * @retval State of bit (1 or 0).
2576 */
LL_RCC_PLL1_IsEnabledDomain_PLL1R(void)2577 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_PLL1R(void)
2578 {
2579 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN) == RCC_PLL1CFGR_PLL1REN) ? 1UL : 0UL);
2580 }
2581
2582 /**
2583 * @brief Enable PLL1 FRACN
2584 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
2585 * @retval None
2586 */
LL_RCC_PLL1FRACN_Enable(void)2587 __STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
2588 {
2589 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN);
2590 }
2591
2592 /**
2593 * @brief Check if PLL1 FRACN is enabled
2594 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled
2595 * @retval State of bit (1 or 0).
2596 */
LL_RCC_PLL1FRACN_IsEnabled(void)2597 __STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
2598 {
2599 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) == RCC_PLL1CFGR_PLL1FRACEN) ? 1UL : 0UL);
2600 }
2601
2602 /**
2603 * @brief Disable PLL1 FRACN
2604 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Disable
2605 * @retval None
2606 */
LL_RCC_PLL1FRACN_Disable(void)2607 __STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
2608 {
2609 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN);
2610 }
2611
2612 /**
2613 * @brief Set PLL1 FRACN Coefficient
2614 * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_SetFRACN
2615 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
2616 */
LL_RCC_PLL1_SetFRACN(uint32_t FRACN)2617 __STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
2618 {
2619 MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN, FRACN << RCC_PLL1FRACR_PLL1FRACN_Pos);
2620 }
2621
2622 /**
2623 * @brief Get PLL1 FRACN Coefficient
2624 * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_GetFRACN
2625 * @retval A value between 0 and 8191 (0x1FFF)
2626 */
LL_RCC_PLL1_GetFRACN(void)2627 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
2628 {
2629 return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos);
2630 }
2631
2632 /**
2633 * @brief Set PLL1 VCO Input Range
2634 * @note This API shall be called only when PLL1 is disabled.
2635 * @rmtoll PLL1CFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange
2636 * @param InputRange This parameter can be one of the following values:
2637 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
2638 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
2639 * @retval None
2640 */
LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)2641 __STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
2642 {
2643 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, InputRange << RCC_PLL1CFGR_PLL1RGE_Pos);
2644 }
2645
2646 /**
2647 * @}
2648 */
2649
2650 #if defined(RCC_PRIVCFGR_NSPRIV)
2651 /** @defgroup RCC_LL_EF_PRIV Privileged mode
2652 * @{
2653 */
2654
2655 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2656 /**
2657 * @brief Enable Secure Privileged mode
2658 * @rmtoll PRIVCFGR SPRIV LL_RCC_EnableSecPrivilegedMode
2659 * @retval None
2660 */
LL_RCC_EnableSecPrivilegedMode(void)2661 __STATIC_INLINE void LL_RCC_EnableSecPrivilegedMode(void)
2662 {
2663 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
2664 }
2665
2666 /**
2667 * @brief Disable Secure Privileged mode
2668 * @rmtoll PRIVCFGR SPRIV LL_RCC_DisableSecPrivilegedMode
2669 * @retval None
2670 */
LL_RCC_DisableSecPrivilegedMode(void)2671 __STATIC_INLINE void LL_RCC_DisableSecPrivilegedMode(void)
2672 {
2673 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
2674 }
2675
2676 /**
2677 * @brief Check if Secure Privileged mode has been enabled or not
2678 * @rmtoll PRIVCFGR SPRIV LL_RCC_IsEnabledSecPrivilegedMode
2679 * @retval State of bit (1 or 0).
2680 */
LL_RCC_IsEnabledSecPrivilegedMode(void)2681 __STATIC_INLINE uint32_t LL_RCC_IsEnabledSecPrivilegedMode(void)
2682 {
2683 return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV) == RCC_PRIVCFGR_SPRIV) ? 1UL : 0UL);
2684 }
2685 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
2686
2687 /**
2688 * @brief Enable Non Secure Privileged mode
2689 * @rmtoll PRIVCFGR NSPRIV LL_RCC_EnableNSecPrivilegedMode
2690 * @retval None
2691 */
LL_RCC_EnableNSecPrivilegedMode(void)2692 __STATIC_INLINE void LL_RCC_EnableNSecPrivilegedMode(void)
2693 {
2694 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
2695 }
2696
2697 /**
2698 * @brief Disable Non Secure Privileged mode
2699 * @rmtoll PRIVCFGR NSPRIV LL_RCC_DisableNSecPrivilegedMode
2700 * @retval None
2701 */
LL_RCC_DisableNSecPrivilegedMode(void)2702 __STATIC_INLINE void LL_RCC_DisableNSecPrivilegedMode(void)
2703 {
2704 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
2705 }
2706
2707 /**
2708 * @brief Check if Non Secure Privileged mode has been enabled or not
2709 * @rmtoll PRIVCFGR NSPRIV LL_RCC_IsEnabledNSecPrivilegedMode
2710 * @retval State of bit (1 or 0).
2711 */
LL_RCC_IsEnabledNSecPrivilegedMode(void)2712 __STATIC_INLINE uint32_t LL_RCC_IsEnabledNSecPrivilegedMode(void)
2713 {
2714 return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV) == RCC_PRIVCFGR_NSPRIV) ? 1UL : 0UL);
2715 }
2716
2717 /**
2718 * @}
2719 */
2720 #endif /* RCC_PRIVCFGR_NSPRIV */
2721
2722 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
2723 * @{
2724 */
2725
2726 /**
2727 * @brief Clear LSI1 ready interrupt flag
2728 * @rmtoll CICR LSI1RDYC LL_RCC_ClearFlag_LSI1RDY
2729 * @retval None
2730 */
LL_RCC_ClearFlag_LSI1RDY(void)2731 __STATIC_INLINE void LL_RCC_ClearFlag_LSI1RDY(void)
2732 {
2733 SET_BIT(RCC->CICR, RCC_CICR_LSI1RDYC);
2734 }
2735
2736 #if defined(RCC_LSI2_SUPPORT)
2737 /**
2738 * @brief Clear LSI2 ready interrupt flag
2739 * @rmtoll CICR LSI2RDYC LL_RCC_ClearFlag_LSI2RDY
2740 * @retval None
2741 */
LL_RCC_ClearFlag_LSI2RDY(void)2742 __STATIC_INLINE void LL_RCC_ClearFlag_LSI2RDY(void)
2743 {
2744 SET_BIT(RCC->CICR, RCC_CICR_LSI2RDYC);
2745 }
2746 #endif /* RCC_BDCR1_LSI2ON */
2747
2748 /**
2749 * @brief Clear LSE ready interrupt flag
2750 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
2751 * @retval None
2752 */
LL_RCC_ClearFlag_LSERDY(void)2753 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
2754 {
2755 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
2756 }
2757
2758 /**
2759 * @brief Clear HSI ready interrupt flag
2760 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
2761 * @retval None
2762 */
LL_RCC_ClearFlag_HSIRDY(void)2763 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
2764 {
2765 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
2766 }
2767
2768 /**
2769 * @brief Clear HSE ready interrupt flag
2770 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
2771 * @retval None
2772 */
LL_RCC_ClearFlag_HSERDY(void)2773 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
2774 {
2775 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
2776 }
2777
2778 /**
2779 * @brief Clear PLL1 ready interrupt flag
2780 * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY
2781 * @retval None
2782 */
LL_RCC_ClearFlag_PLL1RDY(void)2783 __STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
2784 {
2785 SET_BIT(RCC->CICR, RCC_CICR_PLL1RDYC);
2786 }
2787
2788 /**
2789 * @brief Clear Clock security system interrupt flag
2790 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
2791 * @retval None
2792 */
LL_RCC_ClearFlag_HSECSS(void)2793 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
2794 {
2795 SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
2796 }
2797
2798
2799 /**
2800 * @brief Check if LSI1 ready interrupt occurred or not
2801 * @rmtoll CIFR LSI1RDYF LL_RCC_IsActiveFlag_LSI1RDY
2802 * @retval State of bit (1 or 0).
2803 */
LL_RCC_IsActiveFlag_LSI1RDY(void)2804 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI1RDY(void)
2805 {
2806 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSI1RDYF) == RCC_CIFR_LSI1RDYF) ? 1UL : 0UL);
2807 }
2808
2809 #if defined(RCC_LSI2_SUPPORT)
2810 /**
2811 * @brief Check if LSI2 ready interrupt occurred or not
2812 * @rmtoll CIFR LSI2RDYF LL_RCC_IsActiveFlag_LSI2RDY
2813 * @retval State of bit (1 or 0).
2814 */
LL_RCC_IsActiveFlag_LSI2RDY(void)2815 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI2RDY(void)
2816 {
2817 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSI2RDYF) == RCC_CIFR_LSI2RDYF) ? 1UL : 0UL);
2818 }
2819 #endif /* RCC_BDCR1_LSI2ON */
2820
2821 /**
2822 * @brief Check if LSE ready interrupt occurred or not
2823 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
2824 * @retval State of bit (1 or 0).
2825 */
LL_RCC_IsActiveFlag_LSERDY(void)2826 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
2827 {
2828 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
2829 }
2830
2831 /**
2832 * @brief Check if HSI ready interrupt occurred or not
2833 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
2834 * @retval State of bit (1 or 0).
2835 */
LL_RCC_IsActiveFlag_HSIRDY(void)2836 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
2837 {
2838 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
2839 }
2840
2841 /**
2842 * @brief Check if HSE ready interrupt occurred or not
2843 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
2844 * @retval State of bit (1 or 0).
2845 */
LL_RCC_IsActiveFlag_HSERDY(void)2846 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
2847 {
2848 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
2849 }
2850
2851 /**
2852 * @brief Check if PLL1 ready interrupt occurred or not
2853 * @rmtoll CIFR PLL1RDYF LL_RCC_IsActiveFlag_PLL1RDY
2854 * @retval State of bit (1 or 0).
2855 */
LL_RCC_IsActiveFlag_PLL1RDY(void)2856 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
2857 {
2858 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL);
2859 }
2860
2861 /**
2862 * @brief Check if Clock security system interrupt occurred or not
2863 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
2864 * @retval State of bit (1 or 0).
2865 */
LL_RCC_IsActiveFlag_HSECSS(void)2866 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
2867 {
2868 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == RCC_CIFR_HSECSSF) ? 1UL : 0UL);
2869 }
2870
2871 /**
2872 * @brief Check if RCC flag Independent Watchdog reset is set or not.
2873 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
2874 * @retval State of bit (1 or 0).
2875 */
LL_RCC_IsActiveFlag_IWDGRST(void)2876 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
2877 {
2878 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL);
2879 }
2880
2881 /**
2882 * @brief Check if RCC flag Low Power reset is set or not.
2883 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
2884 * @retval State of bit (1 or 0).
2885 */
LL_RCC_IsActiveFlag_LPWRRST(void)2886 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
2887 {
2888 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL);
2889 }
2890
2891 /**
2892 * @brief Check if RCC flag is set or not.
2893 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
2894 * @retval State of bit (1 or 0).
2895 */
LL_RCC_IsActiveFlag_OBLRST(void)2896 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
2897 {
2898 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL);
2899 }
2900
2901 /**
2902 * @brief Check if RCC flag Pin reset is set or not.
2903 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
2904 * @retval State of bit (1 or 0).
2905 */
LL_RCC_IsActiveFlag_PINRST(void)2906 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
2907 {
2908 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL);
2909 }
2910
2911 /**
2912 * @brief Check if RCC flag Software reset is set or not.
2913 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
2914 * @retval State of bit (1 or 0).
2915 */
LL_RCC_IsActiveFlag_SFTRST(void)2916 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
2917 {
2918 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL);
2919 }
2920
2921 /**
2922 * @brief Check if RCC flag Window Watchdog reset is set or not.
2923 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
2924 * @retval State of bit (1 or 0).
2925 */
LL_RCC_IsActiveFlag_WWDGRST(void)2926 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
2927 {
2928 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL);
2929 }
2930
2931 /**
2932 * @brief Check if RCC flag BOR reset is set or not.
2933 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
2934 * @retval State of bit (1 or 0).
2935 */
LL_RCC_IsActiveFlag_BORRST(void)2936 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
2937 {
2938 return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL);
2939 }
2940
2941 /**
2942 * @brief Set RMVF bit to clear the reset flags.
2943 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
2944 * @retval None
2945 */
LL_RCC_ClearResetFlags(void)2946 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
2947 {
2948 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
2949 }
2950
2951 /* Alias for portability */
2952 #define LL_RCC_PLL1_ConfigDomain_SYS LL_RCC_PLL1_ConfigDomain_PLL1R
2953
2954 /**
2955 * @}
2956 */
2957
2958 /** @defgroup RCC_LL_EF_IT_Management IT Management
2959 * @{
2960 */
2961
2962 /**
2963 * @brief Enable LSI1 ready interrupt
2964 * @rmtoll CIER LSI1RDYIE LL_RCC_EnableIT_LSI1RDY
2965 * @retval None
2966 */
LL_RCC_EnableIT_LSI1RDY(void)2967 __STATIC_INLINE void LL_RCC_EnableIT_LSI1RDY(void)
2968 {
2969 SET_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE);
2970 }
2971
2972 #if defined(RCC_LSI2_SUPPORT)
2973 /**
2974 * @brief Enable LSI2 ready interrupt
2975 * @rmtoll CIER LSI2RDYIE LL_RCC_EnableIT_LSI2RDY
2976 * @retval None
2977 */
LL_RCC_EnableIT_LSI2RDY(void)2978 __STATIC_INLINE void LL_RCC_EnableIT_LSI2RDY(void)
2979 {
2980 SET_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE);
2981 }
2982 #endif /* RCC_BDCR1_LSI2ON */
2983
2984 /**
2985 * @brief Enable LSE ready interrupt
2986 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
2987 * @retval None
2988 */
LL_RCC_EnableIT_LSERDY(void)2989 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
2990 {
2991 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
2992 }
2993
2994 /**
2995 * @brief Enable HSI ready interrupt
2996 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
2997 * @retval None
2998 */
LL_RCC_EnableIT_HSIRDY(void)2999 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
3000 {
3001 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
3002 }
3003
3004 /**
3005 * @brief Enable HSE ready interrupt
3006 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
3007 * @retval None
3008 */
LL_RCC_EnableIT_HSERDY(void)3009 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
3010 {
3011 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
3012 }
3013
3014 /**
3015 * @brief Enable PLL1 ready interrupt
3016 * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY
3017 * @retval None
3018 */
LL_RCC_EnableIT_PLL1RDY(void)3019 __STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
3020 {
3021 SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
3022 }
3023
3024 /**
3025 * @brief Disable LSI1 ready interrupt
3026 * @rmtoll CIER LSI1RDYIE LL_RCC_DisableIT_LSI1RDY
3027 * @retval None
3028 */
LL_RCC_DisableIT_LSI1RDY(void)3029 __STATIC_INLINE void LL_RCC_DisableIT_LSI1RDY(void)
3030 {
3031 CLEAR_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE);
3032 }
3033
3034 #if defined(RCC_LSI2_SUPPORT)
3035 /**
3036 * @brief Disable LSI2 ready interrupt
3037 * @rmtoll CIER LSI2RDYIE LL_RCC_DisableIT_LSI2RDY
3038 * @retval None
3039 */
LL_RCC_DisableIT_LSI2RDY(void)3040 __STATIC_INLINE void LL_RCC_DisableIT_LSI2RDY(void)
3041 {
3042 CLEAR_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE);
3043 }
3044 #endif /* RCC_BDCR1_LSI2ON */
3045
3046 /**
3047 * @brief Disable LSE ready interrupt
3048 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
3049 * @retval None
3050 */
LL_RCC_DisableIT_LSERDY(void)3051 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
3052 {
3053 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
3054 }
3055
3056 /**
3057 * @brief Disable HSI ready interrupt
3058 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
3059 * @retval None
3060 */
LL_RCC_DisableIT_HSIRDY(void)3061 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
3062 {
3063 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
3064 }
3065
3066 /**
3067 * @brief Disable HSE ready interrupt
3068 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
3069 * @retval None
3070 */
LL_RCC_DisableIT_HSERDY(void)3071 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
3072 {
3073 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
3074 }
3075
3076 /**
3077 * @brief Disable PLL1 ready interrupt
3078 * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY
3079 * @retval None
3080 */
LL_RCC_DisableIT_PLL1RDY(void)3081 __STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
3082 {
3083 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
3084 }
3085
3086 /**
3087 * @brief Checks if LSI1 ready interrupt source is enabled or disabled.
3088 * @rmtoll CIER LSI1RDYIE LL_RCC_IsEnabledIT_LSI1RDY
3089 * @retval State of bit (1 or 0).
3090 */
LL_RCC_IsEnabledIT_LSI1RDY(void)3091 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI1RDY(void)
3092 {
3093 return ((READ_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE) == RCC_CIER_LSI1RDYIE) ? 1UL : 0UL);
3094 }
3095
3096 #if defined(RCC_LSI2_SUPPORT)
3097 /**
3098 * @brief Checks if LSI2 ready interrupt source is enabled or disabled.
3099 * @rmtoll CIER LSI2RDYIE LL_RCC_IsEnabledIT_LSI2RDY
3100 * @retval State of bit (1 or 0).
3101 */
LL_RCC_IsEnabledIT_LSI2RDY(void)3102 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI2RDY(void)
3103 {
3104 return ((READ_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE) == RCC_CIER_LSI2RDYIE) ? 1UL : 0UL);
3105 }
3106 #endif /* RCC_BDCR1_LSI2ON */
3107
3108 /**
3109 * @brief Checks if LSE ready interrupt source is enabled or disabled.
3110 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
3111 * @retval State of bit (1 or 0).
3112 */
LL_RCC_IsEnabledIT_LSERDY(void)3113 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
3114 {
3115 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
3116 }
3117
3118
3119 /**
3120 * @brief Checks if HSI ready interrupt source is enabled or disabled.
3121 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
3122 * @retval State of bit (1 or 0).
3123 */
LL_RCC_IsEnabledIT_HSIRDY(void)3124 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
3125 {
3126 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
3127 }
3128
3129 /**
3130 * @brief Checks if HSE ready interrupt source is enabled or disabled.
3131 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
3132 * @retval State of bit (1 or 0).
3133 */
LL_RCC_IsEnabledIT_HSERDY(void)3134 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
3135 {
3136 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
3137 }
3138
3139 /**
3140 * @brief Checks if PLL1 ready interrupt source is enabled or disabled.
3141 * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnabledIT_PLL1RDY
3142 * @retval State of bit (1 or 0).
3143 */
LL_RCC_IsEnabledIT_PLL1RDY(void)3144 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL1RDY(void)
3145 {
3146 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL);
3147 }
3148
3149 /**
3150 * @}
3151 */
3152
3153 /** @defgroup RCC_LL_EF_Security_Services Security Services
3154 * @{
3155 */
3156
3157 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3158 /**
3159 * @brief Configure RCC resources security
3160 * @note Only available from secure state when system implements security (TZEN=1)
3161 * @rmtoll SECCFGR HSISEC LL_RCC_ConfigSecure\n
3162 * SECCFGR HSESEC LL_RCC_ConfigSecure\n
3163 * SECCFGR LSISEC LL_RCC_ConfigSecure\n
3164 * SECCFGR LSESEC LL_RCC_ConfigSecure\n
3165 * SECCFGR SYSCLKSEC LL_RCC_ConfigSecure\n
3166 * SECCFGR PRESCSEC LL_RCC_ConfigSecure\n
3167 * SECCFGR PLL1SEC LL_RCC_ConfigSecure\n
3168 * SECCFGR RMVFSEC LL_RCC_ConfigSecure
3169 * @param SecureConfig This parameter can be one or a combination of the following values:
3170 * @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC
3171 * @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC
3172 * @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC
3173 * @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC
3174 * @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC
3175 * @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC
3176 * @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC
3177 * @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC
3178 * @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC
3179 * @retval None
3180 */
LL_RCC_ConfigSecure(uint32_t SecureConfig)3181 __STATIC_INLINE void LL_RCC_ConfigSecure(uint32_t SecureConfig)
3182 {
3183 WRITE_REG(RCC->SECCFGR, SecureConfig);
3184 }
3185 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
3186
3187 /**
3188 * @brief Get RCC resources security status
3189 * @note Only available from secure state when system implements security (TZEN=1)
3190 * @rmtoll SECCFGR HSISEC LL_RCC_GetConfigSecure\n
3191 * SECCFGR HSESEC LL_RCC_GetConfigSecure\n
3192 * SECCFGR LSISEC LL_RCC_GetConfigSecure\n
3193 * SECCFGR LSESEC LL_RCC_GetConfigSecure\n
3194 * SECCFGR SYSCLKSEC LL_RCC_GetConfigSecure\n
3195 * SECCFGR PRESCSEC LL_RCC_GetConfigSecure\n
3196 * SECCFGR PLL1SEC LL_RCC_GetConfigSecure\n
3197 * SECCFGR RMVFSEC LL_RCC_GetConfigSecure
3198 * @retval Returned value can be one or a combination of the following values:
3199 * @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC
3200 * @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC
3201 * @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC
3202 * @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC
3203 * @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC
3204 * @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC
3205 * @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC
3206 * @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC
3207 * @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC
3208 * @retval None
3209 */
LL_RCC_GetConfigSecure(void)3210 __STATIC_INLINE uint32_t LL_RCC_GetConfigSecure(void)
3211 {
3212 return (uint32_t)(READ_BIT(RCC->SECCFGR, RCC_SECURE_MASK));
3213 }
3214
3215 /**
3216 * @}
3217 */
3218
3219 #if defined(USE_FULL_LL_DRIVER)
3220 /** @defgroup RCC_LL_EF_Init De-initialization function
3221 * @{
3222 */
3223 ErrorStatus LL_RCC_DeInit(void);
3224 /**
3225 * @}
3226 */
3227
3228 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
3229 * @{
3230 */
3231 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
3232 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
3233 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
3234 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
3235 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
3236 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
3237 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
3238 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
3239 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
3240 /**
3241 * @}
3242 */
3243
3244 #endif /* USE_FULL_LL_DRIVER */
3245
3246 /**
3247 * @}
3248 */
3249
3250 /**
3251 * @}
3252 */
3253
3254 #endif /* defined(RCC) */
3255
3256 /**
3257 * @}
3258 */
3259
3260 #ifdef __cplusplus
3261 }
3262 #endif
3263
3264 #endif /* STM32WBAxx_LL_RCC_H */
3265
3266
