1 /**
2 ******************************************************************************
3 * @file stm32wbaxx_hal_rcc_ex.c
4 * @author MCD Application Team
5 * @brief Extended RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities RCC extended peripheral:
8 * + Extended Peripheral Control functions
9 * + Extended Clock management functions
10 * + Extended Clock Recovery System Control functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2022 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 */
24
25 /* Includes ------------------------------------------------------------------*/
26 #include "stm32wbaxx_hal.h"
27
28 /** @addtogroup STM32WBAxx_HAL_Driver
29 * @{
30 */
31
32 /** @defgroup RCCEx RCCEx
33 * @brief RCC Extended HAL module driver
34 * @{
35 */
36
37 #ifdef HAL_RCC_MODULE_ENABLED
38
39 /* Private typedef -----------------------------------------------------------*/
40 /* Private defines -----------------------------------------------------------*/
41 /* Private macros ------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private function prototypes -----------------------------------------------*/
44 /* Exported functions --------------------------------------------------------*/
45
46 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
47 * @{
48 */
49
50 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
51 * @brief Extended Peripheral Control functions
52 *
53 @verbatim
54 ===============================================================================
55 ##### Extended Peripheral Control functions #####
56 ===============================================================================
57 [..]
58 This subsection provides a set of functions allowing to control the RCC Clocks
59 frequencies.
60 [..]
61 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
62 select the RTC clock source; in this case the Backup domain will be reset in
63 order to modify the RTC Clock source, as consequence RTC registers (including
64 the backup registers) are set to their reset values.
65
66 @endverbatim
67 * @{
68 */
69
70 /**
71 * @brief Initialize the RCC extended peripherals clocks according to the specified
72 * parameters in the RCC_PeriphCLKInitTypeDef.
73 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
74 * contains a field PeriphClockSelection which can be a combination of the following values:
75 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
76 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock (*)
77 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock (*)
78 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock (*)
79 * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock (*)
80 * @arg @ref RCC_PERIPHCLK_SYSTICK SYSTICK peripheral clock
81 * @arg @ref RCC_PERIPHCLK_TIMIC TIMIC peripheral clock
82 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*)
83 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
84 * @arg @ref RCC_PERIPHCLK_AUDIOSYNC AUDIOSYNC peripheral clock (*)
85 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
86 * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
87 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
88 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
89 * @arg @ref RCC_PERIPHCLK_ADC ADC4 peripheral clock
90 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
91 * @note (*) Peripherals are not available on all devices
92 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
93 * the RTC clock source: in this case the access to Backup domain is enabled.
94 * @retval HAL status
95 */
HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef * PeriphClkInit)96 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit)
97 {
98 uint32_t tmpreg1;
99 uint32_t tmpreg2;
100 uint32_t tickstart;
101
102 /* Check the parameters */
103 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
104
105 /*-------------------------- USART1 clock source configuration -------------------*/
106 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
107 {
108 /* Check the parameters */
109 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
110
111 /* Configure the USART1 clock source */
112 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
113 }
114
115 #if defined (USART2)
116 /*-------------------------- USART2 clock source configuration -------------------*/
117 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
118 {
119 /* Check the parameters */
120 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
121
122 /* Configure the USART2 clock source */
123 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
124 }
125 #endif
126
127
128 #if defined (I2C1)
129 /*-------------------------- I2C1 clock source configuration ---------------------*/
130 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
131 {
132 /* Check the parameters */
133 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
134
135 /* Configure the I2C1 clock source */
136 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
137 }
138 #endif
139
140
141
142
143 #if defined (LPTIM2)
144 /*-------------------------- LPTIM2 clock source configuration -------------------*/
145 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
146 {
147 /* Check the parameters */
148 assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection));
149
150 /* Configure the LPTIM2 clock source */
151 __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
152 }
153 #endif
154
155 #if defined (SPI1)
156 /*-------------------------- SPI1 clock source configuration ----------------*/
157 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1)
158 {
159 /* Check the parameters */
160 assert_param(IS_RCC_SPI1CLKSOURCE(PeriphClkInit->Spi1ClockSelection));
161
162 /* Configure the SPI1 clock source */
163 __HAL_RCC_SPI1_CONFIG(PeriphClkInit->Spi1ClockSelection);
164 }
165 #endif
166
167 /*-------------------------- SYSTICK clock source configuration ----------------*/
168 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SYSTICK) == RCC_PERIPHCLK_SYSTICK)
169 {
170 /* Check the parameters */
171 assert_param(IS_RCC_SYSTICKCLKSOURCE(PeriphClkInit->SystickClockSelection));
172
173 /* Configure the SYSTICK clock source */
174 __HAL_RCC_SYSTICK_CONFIG(PeriphClkInit->SystickClockSelection);
175 }
176
177 /*-------------------------- TIMIC clock source configuration ----------------*/
178 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIMIC) == RCC_PERIPHCLK_TIMIC)
179 {
180 /* Check the parameters */
181 assert_param(IS_RCC_TIMICCLKSOURCE(PeriphClkInit->TimIcClockSelection));
182
183 /* Configure the TIMIC clock source */
184 __HAL_RCC_TIMIC_CONFIG(PeriphClkInit->TimIcClockSelection);
185 }
186
187 #if defined (SAI1)
188 /*-------------------------- SAI1 clock source configuration ---------------------*/
189 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
190 {
191 /* Check the parameters */
192 assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
193
194 /* Set the source of SAI1 clock*/
195 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
196
197 if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL1P)
198 {
199 /* Enable PLL1 PCLK output */
200 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_PCLK);
201 }
202 else if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL1Q)
203 {
204 /* Enable PLL1 QCLK output */
205 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_QCLK);
206 }
207 else
208 {
209 /* Do nothing ; for misra 15.7 error only */
210 }
211 }
212 #endif
213
214 /*------------------------------ RNG Configuration -------------------------*/
215 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
216 {
217 /* Check the parameters */
218 assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
219
220 /* Set the source of RNG clock*/
221 __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
222
223 if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL1Q)
224 {
225 /* Enable PLL1 QCLK output */
226 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_QCLK);
227 }
228 }
229
230
231 #if defined (RCC_CCIPR2_ASSEL)
232 /*-------------------------- AS clock source configuration -------------------*/
233 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_AUDIOSYNC) == RCC_PERIPHCLK_AUDIOSYNC)
234 {
235 /* Check the parameters */
236 assert_param(IS_RCC_ASCLKSOURCE(PeriphClkInit->AudioSyncClockSelection));
237
238 /* Configure the AS clock source */
239 __HAL_RCC_AUDIOSYNC_CONFIG(PeriphClkInit->AudioSyncClockSelection);
240 }
241 #endif
242
243 /*-------------------------- LPUART1 clock source configuration ------------------*/
244 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
245 {
246 /* Check the parameters */
247 assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
248
249 /* Configure the LPUART1 clock source */
250 __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
251 }
252
253 /*-------------------------- SPI3 clock source configuration ----------------*/
254 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3)
255 {
256 /* Check the parameters */
257 assert_param(IS_RCC_SPI3CLKSOURCE(PeriphClkInit->Spi3ClockSelection));
258
259 /* Configure the SPI3 clock source */
260 __HAL_RCC_SPI3_CONFIG(PeriphClkInit->Spi3ClockSelection);
261 }
262
263
264 /*-------------------------- I2C3 clock source configuration ---------------------*/
265 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
266 {
267 /* Check the parameters */
268 assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
269
270 /* Configure the I2C3 clock source */
271 __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
272 }
273
274 /*-------------------------- LPTIM1 clock source configuration -------------------*/
275 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
276 {
277 /* Check the parameters */
278 assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
279
280 /* Configure the I2C3 clock source */
281 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
282 }
283
284 /*-------------------------- ADC clock source configuration ----------------------*/
285 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
286 {
287 /* Check the parameters */
288 assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
289
290 /* Configure the ADC4 interface clock source */
291 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
292
293 if (PeriphClkInit->AdcClockSelection == RCC_PERIPHCLK_ADC)
294 {
295 /* Enable PLL1 PCLK output */
296 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_PCLK);
297 }
298 }
299
300 /*-------------------------- RTC clock source configuration ----------------------*/
301 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
302 {
303 FlagStatus pwrclkchanged = RESET;
304
305 /* Check for RTC Parameters used to output RTCCLK */
306 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
307
308 /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
309 tmpreg2 = __HAL_RCC_GET_RTC_SOURCE();
310
311 /* Check if RTC clock source needs to be changed */
312 if (tmpreg2 != PeriphClkInit->RTCClockSelection)
313 {
314 /* Enable Power Clock */
315 if (__HAL_RCC_PWR_IS_CLK_ENABLED() != 0x01u)
316 {
317 __HAL_RCC_PWR_CLK_ENABLE();
318 pwrclkchanged = SET;
319 }
320
321 /* Enable write access to Backup domain */
322 SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
323
324 /* Wait for Backup domain Write protection disable */
325 tickstart = HAL_GetTick();
326
327 while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
328 {
329 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
330 {
331 return HAL_TIMEOUT;
332 }
333 }
334
335 /* Save BDCR1 content */
336 tmpreg1 = (RCC->BDCR1 & ~RCC_BDCR1_RTCSEL);
337
338 /* Check if a backup domain reset is required */
339 if (tmpreg2 != RCC_RTCCLKSOURCE_DISABLE)
340 {
341 /* Save BDCR2 content */
342 tmpreg2 = RCC->BDCR2;
343
344 /* RTC Clock selection can be changed only if the Backup Domain is reset */
345 __HAL_RCC_BACKUPRESET_FORCE();
346 __HAL_RCC_BACKUPRESET_RELEASE();
347
348 /* Restore previously saved BDCR2 */
349 RCC->BDCR2 = tmpreg2;
350 }
351
352 /* Apply new RTC clock source selection */
353 RCC->BDCR1 = (tmpreg1 | PeriphClkInit->RTCClockSelection);
354
355 /* mask all ON bits */
356 tmpreg2 = (RCC_BDCR1_LSEON | RCC_BDCR1_LSI1ON);
357 #if defined(RCC_LSI2_SUPPORT)
358 tmpreg2 |= RCC_BDCR1_LSI2ON;
359 #endif
360
361 /* Check which oscillators were enable */
362 tmpreg2 &= tmpreg1;
363
364 if (tmpreg2 != 0x00u)
365 {
366 /* Get Start Tick*/
367 tickstart = HAL_GetTick();
368
369 /* Wait till all oscillators are enabled : RDY bit position is ON shifted by 1 */
370 while (READ_BIT(RCC->BDCR1, (tmpreg2 << 1)) == 0x00u)
371 {
372 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
373 {
374 return HAL_TIMEOUT;
375 }
376 }
377 }
378 /* Restore clock configuration if changed */
379 if (pwrclkchanged == SET)
380 {
381 __HAL_RCC_PWR_CLK_DISABLE();
382 }
383 }
384 }
385
386 /*-------------------------- RADIO Sleep Timer clock source configuration --*/
387 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RADIOST) == RCC_PERIPHCLK_RADIOST)
388 {
389 /* Check the parameters */
390 assert_param(IS_RCC_RADIOSLEEPTIMERSOURCE(PeriphClkInit->RadioSlpTimClockSelection));
391
392 /* Configure the RADIO Sleep Timer clock source */
393 __HAL_RCC_RADIOSLPTIM_CONFIG(PeriphClkInit->RadioSlpTimClockSelection);
394 }
395
396 return HAL_OK;
397 }
398
399
400 /**
401 * @brief Get the peripheral kernel clock configuration.
402 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
403 * returns the configuration information for all existing peripheral kernel clocks. (*)
404 * @note (*) Peripherals are not available on all devices
405 * @retval None
406 */
HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef * PeriphClkInit)407 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
408 {
409 uint32_t tmpreg;
410
411 /* Check the parameters */
412 assert_param(PeriphClkInit != NULL);
413
414 /* Set all possible values for the extended clock type parameter------------*/
415 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLOCK_ALL;
416
417 /* Get CCIPR1 register value */
418 tmpreg = RCC->CCIPR1;
419
420 /* Get the USART1 clock source ---------------------------------------------*/
421 PeriphClkInit->Usart1ClockSelection = (tmpreg & RCC_CCIPR1_USART1SEL);
422
423 #if defined (USART2)
424 /* Get the USART2 clock source ---------------------------------------------*/
425 PeriphClkInit->Usart2ClockSelection = (tmpreg & RCC_CCIPR1_USART2SEL);
426 #endif
427
428
429
430
431
432 #if defined (I2C1)
433 /* Get the I2C1 clock source -----------------------------------------------*/
434 PeriphClkInit->I2c1ClockSelection = (tmpreg & RCC_CCIPR1_I2C1SEL);
435 #endif
436
437 #if defined (LPTIM2)
438 /* Get the LPTIM2 clock source ---------------------------------------------*/
439 PeriphClkInit->Lptim2ClockSelection = (tmpreg & RCC_CCIPR1_LPTIM2SEL);
440 #endif
441
442 #if defined (SPI1)
443 /* Get the SPI1 clock source -----------------------------------------------*/
444 PeriphClkInit->Spi1ClockSelection = (tmpreg & RCC_CCIPR1_SPI1SEL);
445 #endif
446
447 /* Get the SYSTICK clock source --------------------------------------------*/
448 PeriphClkInit->SystickClockSelection = (tmpreg & RCC_CCIPR1_SYSTICKSEL);
449
450 /* Get the TIMIC clock source ----------------------------------------------*/
451 PeriphClkInit->TimIcClockSelection = (tmpreg & RCC_CCIPR1_TIMICSEL);
452
453 /* Get CCIPR2 register value */
454 tmpreg = RCC->CCIPR2;
455
456 #if defined (SAI1)
457 /* Get the SAI1 clock source -----------------------------------------------*/
458 PeriphClkInit->Sai1ClockSelection = (tmpreg & RCC_CCIPR2_SAI1SEL);
459 #endif
460
461 /* Get the RNG clock source ------------------------------------------------*/
462 PeriphClkInit->RngClockSelection = (tmpreg & RCC_CCIPR2_RNGSEL);
463
464
465 #if defined (RCC_CCIPR2_ASSEL)
466 /* Get the Audio sync clock source -----------------------------------------*/
467 PeriphClkInit->AudioSyncClockSelection = (tmpreg & RCC_CCIPR2_ASSEL);
468 #endif
469
470 /* Get CCIPR3 register value */
471 tmpreg = RCC->CCIPR3;
472
473 /* Get the LPUART1 clock source --------------------------------------------*/
474 PeriphClkInit->Lpuart1ClockSelection = (tmpreg & RCC_CCIPR3_LPUART1SEL);
475
476 /* Get the SPI3 clock source -----------------------------------------------*/
477 PeriphClkInit->Spi3ClockSelection = (tmpreg & RCC_CCIPR3_SPI3SEL);
478
479 /* Get the I2C3 clock source -----------------------------------------------*/
480 PeriphClkInit->I2c3ClockSelection = (tmpreg & RCC_CCIPR3_I2C3SEL);
481
482 /* Get the LPTIM1 clock source ---------------------------------------------*/
483 PeriphClkInit->Lptim1ClockSelection = (tmpreg & RCC_CCIPR3_LPTIM1SEL);
484
485 /* Get the ADC clock source ------------------------------------------------*/
486 PeriphClkInit->AdcClockSelection = (tmpreg & RCC_CCIPR3_ADCSEL);
487
488 /* Get BDCR1 register value */
489 tmpreg = RCC->BDCR1;
490
491 /* Get the RTC clock source ------------------------------------------------*/
492 PeriphClkInit->RTCClockSelection = (tmpreg & RCC_BDCR1_RTCSEL);
493
494 /* Get the Radio Sleep Timer clock source ----------------------------------*/
495 PeriphClkInit->RadioSlpTimClockSelection = (tmpreg & RCC_BDCR1_RADIOSTSEL);
496 }
497
498
499 /**
500 * @brief Return the peripheral clock frequency for peripherals
501 * @note Return 0 if peripheral clock identifier not managed by this API
502 * @param PeriphClk Peripheral clock identifier
503 * This parameter can be one of the following values:
504 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
505 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock (*)
506 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock (*)
507 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock (*)
508 * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock (*)
509 * @arg @ref RCC_PERIPHCLK_SYSTICK SYSTICK peripheral clock
510 * @arg @ref RCC_PERIPHCLK_TIMIC TIMIC peripheral clock
511 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*)
512 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
513 * @arg @ref RCC_PERIPHCLK_AUDIOSYNC AUDIOSYNC peripheral clock (*)
514 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
515 * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
516 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
517 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
518 * @arg @ref RCC_PERIPHCLK_ADC ADC4 peripheral clock
519 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
520 * @note (*) Peripherals are not available on all devices
521 * @retval Frequency in Hz
522 */
HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)523 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
524 {
525 uint32_t frequency = 0;
526 uint32_t srcclk;
527
528 /* Check the parameters */
529 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
530
531 switch (PeriphClk)
532 {
533 case RCC_PERIPHCLK_USART1:
534 /* Get the current USART1 source */
535 srcclk = __HAL_RCC_GET_USART1_SOURCE();
536
537 if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
538 {
539 frequency = HAL_RCC_GetPCLK2Freq();
540 }
541 else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
542 {
543 frequency = HAL_RCC_GetSysClockFreq();
544 }
545 else if (srcclk == RCC_USART1CLKSOURCE_HSI)
546 {
547 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
548 {
549 frequency = HSI_VALUE;
550 }
551 }
552 else
553 {
554 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
555 {
556 frequency = LSE_VALUE;
557 }
558 }
559 break;
560
561 #if defined (USART2)
562 case RCC_PERIPHCLK_USART2:
563 /* Get the current USART2 source */
564 srcclk = __HAL_RCC_GET_USART2_SOURCE();
565
566 if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
567 {
568 frequency = HAL_RCC_GetPCLK1Freq();
569 }
570 else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
571 {
572 frequency = HAL_RCC_GetSysClockFreq();
573 }
574 else if (srcclk == RCC_USART2CLKSOURCE_HSI)
575 {
576 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
577 {
578 frequency = HSI_VALUE;
579 }
580 }
581 else
582 {
583 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
584 {
585 frequency = LSE_VALUE;
586 }
587 }
588 break;
589 #endif
590
591
592 #if defined(I2C1)
593 case RCC_PERIPHCLK_I2C1:
594 /* Get the current I2C1 source */
595 srcclk = __HAL_RCC_GET_I2C1_SOURCE();
596
597 if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
598 {
599 frequency = HAL_RCC_GetPCLK1Freq();
600 }
601 else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
602 {
603 frequency = HAL_RCC_GetSysClockFreq();
604 }
605 else if (srcclk == RCC_I2C1CLKSOURCE_HSI)
606 {
607 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
608 {
609 frequency = HSI_VALUE;
610 }
611 }
612 else
613 {
614 /* Do nothing ; for misra 15.7 error only */
615 }
616 break;
617 #endif
618
619
620
621 #if defined(LPTIM2)
622 case RCC_PERIPHCLK_LPTIM2:
623 /* Get the current LPTIM2 source */
624 srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
625
626 if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1)
627 {
628 frequency = HAL_RCC_GetPCLK1Freq();
629 }
630 /* Check if LSI1 or LIS2 is ready and if LPTIM2 clock selection is LSI */
631 else if (srcclk == RCC_LPTIM2CLKSOURCE_LSI)
632 {
633 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY))
634 {
635 /* LSI Frequency */
636 frequency = LSI_VALUE;
637
638 /* Check is LSI1 is divided */
639 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV))
640 {
641 frequency /= 128U;
642 }
643 }
644 #if defined(RCC_LSI2_SUPPORT)
645 else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY))
646 {
647 frequency = LSI2_VALUE;
648 }
649 else
650 {
651 /* Do nothing ; for misra 15.7 error only */
652 }
653 #endif
654 }
655 else if (srcclk == RCC_LPTIM2CLKSOURCE_HSI)
656 {
657 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
658 {
659 frequency = HSI_VALUE;
660 }
661 }
662 else
663 {
664 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
665 {
666 frequency = LSE_VALUE;
667 }
668 }
669 break;
670 #endif
671
672 #if defined(SPI1)
673 case RCC_PERIPHCLK_SPI1:
674 /* Get the current SPI1 kernel source */
675 srcclk = __HAL_RCC_GET_SPI1_SOURCE();
676
677 if (srcclk == RCC_SPI1CLKSOURCE_PCLK2)
678 {
679 frequency = HAL_RCC_GetPCLK2Freq();
680 }
681 else if (srcclk == RCC_SPI1CLKSOURCE_SYSCLK)
682 {
683 frequency = HAL_RCC_GetSysClockFreq();
684 }
685 else if (srcclk == RCC_SPI1CLKSOURCE_HSI)
686 {
687 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
688 {
689 frequency = HSI_VALUE;
690 }
691 }
692 else
693 {
694 /* Do nothing ; for misra 15.7 error only */
695 }
696 break;
697 #endif
698
699 case RCC_PERIPHCLK_SYSTICK:
700 /* Get the current SYSTICK kernel source */
701 srcclk = __HAL_RCC_GET_SYSTICK_SOURCE();
702
703 if (srcclk == RCC_SYSTICKCLKSOURCE_HCLK_DIV8)
704 {
705 frequency = (HAL_RCC_GetHCLKFreq() / 8U);
706 }
707 else if (srcclk == RCC_SYSTICKCLKSOURCE_LSE)
708 {
709 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
710 {
711 frequency = LSE_VALUE;
712 }
713 }
714 else if (srcclk == RCC_SYSTICKCLKSOURCE_LSI)
715 {
716 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY))
717 {
718 /* LSI Frequency */
719 frequency = LSI_VALUE;
720
721 /* Check is LSI1 is divided */
722 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV))
723 {
724 frequency /= 128U;
725 }
726 }
727 #if defined(RCC_LSI2_SUPPORT)
728 else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY))
729 {
730 frequency = LSI2_VALUE;
731 }
732 else
733 {
734 /* Do nothing ; for misra 15.7 error only */
735 }
736 #endif
737 }
738 else
739 {
740 /* Do nothing ; for misra 15.7 error only */
741 }
742 break;
743
744 case RCC_PERIPHCLK_TIMIC:
745 /* Get the current TIMIC source */
746 srcclk = __HAL_RCC_GET_TIMIC_SOURCE();
747
748 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
749 {
750 frequency = HSI_VALUE;
751 if (srcclk == RCC_TIMICCLKSOURCE_HSI_DIV256)
752 {
753 frequency /= 256U;
754 }
755 }
756 break;
757
758 #if defined (SAI1)
759 case RCC_PERIPHCLK_SAI1:
760 /* Get the current SAI1 source */
761 srcclk = __HAL_RCC_GET_SAI1_SOURCE();
762
763 if (srcclk == RCC_SAI1CLKSOURCE_PLL1P)
764 {
765 frequency = HAL_RCC_GetPLL1PFreq();
766 }
767 else if (srcclk == RCC_SAI1CLKSOURCE_PLL1Q)
768 {
769 frequency = HAL_RCC_GetPLL1QFreq();
770 }
771 else if (srcclk == RCC_SAI1CLKSOURCE_SYSCLK)
772 {
773 frequency = HAL_RCC_GetSysClockFreq();
774 }
775 else if (srcclk == RCC_SAI1CLKSOURCE_PIN)
776 {
777 frequency = EXTERNAL_SAI1_CLOCK_VALUE;
778 }
779 else if (srcclk == RCC_SAI1CLKSOURCE_HSI)
780 {
781 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
782 {
783 frequency = HSI_VALUE;
784 }
785 }
786 else
787 {
788 /* Do nothing ; for misra 15.7 error only */
789 }
790 break;
791 #endif
792
793 case RCC_PERIPHCLK_RNG:
794 /* Get the current RNG source */
795 srcclk = __HAL_RCC_GET_RNG_SOURCE();
796
797 if (srcclk == RCC_RNGCLKSOURCE_LSE)
798 {
799 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
800 {
801 frequency = LSE_VALUE;
802 }
803 }
804 else if (srcclk == RCC_RNGCLKSOURCE_LSI)
805 {
806 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY))
807 {
808 /* LSI Frequency */
809 frequency = LSI_VALUE;
810
811 /* Check is LSI1 is divided */
812 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV))
813 {
814 frequency /= 128U;
815 }
816 }
817 #if defined(RCC_LSI2_SUPPORT)
818 else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY))
819 {
820 frequency = LSI2_VALUE;
821 }
822 else
823 {
824 /* Do nothing ; for misra 15.7 error only */
825 }
826 #endif
827 }
828 else if (srcclk == RCC_RNGCLKSOURCE_HSI)
829 {
830 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
831 {
832 frequency = HSI_VALUE;
833 }
834 }
835 else
836 {
837 frequency = HAL_RCC_GetPLL1QFreq();
838 }
839 break;
840
841
842 #if defined (RCC_CCIPR2_ASSEL)
843 case RCC_PERIPHCLK_AUDIOSYNC:
844 /* Get the current Audio Sync source */
845 srcclk = __HAL_RCC_GET_AUDIOSYNC_SOURCE();
846
847 if (srcclk == RCC_ASCLKSOURCE_PLL1P)
848 {
849 frequency = HAL_RCC_GetPLL1PFreq();
850 }
851 else
852 {
853 frequency = HAL_RCC_GetPLL1QFreq();
854 }
855 break;
856 #endif
857
858 case RCC_PERIPHCLK_LPUART1:
859 /* Get the current LPUART1 source */
860 srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
861
862 if (srcclk == RCC_LPUART1CLKSOURCE_PCLK7)
863 {
864 frequency = HAL_RCC_GetPCLK7Freq();
865 }
866 else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
867 {
868 frequency = HAL_RCC_GetSysClockFreq();
869 }
870 else if (srcclk == RCC_LPUART1CLKSOURCE_HSI)
871 {
872 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
873 {
874 frequency = HSI_VALUE;
875 }
876 }
877 else
878 {
879 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
880 {
881 frequency = LSE_VALUE;
882 }
883 }
884 break;
885
886 case RCC_PERIPHCLK_SPI3:
887 /* Get the current SPI3 kernel source */
888 srcclk = __HAL_RCC_GET_SPI3_SOURCE();
889
890 if (srcclk == RCC_SPI3CLKSOURCE_PCLK7)
891 {
892 frequency = HAL_RCC_GetPCLK7Freq();
893 }
894 else if (srcclk == RCC_SPI3CLKSOURCE_SYSCLK)
895 {
896 frequency = HAL_RCC_GetSysClockFreq();
897 }
898 else if (srcclk == RCC_SPI3CLKSOURCE_HSI)
899 {
900 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
901 {
902 frequency = HSI_VALUE;
903 }
904 }
905 else
906 {
907 /* Do nothing ; for misra 15.7 error only */
908 }
909 break;
910
911 case RCC_PERIPHCLK_I2C3:
912 /* Get the current I2C3 source */
913 srcclk = __HAL_RCC_GET_I2C3_SOURCE();
914
915 if (srcclk == RCC_I2C3CLKSOURCE_PCLK7)
916 {
917 frequency = HAL_RCC_GetPCLK7Freq();
918 }
919 else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
920 {
921 frequency = HAL_RCC_GetSysClockFreq();
922 }
923 else if (srcclk == RCC_I2C3CLKSOURCE_HSI)
924 {
925 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
926 {
927 frequency = HSI_VALUE;
928 }
929 }
930 else
931 {
932 /* Do nothing ; for misra 15.7 error only */
933 }
934 break;
935
936 case RCC_PERIPHCLK_LPTIM1:
937 /* Get the current LPTIM1 source */
938 srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
939
940 if (srcclk == RCC_LPTIM1CLKSOURCE_PCLK7)
941 {
942 frequency = HAL_RCC_GetPCLK7Freq();
943 }
944 else if (srcclk == RCC_LPTIM1CLKSOURCE_LSI)
945 {
946 /* Check if LSI1 or LIS2 is ready */
947 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY))
948 {
949 /* LSI Frequency */
950 frequency = LSI_VALUE;
951
952 /* Check is LSI1 is divided */
953 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV))
954 {
955 frequency /= 128U;
956 }
957 }
958 #if defined(RCC_LSI2_SUPPORT)
959 else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY))
960 {
961 frequency = LSI2_VALUE;
962 }
963 else
964 {
965 /* Do nothing ; for misra 15.7 error only */
966 }
967 #endif
968 }
969 else if (srcclk == RCC_LPTIM1CLKSOURCE_HSI)
970 {
971 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
972 {
973 frequency = HSI_VALUE;
974 }
975 }
976 else
977 {
978 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
979 {
980 frequency = LSE_VALUE;
981 }
982 }
983 break;
984
985 case RCC_PERIPHCLK_ADC:
986 /* Get the current ADC kernel source */
987 srcclk = __HAL_RCC_GET_ADC_SOURCE();
988
989 if (srcclk == RCC_ADCCLKSOURCE_HCLK)
990 {
991 frequency = HAL_RCC_GetHCLKFreq();
992 }
993 else if (srcclk == RCC_ADCCLKSOURCE_SYSCLK)
994 {
995 frequency = HAL_RCC_GetSysClockFreq();
996 }
997 else if (srcclk == RCC_ADCCLKSOURCE_PLL1P)
998 {
999 frequency = HAL_RCC_GetPLL1PFreq();
1000 }
1001 else if (srcclk == RCC_ADCCLKSOURCE_HSE)
1002 {
1003 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
1004 {
1005 frequency = HSE_VALUE;
1006 }
1007 }
1008 else if (srcclk == RCC_ADCCLKSOURCE_HSI)
1009 {
1010 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1011 {
1012 frequency = HSI_VALUE;
1013 }
1014 }
1015 else
1016 {
1017 /* Do nothing ; for misra 15.7 error only */
1018 }
1019 break;
1020
1021 case RCC_PERIPHCLK_RTC:
1022 /* Get the current RTC source */
1023 srcclk = __HAL_RCC_GET_RTC_SOURCE();
1024
1025 /* Check if LSE is ready and if RTC clock selection is LSE */
1026 if (srcclk == RCC_RTCCLKSOURCE_LSE)
1027 {
1028 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
1029 {
1030 frequency = LSE_VALUE;
1031 }
1032 }
1033 /* Check if LSI1 or LIS2 is ready and if RTC clock selection is LSI */
1034 else if (srcclk == RCC_RTCCLKSOURCE_LSI)
1035 {
1036 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY))
1037 {
1038 /* LSI Frequency */
1039 frequency = LSI_VALUE;
1040
1041 /* Check is LSI1 is divided */
1042 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV))
1043 {
1044 frequency /= 128U;
1045 }
1046 }
1047 #if defined(RCC_LSI2_SUPPORT)
1048 else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY))
1049 {
1050 frequency = LSI2_VALUE;
1051 }
1052 else
1053 {
1054 /* Do nothing ; for misra 15.7 error only */
1055 }
1056 #endif /* RCC_LSI2_SUPPORT */
1057 }
1058 /* Check if HSE is ready and if RTC clock selection is HSI_DIV32 */
1059 else
1060 {
1061 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
1062 {
1063 frequency = (HSE_VALUE / 32U);
1064 }
1065 }
1066 break;
1067
1068 case RCC_PERIPHCLK_RADIOST:
1069 /* Get the current RADIOST kernel source */
1070 srcclk = __HAL_RCC_GET_RADIOSLPTIM_SOURCE();
1071
1072 if (srcclk == RCC_RADIOSTCLKSOURCE_HSE_DIV1000)
1073 {
1074 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
1075 {
1076 frequency = (HSE_VALUE / 1000U);
1077 }
1078 }
1079 else if (srcclk == RCC_RADIOSTCLKSOURCE_LSE)
1080 {
1081 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY))
1082 {
1083 frequency = LSE_VALUE;
1084 }
1085 }
1086 else if (srcclk == RCC_RADIOSTCLKSOURCE_LSI)
1087 {
1088 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY))
1089 {
1090 /* LSI Frequency */
1091 frequency = LSI_VALUE;
1092
1093 /* Check is LSI1 is divided */
1094 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV))
1095 {
1096 frequency /= 128U;
1097 }
1098 }
1099 #if defined(RCC_LSI2_SUPPORT)
1100 else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY))
1101 {
1102 frequency = LSI2_VALUE;
1103 }
1104 else
1105 {
1106 /* Do nothing ; for misra 15.7 error only */
1107 }
1108 #endif
1109 }
1110 else
1111 {
1112 /* Do nothing ; for misra 15.7 error only */
1113 }
1114 break;
1115
1116 default:
1117 break;
1118 }
1119
1120 return (frequency);
1121 }
1122
1123 /**
1124 * @}
1125 */
1126
1127 /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
1128 * @brief Extended Clock management functions
1129 *
1130 @verbatim
1131 ===============================================================================
1132 ##### Extended clock management functions #####
1133 ===============================================================================
1134 [..]
1135 This subsection provides a set of functions allowing to control the
1136 activation or deactivation of LSE CSS, Low Speed Clock Output (LSCO), HSE and
1137 LSE trimming and LSI2 configuration (when applicable).
1138 @endverbatim
1139 * @{
1140 */
1141
1142 /**
1143 * @brief Enable the LSE Clock Security System.
1144 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
1145 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
1146 * clock with HAL_RCCEx_PeriphCLKConfig().
1147 * @retval None
1148 */
HAL_RCCEx_EnableLSECSS(void)1149 void HAL_RCCEx_EnableLSECSS(void)
1150 {
1151 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSON);
1152 }
1153
1154 /**
1155 * @brief Disable the LSE Clock Security System.
1156 * @note LSE Clock Security System can only be disabled after a LSE failure detection.
1157 * @retval None
1158 */
HAL_RCCEx_DisableLSECSS(void)1159 void HAL_RCCEx_DisableLSECSS(void)
1160 {
1161 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSON);
1162 }
1163
1164 /**
1165 * @brief Select the Low Speed clock source to output on LSCO pin (PA2).
1166 * @param LSCOSource specifies the Low Speed clock source to output.
1167 * This parameter can be one of the following values:
1168 * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
1169 * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
1170 * @retval None
1171 */
HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)1172 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
1173 {
1174 /* Check the parameters */
1175 assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
1176
1177 /* Update LSCO selection according to parameter and enable LSCO */
1178 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSCOSEL, LSCOSource | RCC_BDCR1_LSCOEN);
1179 }
1180
1181 /**
1182 * @brief Disable the Low Speed clock output.
1183 * @retval None
1184 */
HAL_RCCEx_DisableLSCO(void)1185 void HAL_RCCEx_DisableLSCO(void)
1186 {
1187 /* Clear LSCOEN in BDCR register */
1188 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSCOEN);
1189 }
1190
1191 /**
1192 * @brief Set HSE trimming value
1193 * @param Trimming specifies the HSE trimmign value.
1194 * This parameter should be below 0x3F.
1195 * @retval None
1196 */
HAL_RCCEx_HSESetTrimming(uint32_t Trimming)1197 void HAL_RCCEx_HSESetTrimming(uint32_t Trimming)
1198 {
1199 /* Check the parameters */
1200 assert_param(IS_RCC_HSETRIM(Trimming));
1201
1202 MODIFY_REG(RCC->ECSCR1, RCC_ECSCR1_HSETRIM, Trimming << RCC_ECSCR1_HSETRIM_Pos);
1203 }
1204
1205 /**
1206 * @brief Get HSE trimming value
1207 * @retval The programmed HSE trimmign value
1208 */
HAL_RCCEx_HSEGetTrimming(void)1209 uint32_t HAL_RCCEx_HSEGetTrimming(void)
1210 {
1211 return ((RCC->ECSCR1 & RCC_ECSCR1_HSETRIM) >> RCC_ECSCR1_HSETRIM_Pos);
1212 }
1213
1214 /**
1215 * @brief Set LSE trimming value
1216 * @param Trimming specifies the Low Speed clock source to output.
1217 * This parameter can be one of the following values:
1218 * @arg @ref RCC_LSETRIMMING_R current source resistance R
1219 * @arg @ref RCC_LSETRIMMING_3_4_R current source resistance 3/4*R
1220 * @arg @ref RCC_LSETRIMMING_2_3_R current source resistance 2/3*R
1221 * @arg @ref RCC_LSETRIMMING_1_2_R current source resistance 1/2*R
1222 * @retval None
1223 */
HAL_RCCEx_LSESetTrimming(uint32_t Trimming)1224 void HAL_RCCEx_LSESetTrimming(uint32_t Trimming)
1225 {
1226 /* Check the parameters */
1227 assert_param(IS_RCC_LSETRIM(Trimming));
1228
1229 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSETRIM, Trimming);
1230 }
1231
1232 /**
1233 * @brief Get LSE trimming value
1234 * @retval The programmed LSE trimmign value
1235 */
HAL_RCCEx_LSEGetTrimming(void)1236 uint32_t HAL_RCCEx_LSEGetTrimming(void)
1237 {
1238 return (RCC->BDCR1 & RCC_BDCR1_LSETRIM);
1239 }
1240
1241 #if defined(RCC_LSI2_SUPPORT)
1242 /**
1243 * @brief Set LSI2 Configuration
1244 * @param pConfig pointer to an RCC_LSIConfigTypeDef structure that
1245 * contains the configuration information for the LSI2 oscillattor
1246 * @retval None
1247 */
HAL_RCCEx_LSI2SetConfig(const RCC_LSIConfigTypeDef * pConfig)1248 void HAL_RCCEx_LSI2SetConfig(const RCC_LSIConfigTypeDef *pConfig)
1249 {
1250 /* Check the parameters */
1251 assert_param(pConfig != NULL);
1252 assert_param(IS_RCC_LSI2_FREQTEMPSENS(pConfig->FreqTempSens));
1253 assert_param(IS_RCC_LSI2_OPERATINGMODE(pConfig->OpMode));
1254
1255 WRITE_REG(RCC->BDCR2, (pConfig->FreqTempSens | pConfig->OpMode));
1256 }
1257
1258 /**
1259 * @brief Set LSI2 Configuration
1260 * @param pConfig pointer to an RCC_LSIConfigTypeDef structure that
1261 * contains the configuration information for the LSI2 oscillattor
1262 * @retval None
1263 */
HAL_RCCEx_LSI2GetConfig(RCC_LSIConfigTypeDef * pConfig)1264 void HAL_RCCEx_LSI2GetConfig(RCC_LSIConfigTypeDef *pConfig)
1265 {
1266 uint32_t regbdcr2;
1267
1268 /* Check the parameters */
1269 assert_param(pConfig != NULL);
1270
1271 /* Get register value */
1272 regbdcr2 = RCC->BDCR2;
1273
1274 pConfig->FreqTempSens = (regbdcr2 & RCC_BDCR2_LSI2CFG);
1275 pConfig->OpMode = (regbdcr2 & RCC_BDCR2_LSI2MODE);
1276 }
1277
1278 #endif /* RCC_BDCR1_LSI2ON */
1279
1280 /**
1281 * @}
1282 */
1283
1284 /** @defgroup RCCEx_Exported_Functions_Group3 Radio clock management functions
1285 * @brief Radio clock management functions
1286 *
1287 @verbatim
1288 ===============================================================================
1289 ##### Extended radio clock management functions #####
1290 ===============================================================================
1291 [..]
1292 This subsection provides a set of functions allowing to control the
1293 radio-related parameters.
1294 @endverbatim
1295 * @{
1296 */
1297
1298 /**
1299 * @brief Enable the 2.4 GHz RADIO baseband clock
1300 * @retval None
1301 */
HAL_RCCEx_EnableRadioBBClock(void)1302 void HAL_RCCEx_EnableRadioBBClock(void)
1303 {
1304 SET_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN);
1305 }
1306
1307 /**
1308 * @brief Disable the 2.4 GHz RADIO baseband clock
1309 * @retval None
1310 */
HAL_RCCEx_DisableRadioBBClock(void)1311 void HAL_RCCEx_DisableRadioBBClock(void)
1312 {
1313 CLEAR_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN);
1314 }
1315
1316 /**
1317 * @brief Enable the 2.4 GHz RADIO bus clock and HSE32 oscillator by 2.4 GHz RADIO sleep timer wakeup event
1318 * @retval None
1319 */
HAL_RCCEx_EnableRequestUponRadioWakeUpEvent(void)1320 void HAL_RCCEx_EnableRequestUponRadioWakeUpEvent(void)
1321 {
1322 SET_BIT(RCC->RADIOENR, RCC_RADIOENR_STRADIOCLKON);
1323 }
1324
1325 /**
1326 * @brief Disable the 2.4 GHz RADIO bus clock and HSE32 oscillator by 2.4 GHz RADIO sleep timer wakeup event
1327 * @retval None
1328 */
HAL_RCCEx_DisableRequestUponRadioWakeUpEvent(void)1329 void HAL_RCCEx_DisableRequestUponRadioWakeUpEvent(void)
1330 {
1331 CLEAR_BIT(RCC->RADIOENR, RCC_RADIOENR_STRADIOCLKON);
1332 }
1333
1334 /**
1335 * @brief Get the 2.4 GHz RADIO bus clock readiness.
1336 * @note Indicate that the 2.4 GHz RADIO bus clock is ready and the 2.4 GHz RADIO registers can be accessed.
1337 * @note The output can be one of the following values :
1338 * @arg RCC_RADIO_BUS_CLOCK_NOT_READY : 2.4 GHz RADIO bus clock not ready.
1339 * @arg RCC_RADIO_BUS_CLOCK_READY : 2.4 GHz RADIO bus clock ready.
1340 * @retval The regulator REG_VDDHPA input supply selection.
1341 */
HAL_RCCEx_GetRadioBusClockReadiness(void)1342 uint32_t HAL_RCCEx_GetRadioBusClockReadiness(void)
1343 {
1344 return READ_BIT(RCC->RADIOENR, RCC_RADIOENR_RADIOCLKRDY);
1345 }
1346 /**
1347 * @}
1348 */
1349
1350 /**
1351 * @}
1352 */
1353
1354 #endif /* HAL_RCC_MODULE_ENABLED */
1355 /**
1356 * @}
1357 */
1358
1359 /**
1360 * @}
1361 */
1362
