1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U5xx_LL_PWR_H
21 #define STM32U5xx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif /* __cplusplus */
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u5xx.h"
29
30 /** @addtogroup STM32U5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /* Exported types ------------------------------------------------------------*/
45 /* Exported constants --------------------------------------------------------*/
46
47 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
48 * @{
49 */
50
51 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
52 * @brief Flags defines which can be used with LL_PWR_WriteReg function
53 * @{
54 */
55 #define LL_PWR_SR_CSSF PWR_SR_CSSF /*!< Clear Stop and Standby flags */
56 #define LL_PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1 /*!< Clear Wakeup flag 1 */
57 #define LL_PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2 /*!< Clear Wakeup flag 2 */
58 #define LL_PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3 /*!< Clear Wakeup flag 3 */
59 #define LL_PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4 /*!< Clear Wakeup flag 4 */
60 #define LL_PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5 /*!< Clear Wakeup flag 5 */
61 #define LL_PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6 /*!< Clear Wakeup flag 6 */
62 #define LL_PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7 /*!< Clear Wakeup flag 7 */
63 #define LL_PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8 /*!< Clear Wakeup flag 8 */
64 #define LL_PWR_WUSCR_CWUF_ALL PWR_WUSCR_CWUF /*!< Clear all Wakeup flags */
65 /**
66 * @}
67 */
68
69 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
70 * @brief Flags defines which can be used with LL_PWR_ReadReg function
71 * @{
72 */
73 #define LL_PWR_FLAG_VOSRDY PWR_VOSR_VOSRDY /*!< Voltage scaling ready flag */
74 #define LL_PWR_FLAG_BOOSTRDY PWR_VOSR_BOOSTRDY /*!< VOS EPOD booster ready flag */
75 #if defined (PWR_VOSR_USBBOOSTRDY)
76 #define LL_PWR_FLAG_USBBOOSTRDY PWR_VOSR_USBBOOSTRDY /*!< USB EPOD booster ready flag */
77 #endif /* defined (PWR_VOSR_USBBOOSTRDY) */
78 #define LL_PWR_FLAG_STOPF PWR_SR_STOPF /*!< Stop flag */
79 #define LL_PWR_FLAG_SBF PWR_SR_SBF /*!< Standby flag */
80 #define LL_PWR_FLAG_VDDA2RDY PWR_SVMSR_VDDA2RDY /*!< VDDA ready flag (versus 1.8 V threshold) */
81 #define LL_PWR_FLAG_VDDA1RDY PWR_SVMSR_VDDA1RDY /*!< VDDA ready flag (versus 1.6 V threshold) */
82 #define LL_PWR_FLAG_VDDIO2RDY PWR_SVMSR_VDDIO2RDY /*!< VDDIO2 ready flag */
83 #define LL_PWR_FLAG_VDDUSBRDY PWR_SVMSR_VDDUSBRDY /*!< VDDUSB ready flag */
84 #define LL_PWR_FLAG_ACTVOSRDY PWR_SVMSR_ACTVOSRDY /*!< Currently applied VOS ready flag */
85 #define LL_PWR_FLAG_PVDO PWR_SR2_PVDO /*!< VDD voltage detector output flag */
86 #define LL_PWR_FLAG_REGS PWR_SVMSR_REGS /*!< Regulator selection flag */
87 #define LL_PWR_FLAG_TEMPH PWR_BDSR_TEMPH /*!< Temperature level flag (versus high threshold) */
88 #define LL_PWR_FLAG_TEMPL PWR_BDSR_TEMPL /*!< Temperature level flag (versus low threshold) */
89 #define LL_PWR_FLAG_VBATH PWR_BDSR_VBATH /*!< Backup domain voltage level flag (versus high threshold) */
90
91 #define LL_PWR_WAKEUP_FLAG1 PWR_WUSR_WUF1 /*!< Wakeup flag 1 */
92 #define LL_PWR_WAKEUP_FLAG2 PWR_WUSR_WUF2 /*!< Wakeup flag 2 */
93 #define LL_PWR_WAKEUP_FLAG3 PWR_WUSR_WUF3 /*!< Wakeup flag 3 */
94 #define LL_PWR_WAKEUP_FLAG4 PWR_WUSR_WUF4 /*!< Wakeup flag 4 */
95 #define LL_PWR_WAKEUP_FLAG5 PWR_WUSR_WUF5 /*!< Wakeup flag 5 */
96 #define LL_PWR_WAKEUP_FLAG6 PWR_WUSR_WUF6 /*!< Wakeup flag 6 */
97 #define LL_PWR_WAKEUP_FLAG7 PWR_WUSR_WUF7 /*!< Wakeup flag 7 */
98 #define LL_PWR_WAKEUP_FLAG8 PWR_WUSR_WUF8 /*!< Wakeup flag 8 */
99 /**
100 * @}
101 */
102
103 /** @defgroup PWR_LL_EC_LOW_POWER_MODE_SELCTION Low Power Mode Selection
104 * @{
105 */
106 #define LL_PWR_STOP0_MODE (0U) /*!< Stop 0 mode */
107 #define LL_PWR_STOP1_MODE PWR_CR1_LPMS_0 /*!< Stop 1 mode */
108 #define LL_PWR_STOP2_MODE PWR_CR1_LPMS_1 /*!< Stop 2 mode */
109 #define LL_PWR_STOP3_MODE (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Stop 3 mode */
110 #define LL_PWR_STANDBY_MODE PWR_CR1_LPMS_2 /*!< Standby mode */
111 #define LL_PWR_SHUTDOWN_MODE (PWR_CR1_LPMS_2 | PWR_CR1_LPMS_1) /*!< Shutdown mode */
112 /**
113 * @}
114 */
115
116 /** @defgroup PWR_LL_EC_SRAM2_SB_CONTENTS_RETENTION PWR SRAM2 Content Retention in Standby Mode
117 * @note For some products of the U5 family (please see the Reference Manual),
118 * the SRAM2 content is preserved based on the same defines in Stop 3 mode.
119 * @{
120 */
121 #define LL_PWR_SRAM2_SB_NO_RETENTION 0U /*!< SRAM2 no retention in Stop 3 and Standby mode */
122 #define LL_PWR_SRAM2_SB_PAGE1_RETENTION PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby mode */
123 #define LL_PWR_SRAM2_SB_PAGE2_RETENTION PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby mode */
124 #define LL_PWR_SRAM2_SB_FULL_RETENTION (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby mode */
125 /**
126 * @}
127 */
128
129 /** @defgroup PWR_LL_EC_SRAM1_STOP_CONTENTS_RETENTION PWR SRAM1 Content Retention in Stop Mode
130 * @{
131 */
132 #define LL_PWR_SRAM1_STOP_NO_RETENTION 0U /*!< SRAM1 no retention in Stop mode (Stop 0, 1, 2, 3) */
133 #define LL_PWR_SRAM1_STOP_PAGE1_RETENTION (PWR_CR2_SRAM1PDS1) /*!< SRAM1 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
134 #define LL_PWR_SRAM1_STOP_PAGE2_RETENTION (PWR_CR2_SRAM1PDS2) /*!< SRAM1 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
135 #define LL_PWR_SRAM1_STOP_PAGE3_RETENTION (PWR_CR2_SRAM1PDS3) /*!< SRAM1 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
136 #if defined (PWR_CR4_SRAM1PDS4)
137 #define LL_PWR_SRAM1_STOP_PAGE4_RETENTION (PWR_CR4_SRAM1PDS4) /*!< SRAM1 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
138 #define LL_PWR_SRAM1_STOP_PAGE5_RETENTION (PWR_CR4_SRAM1PDS5) /*!< SRAM1 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
139 #define LL_PWR_SRAM1_STOP_PAGE6_RETENTION (PWR_CR4_SRAM1PDS6) /*!< SRAM1 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
140 #define LL_PWR_SRAM1_STOP_PAGE7_RETENTION (PWR_CR4_SRAM1PDS7) /*!< SRAM1 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
141 #define LL_PWR_SRAM1_STOP_PAGE8_RETENTION (PWR_CR4_SRAM1PDS8) /*!< SRAM1 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
142 #define LL_PWR_SRAM1_STOP_PAGE9_RETENTION (PWR_CR4_SRAM1PDS9) /*!< SRAM1 page 9 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
143 #define LL_PWR_SRAM1_STOP_PAGE10_RETENTION (PWR_CR4_SRAM1PDS10) /*!< SRAM1 page 10 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
144 #define LL_PWR_SRAM1_STOP_PAGE11_RETENTION (PWR_CR4_SRAM1PDS11) /*!< SRAM1 page 11 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
145 #define LL_PWR_SRAM1_STOP_PAGE12_RETENTION (PWR_CR4_SRAM1PDS12) /*!< SRAM1 page 12 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
146 #endif /* defined (PWR_CR4_SRAM1PDS4) */
147 #define LL_PWR_SRAM1_STOP_1_3_RETENTION (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 | \
148 PWR_CR2_SRAM1PDS3) /*!< SRAM1 pages (1 to 3) retention in Stop mode (Stop 0, 1, 2, 3) */
149 #if defined (PWR_CR4_SRAM1PDS4)
150 #define LL_PWR_SRAM1_STOP_4_12_RETENTION (PWR_CR4_SRAM1PDS4 | PWR_CR4_SRAM1PDS5 | \
151 PWR_CR4_SRAM1PDS6 | PWR_CR4_SRAM1PDS7 | \
152 PWR_CR4_SRAM1PDS8 | PWR_CR4_SRAM1PDS9 | \
153 PWR_CR4_SRAM1PDS10 | PWR_CR4_SRAM1PDS11 | \
154 PWR_CR4_SRAM1PDS12) /*!< SRAM1 pages (4 to 12) retention in Stop mode (Stop 0, 1, 2, 3) */
155 #endif /* defined (PWR_CR4_SRAM1PDS4) */
156 /**
157 * @}
158 */
159
160 /** @defgroup PWR_LL_EC_SRAM2_STOP_CONTENTS_RETENTION PWR SRAM2 Content Retention in Stop Mode
161 * @{
162 */
163 #define LL_PWR_SRAM2_STOP_NO_RETENTION 0U /*!< SRAM2 no retention in Stop mode (Stop 0, 1, 2) */
164 #define LL_PWR_SRAM2_STOP_PAGE1_RETENTION (PWR_CR2_SRAM2PDS1) /*!< SRAM2 page 1 (8 KB) retention in Stop mode (Stop 0, 1, 2) */
165 #define LL_PWR_SRAM2_STOP_PAGE2_RETENTION (PWR_CR2_SRAM2PDS2) /*!< SRAM2 page 2 (54 KB) retention in Stop mode (Stop 0, 1, 2) */
166 #define LL_PWR_SRAM2_STOP_FULL_RETENTION (PWR_CR2_SRAM2PDS1 | PWR_CR2_SRAM2PDS2) /*!< SRAM2 all pages retention in Stop mode (Stop 0, 1, 2) */
167 /**
168 * @}
169 */
170
171 #if defined (PWR_CR2_SRAM3PDS1)
172 /** @defgroup PWR_LL_EC_SRAM3_STOP_CONTENTS_RETENTION PWR SRAM3 Content Retention in Stop Mode
173 * @{
174 */
175 #define LL_PWR_SRAM3_STOP_NO_RETENTION 0U /*!< SRAM3 no retention in Stop mode (Stop 0, 1, 2, 3) */
176 #define LL_PWR_SRAM3_STOP_PAGE1_RETENTION (PWR_CR2_SRAM3PDS1) /*!< SRAM3 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
177 #define LL_PWR_SRAM3_STOP_PAGE2_RETENTION (PWR_CR2_SRAM3PDS2) /*!< SRAM3 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
178 #define LL_PWR_SRAM3_STOP_PAGE3_RETENTION (PWR_CR2_SRAM3PDS3) /*!< SRAM3 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
179 #define LL_PWR_SRAM3_STOP_PAGE4_RETENTION (PWR_CR2_SRAM3PDS4) /*!< SRAM3 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
180 #define LL_PWR_SRAM3_STOP_PAGE5_RETENTION (PWR_CR2_SRAM3PDS5) /*!< SRAM3 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
181 #define LL_PWR_SRAM3_STOP_PAGE6_RETENTION (PWR_CR2_SRAM3PDS6) /*!< SRAM3 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
182 #define LL_PWR_SRAM3_STOP_PAGE7_RETENTION (PWR_CR2_SRAM3PDS7) /*!< SRAM3 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
183 #define LL_PWR_SRAM3_STOP_PAGE8_RETENTION (PWR_CR2_SRAM3PDS8) /*!< SRAM3 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
184 #if defined (PWR_CR4_SRAM3PDS9)
185 #define LL_PWR_SRAM3_STOP_PAGE9_RETENTION (PWR_CR4_SRAM3PDS9) /*!< SRAM3 page 9 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
186 #define LL_PWR_SRAM3_STOP_PAGE10_RETENTION (PWR_CR4_SRAM3PDS10) /*!< SRAM3 page 10 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
187 #define LL_PWR_SRAM3_STOP_PAGE11_RETENTION (PWR_CR4_SRAM3PDS11) /*!< SRAM3 page 11 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
188 #define LL_PWR_SRAM3_STOP_PAGE12_RETENTION (PWR_CR4_SRAM3PDS12) /*!< SRAM3 page 12 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
189 #define LL_PWR_SRAM3_STOP_PAGE13_RETENTION (PWR_CR4_SRAM3PDS13) /*!< SRAM3 page 13 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
190 #endif /* defined (PWR_CR4_SRAM3PDS9) */
191 #define LL_PWR_SRAM3_STOP_1_8_RETENTION (PWR_CR2_SRAM3PDS1 | PWR_CR2_SRAM3PDS2 | PWR_CR2_SRAM3PDS3 | \
192 PWR_CR2_SRAM3PDS4 | PWR_CR2_SRAM3PDS5 | PWR_CR2_SRAM3PDS6 | \
193 PWR_CR2_SRAM3PDS7 | PWR_CR2_SRAM3PDS8) /*!< SRAM3 pages (1 to 8) retention in Stop modes (Stop 0, 1, 2, 3) */
194 #if defined (PWR_CR4_SRAM3PDS9)
195 #define LL_PWR_SRAM3_STOP_9_13_RETENTION (PWR_CR4_SRAM3PDS9 | PWR_CR4_SRAM3PDS10 | PWR_CR4_SRAM3PDS11 | \
196 PWR_CR4_SRAM3PDS12 | PWR_CR4_SRAM3PDS13) /*!< SRAM3 pages (9 to 13) retention in Stop modes (Stop 0, 1, 2, 3) */
197 #endif /* defined (PWR_CR4_SRAM3PDS9) */
198 /**
199 * @}
200 */
201 #endif /* PWR_CR2_SRAM3PDS1 */
202
203 /** @defgroup PWR_LL_EC_SRAM4_STOP_CONTENTS_RETENTION PWR SRAM4 Content Retention in Stop Mode
204 * @{
205 */
206 #define LL_PWR_SRAM4_STOP_NO_RETENTION 0U /*!< SRAM4 no retention in Stop mode (Stop 0, 1, 2) */
207 #define LL_PWR_SRAM4_STOP_FULL_RETENTION PWR_CR2_SRAM4PDS /*!< SRAM4 retention in Stop mode (Stop 0, 1, 2) */
208 /**
209 * @}
210 */
211
212 #if defined (PWR_CR4_SRAM5PDS1)
213 /** @defgroup PWR_LL_EC_SRAM5_STOP_CONTENTS_RETENTION PWR SRAM5 Content Retention in Stop Mode
214 * @{
215 */
216 #define LL_PWR_SRAM5_STOP_NO_RETENTION 0U /*!< SRAM5 no retention in Stop mode (Stop 0, 1, 2, 3) */
217 #define LL_PWR_SRAM5_STOP_PAGE1_RETENTION (PWR_CR4_SRAM5PDS1) /*!< SRAM5 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
218 #define LL_PWR_SRAM5_STOP_PAGE2_RETENTION (PWR_CR4_SRAM5PDS2) /*!< SRAM5 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
219 #define LL_PWR_SRAM5_STOP_PAGE3_RETENTION (PWR_CR4_SRAM5PDS3) /*!< SRAM5 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
220 #define LL_PWR_SRAM5_STOP_PAGE4_RETENTION (PWR_CR4_SRAM5PDS4) /*!< SRAM5 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
221 #define LL_PWR_SRAM5_STOP_PAGE5_RETENTION (PWR_CR4_SRAM5PDS5) /*!< SRAM5 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
222 #define LL_PWR_SRAM5_STOP_PAGE6_RETENTION (PWR_CR4_SRAM5PDS6) /*!< SRAM5 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
223 #define LL_PWR_SRAM5_STOP_PAGE7_RETENTION (PWR_CR4_SRAM5PDS7) /*!< SRAM5 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
224 #define LL_PWR_SRAM5_STOP_PAGE8_RETENTION (PWR_CR4_SRAM5PDS8) /*!< SRAM5 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
225 #define LL_PWR_SRAM5_STOP_PAGE9_RETENTION (PWR_CR4_SRAM5PDS9) /*!< SRAM5 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
226 #define LL_PWR_SRAM5_STOP_PAGE10_RETENTION (PWR_CR4_SRAM5PDS10) /*!< SRAM5 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
227 #define LL_PWR_SRAM5_STOP_PAGE11_RETENTION (PWR_CR4_SRAM5PDS11) /*!< SRAM5 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
228 #define LL_PWR_SRAM5_STOP_PAGE12_RETENTION (PWR_CR4_SRAM5PDS12) /*!< SRAM5 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
229 #define LL_PWR_SRAM5_STOP_PAGE13_RETENTION (PWR_CR4_SRAM5PDS13) /*!< SRAM5 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
230 #define LL_PWR_SRAM5_STOP_FULL_RETENTION (PWR_CR4_SRAM5PDS1 | PWR_CR4_SRAM5PDS2 | PWR_CR4_SRAM5PDS3 | \
231 PWR_CR4_SRAM5PDS4 | PWR_CR4_SRAM5PDS5 | PWR_CR4_SRAM5PDS6 | \
232 PWR_CR4_SRAM5PDS7 | PWR_CR4_SRAM5PDS8 | PWR_CR4_SRAM5PDS9 | \
233 PWR_CR4_SRAM5PDS10 | PWR_CR4_SRAM5PDS11 | PWR_CR4_SRAM5PDS12 | \
234 PWR_CR4_SRAM5PDS13) /*!< SRAM5 pages (1 to 13) retention in Stop modes (Stop 0, 1, 2, 3) */
235 /**
236 * @}
237 */
238 #endif /* defined (PWR_CR4_SRAM5PDS1) */
239
240 #if defined (PWR_CR5_SRAM6PDS1)
241 /** @defgroup PWR_LL_EC_SRAM6_STOP_CONTENTS_RETENTION PWR SRAM6 Content Retention in Stop Mode
242 * @{
243 */
244 #define LL_PWR_SRAM6_STOP_NO_RETENTION 0U /*!< SRAM6 no retention in Stop mode (Stop 0, 1, 2, 3) */
245 #define LL_PWR_SRAM6_STOP_PAGE1_RETENTION (PWR_CR5_SRAM6PDS1) /*!< SRAM6 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
246 #define LL_PWR_SRAM6_STOP_PAGE2_RETENTION (PWR_CR5_SRAM6PDS2) /*!< SRAM6 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
247 #define LL_PWR_SRAM6_STOP_PAGE3_RETENTION (PWR_CR5_SRAM6PDS3) /*!< SRAM6 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
248 #define LL_PWR_SRAM6_STOP_PAGE4_RETENTION (PWR_CR5_SRAM6PDS4) /*!< SRAM6 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
249 #define LL_PWR_SRAM6_STOP_PAGE5_RETENTION (PWR_CR5_SRAM6PDS5) /*!< SRAM6 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
250 #define LL_PWR_SRAM6_STOP_PAGE6_RETENTION (PWR_CR5_SRAM6PDS6) /*!< SRAM6 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
251 #define LL_PWR_SRAM6_STOP_PAGE7_RETENTION (PWR_CR5_SRAM6PDS7) /*!< SRAM6 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
252 #define LL_PWR_SRAM6_STOP_PAGE8_RETENTION (PWR_CR5_SRAM6PDS8) /*!< SRAM6 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
253 #define LL_PWR_SRAM6_STOP_FULL_RETENTION (PWR_CR5_SRAM6PDS1 | PWR_CR5_SRAM6PDS2 | PWR_CR5_SRAM6PDS3 | \
254 PWR_CR5_SRAM6PDS4 | PWR_CR5_SRAM6PDS5 | PWR_CR5_SRAM6PDS6 | \
255 PWR_CR5_SRAM6PDS7 | PWR_CR5_SRAM6PDS8)
256 /*!< SRAM6 pages (1 to 8) retention in Stop modes (Stop 0, 1, 2, 3) */
257 /**
258 * @}
259 */
260 #endif /* defined (PWR_CR5_SRAM6PDS1) */
261
262 /** @defgroup PWR_LL_EC_ICACHERAM_STOP_CONTENTS_RETENTION PWR ICACHE Content Retention in Stop Mode
263 * @{
264 */
265 #define LL_PWR_ICACHERAM_STOP_NO_RETENTION 0U /*!< ICACHE SRAM no retention in Stop mode (Stop 0, 1, 2) */
266 #define LL_PWR_ICACHERAM_STOP_FULL_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM retention in Stop mode (Stop 0, 1, 2) */
267 /**
268 * @}
269 */
270
271 /** @defgroup PWR_LL_EC_DCACHE1RAM_STOP_CONTENTS_RETENTION PWR DCACHE1 Content Retention in Stop Mode
272 * @{
273 */
274 #define LL_PWR_DCACHE1RAM_STOP_NO_RETENTION 0U /*!< DCACHE1 SRAM no retention in Stop mode (Stop 0, 1, 2) */
275 #define LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION PWR_CR2_DC1RAMPDS /*!< DCACHE1 SRAM retention in Stop mode (Stop 0, 1, 2) */
276 /**
277 * @}
278 */
279
280 #if defined (PWR_CR2_DC2RAMPDS)
281 /** @defgroup PWR_LL_EC_DCACHE2RAM_STOP_CONTENTS_RETENTION PWR DCACHE2 Content Retention in Stop Mode
282 * @{
283 */
284 #define LL_PWR_DCACHE2RAM_STOP_NO_RETENTION 0U /*!< DCACHE2 SRAM no retention in Stop mode (Stop 0, 1, 2) */
285 #define LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION PWR_CR2_DC2RAMPDS /*!< DCACHE2 SRAM retention in Stop mode (Stop 0, 1, 2) */
286 /**
287 * @}
288 */
289 #endif /* defined (PWR_CR2_DC2RAMPDS) */
290
291 #if defined (PWR_CR2_DMA2DRAMPDS)
292 /** @defgroup PWR_LL_EC_DMA2DRAM_STOP_CONTENTS_RETENTION PWR DMA2DRAM Content Retention in Stop Mode
293 * @{
294 */
295 #define LL_PWR_DMA2DRAM_STOP_NO_RETENTION 0U /*!< DMA2D SRAM no retention in Stop mode (Stop 0, 1, 2) */
296 #define LL_PWR_DMA2DRAM_STOP_FULL_RETENTION PWR_CR2_DMA2DRAMPDS /*!< DMA2D SRAM retention in Stop mode (Stop 0, 1, 2) */
297 /**
298 * @}
299 */
300 #endif /* PWR_CR2_DMA2DRAMPDS */
301
302 /** @defgroup PWR_LL_EC_PERIPHRAM_STOP_CONTENTS_RETENTION PWR PERIPHRAM Content Retention in Stop Mode
303 * @{
304 */
305 #define LL_PWR_PERIPHRAM_STOP_NO_RETENTION 0U /*!< FMAC, FDCAN and USB SRAM no retention in Stop mode (Stop 0, 1, 2) */
306 #define LL_PWR_PERIPHRAM_STOP_FULL_RETENTION PWR_CR2_PRAMPDS /*!< FMAC, FDCAN and USB SRAM retention in Stop mode (Stop 0, 1, 2) */
307 /**
308 * @}
309 */
310
311 /** @defgroup PWR_LL_EC_PKARAM_STOP_CONTENTS_RETENTION PWR PKARAM Content Retention in Stop Mode
312 * @{
313 */
314 #define LL_PWR_PKARAM_STOP_NO_RETENTION 0U /*!< PKA32 SRAM no retention in Stop mode (Stop 0, 1, 2) */
315 #define LL_PWR_PKARAM_STOP_FULL_RETENTION PWR_CR2_PKARAMPDS /*!< PKA32 SRAM retention in Stop mode (Stop 0, 1, 2) */
316 /**
317 * @}
318 */
319
320 #if defined (PWR_CR2_GPRAMPDS)
321 /** @defgroup PWR_LL_EC_GPRAM_STOP_CONTENTS_RETENTION PWR GPRAM Content Retention in Stop Mode
322 * @{
323 */
324 #define LL_PWR_GRAPHICPERIPHRAM_STOP_NO_RETENTION 0U /*!< Graphic peripherals (LTDC, GFXMMU) SRAM no retention in Stop mode (Stop 0, 1, 2) */
325 #define LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION PWR_CR2_GPRAMPDS /*!< Graphic peripherals (LTDC, GFXMMU) SRAM retention in Stop mode (Stop 0, 1, 2) */
326 /**
327 * @}
328 */
329 #endif /* defined (PWR_CR2_GPRAMPDS) */
330
331 #if defined (PWR_CR2_DSIRAMPDS)
332 /** @defgroup PWR_LL_EC_DSIRAM_STOP_CONTENTS_RETENTION PWR DSI RAM Content Retention in Stop Mode
333 * @{
334 */
335 #define LL_PWR_DSIRAM_STOP_NO_RETENTION 0U /*!< DSI SRAM no retention in Stop mode (Stop 0, 1, 2) */
336 #define LL_PWR_DSIRAM_STOP_FULL_RETENTION PWR_CR2_DSIRAMPDS /*!< DSI SRAM retention in Stop mode (Stop 0, 1, 2) */
337 /**
338 * @}
339 */
340 #endif /* defined (PWR_CR2_JPEGRAMPDS) */
341
342 #if defined (PWR_CR2_JPEGRAMPDS)
343 /** @defgroup PWR_LL_EC_JPEGRAM_STOP_CONTENTS_RETENTION PWR JPEG RAM Content Retention in Stop Mode
344 * @{
345 */
346 #define LL_PWR_JPEGRAM_STOP_NO_RETENTION 0U /*!< JPEG SRAM no retention in Stop mode (Stop 0, 1, 2) */
347 #define LL_PWR_JPEGRAM_STOP_FULL_RETENTION PWR_CR2_JPEGRAMPDS /*!< JPEG SRAM retention in Stop mode (Stop 0, 1, 2) */
348 /**
349 * @}
350 */
351 #endif /* defined (PWR_CR2_JPEGRAMPDS) */
352
353 /** @defgroup PWR_LL_EC_SRAM1_RUN_CONTENTS_RETENTION PWR SRAM1 Content Retention in Run Mode
354 * @{
355 */
356 #define LL_PWR_SRAM1_RUN_NO_RETENTION 0U /*!< SRAM1 no retention in Run mode */
357 #define LL_PWR_SRAM1_RUN_FULL_RETENTION PWR_CR1_SRAM1PD /*!< SRAM1 retention in Run mode */
358 /**
359 * @}
360 */
361
362 /** @defgroup PWR_LL_EC_SRAM2_RUN_CONTENTS_RETENTION PWR SRAM2 Content Retention in Run Mode
363 * @{
364 */
365 #define LL_PWR_SRAM2_RUN_NO_RETENTION 0U /*!< SRAM2 no retention in Run mode */
366 #define LL_PWR_SRAM2_RUN_FULL_RETENTION PWR_CR1_SRAM2PD /*!< SRAM2 retention in Run mode */
367 /**
368 * @}
369 */
370
371 #if defined (PWR_CR1_SRAM3PD)
372 /** @defgroup PWR_LL_EC_SRAM3_RUN_CONTENTS_RETENTION PWR SRAM3 Content Retention in Run Mode
373 * @{
374 */
375 #define LL_PWR_SRAM3_RUN_NO_RETENTION 0U /*!< SRAM3 no retention in Run mode */
376 #define LL_PWR_SRAM3_RUN_FULL_RETENTION PWR_CR1_SRAM3PD /*!< SRAM3 retention in Run mode */
377 /**
378 * @}
379 */
380 #endif /* PWR_CR1_SRAM3PD */
381
382 /** @defgroup PWR_LL_EC_SRAM4_RUN_CONTENTS_RETENTION PWR SRAM4 Content Retention in Run Mode
383 * @{
384 */
385 #define LL_PWR_SRAM4_RUN_NO_RETENTION 0U /*!< SRAM4 no retention in Run mode */
386 #define LL_PWR_SRAM4_RUN_FULL_RETENTION PWR_CR1_SRAM4PD /*!< SRAM4 retention in Run mode */
387 /**
388 * @}
389 */
390
391 #if defined (PWR_CR1_SRAM5PD)
392 /** @defgroup PWR_LL_EC_SRAM5_RUN_CONTENTS_RETENTION PWR SRAM5 Content Retention in Run Mode
393 * @{
394 */
395 #define LL_PWR_SRAM5_RUN_NO_RETENTION 0U /*!< SRAM5 no retention in Run mode */
396 #define LL_PWR_SRAM5_RUN_FULL_RETENTION PWR_CR1_SRAM5PD /*!< SRAM5 retention in Run mode */
397 /**
398 * @}
399 */
400 #endif /* defined (PWR_CR1_SRAM5PD) */
401
402 #if defined (PWR_CR1_SRAM6PD)
403 /** @defgroup PWR_LL_EC_SRAM6_RUN_CONTENTS_RETENTION PWR SRAM6 Content Retention in Run Mode
404 * @{
405 */
406 #define LL_PWR_SRAM6_RUN_NO_RETENTION 0U /*!< SRAM6 no retention in Run mode */
407 #define LL_PWR_SRAM6_RUN_FULL_RETENTION PWR_CR1_SRAM6PD /*!< SRAM6 retention in Run mode */
408 /**
409 * @}
410 */
411 #endif /* defined (PWR_CR1_SRAM6PD) */
412
413 /** @defgroup PWR_LL_EC_SRD_MODE PWR Smart Run Domain Mode
414 * @{
415 */
416 #define LL_PWR_SRD_STOP_MODE 0U /*!< SmartRun domain AHB3 and APB3 clocks disabled by default in Stop mode (Stop 0, 1, 2) */
417 #define LL_PWR_SRD_RUN_MODE PWR_CR2_SRDRUN /*!< SmartRun domain AHB3 and APB3 clocks kept enabled in Stop mode (Stop 0, 1, 2) */
418 /**
419 * @}
420 */
421
422 /** @defgroup PWR_LL_EC_REGULATOR_SUPPLY_SELECTION PWR Regulator Supply Selection
423 * @{
424 */
425 #define LL_PWR_LDO_SUPPLY 0U /*!< LDO regulator supply */
426 #define LL_PWR_SMPS_SUPPLY PWR_CR3_REGSEL /*!< SMPS regulator supply */
427 /**
428 * @}
429 */
430
431 /** @defgroup PWR_LL_EC_VOLTAGE_SCALING_RANGE_SELECTION PWR Voltage scaling range selection
432 * @{
433 */
434 #define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_VOSR_VOS /*!< Voltage scaling range 1 */
435 #define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_VOSR_VOS_1 /*!< Voltage scaling range 2 */
436 #define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_VOSR_VOS_0 /*!< Voltage scaling range 3 */
437 #define LL_PWR_REGU_VOLTAGE_SCALE4 0x00000000U /*!< Voltage scaling range 4 */
438 /**
439 * @}
440 */
441
442 /** @defgroup PWR_LL_EC_PVD_LEVEL_SELECTION PWR Power Voltage Detector Level Selection
443 * @{
444 */
445 #define LL_PWR_PVDLEVEL_0 0U /*!< Voltage threshold detected by PVD 2.0 V */
446 #define LL_PWR_PVDLEVEL_1 PWR_SVMCR_PVDLS_0 /*!< Voltage threshold detected by PVD 2.2 V */
447 #define LL_PWR_PVDLEVEL_2 PWR_SVMCR_PVDLS_1 /*!< Voltage threshold detected by PVD 2.4 V */
448 #define LL_PWR_PVDLEVEL_3 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_1) /*!< Voltage threshold detected by PVD 2.5 V */
449 #define LL_PWR_PVDLEVEL_4 PWR_SVMCR_PVDLS_2 /*!< Voltage threshold detected by PVD 2.6 V */
450 #define LL_PWR_PVDLEVEL_5 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.8 V */
451 #define LL_PWR_PVDLEVEL_6 (PWR_SVMCR_PVDLS_1 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.9 V */
452 #define LL_PWR_PVDLEVEL_7 PWR_SVMCR_PVDLS /*!< External input analog voltage on PVD_IN
453 pin, compared to internal VREFINT level */
454 /**
455 * @}
456 */
457
458 /** @defgroup PWR_LL_EC_WAKEUP_PIN PWR Wake Up Pin
459 * @{
460 */
461 #define LL_PWR_WAKEUP_PIN1 PWR_WUCR1_WUPEN1 /*!< Wakeup pin 1 enable */
462 #define LL_PWR_WAKEUP_PIN2 PWR_WUCR1_WUPEN2 /*!< Wakeup pin 2 enable */
463 #define LL_PWR_WAKEUP_PIN3 PWR_WUCR1_WUPEN3 /*!< Wakeup pin 3 enable */
464 #define LL_PWR_WAKEUP_PIN4 PWR_WUCR1_WUPEN4 /*!< Wakeup pin 4 enable */
465 #define LL_PWR_WAKEUP_PIN5 PWR_WUCR1_WUPEN5 /*!< Wakeup pin 5 enable */
466 #define LL_PWR_WAKEUP_PIN6 PWR_WUCR1_WUPEN6 /*!< Wakeup pin 6 enable */
467 #define LL_PWR_WAKEUP_PIN7 PWR_WUCR1_WUPEN7 /*!< Wakeup pin 7 enable */
468 #define LL_PWR_WAKEUP_PIN8 PWR_WUCR1_WUPEN8 /*!< Wakeup pin 8 enable */
469 /**
470 * @}
471 */
472
473 /** @defgroup PWR_LL_EC_WAKEUP_PIN_SELECTION PWR Wakeup Pin Selection
474 * @{
475 */
476 #define LL_PWR_WAKEUP_PIN_SELECTION_0 0UL /*!< Wakeup pin selection 0 */
477 #define LL_PWR_WAKEUP_PIN_SELECTION_1 PWR_WUCR3_WUSEL1_0 /*!< Wakeup pin selection 1 */
478 #define LL_PWR_WAKEUP_PIN_SELECTION_2 PWR_WUCR3_WUSEL1_1 /*!< Wakeup pin selection 2 */
479 #define LL_PWR_WAKEUP_PIN_SELECTION_3 PWR_WUCR3_WUSEL1 /*!< Wakeup pin selection 3 */
480 /**
481 * @}
482 */
483
484 /** @defgroup PWR_LL_EC_CHARGING_RESISTOR_SELECTION PWR VBAT Charging Resistor Selection
485 * @{
486 */
487 #define LL_PWR_BATT_CHARG_RESISTOR_5K 0U /*!< Charge the battery through a 5 kO resistor */
488 #define LL_PWR_BATT_CHARG_RESISTOR_1_5K PWR_BDCR2_VBRS /*!< Charge the battery through a 1.5 kO resistor */
489 /**
490 * @}
491 */
492
493 /** @defgroup PWR_LL_EC_GPIO_PORT_SELECTION PWR GPIO Port Selection
494 * @{
495 */
496 #define LL_PWR_GPIO_PORTA (&(PWR->PUCRA)) /*!< GPIO port A */
497 #define LL_PWR_GPIO_PORTB (&(PWR->PUCRB)) /*!< GPIO port B */
498 #define LL_PWR_GPIO_PORTC (&(PWR->PUCRC)) /*!< GPIO port C */
499 #define LL_PWR_GPIO_PORTD (&(PWR->PUCRD)) /*!< GPIO port D */
500 #define LL_PWR_GPIO_PORTE (&(PWR->PUCRE)) /*!< GPIO port E */
501 #ifdef PWR_PUCRF_PU0
502 #define LL_PWR_GPIO_PORTF (&(PWR->PUCRF)) /*!< GPIO port F */
503 #endif /* PWR_PUCRF_PU0 */
504 #define LL_PWR_GPIO_PORTG (&(PWR->PUCRG)) /*!< GPIO port G */
505 #define LL_PWR_GPIO_PORTH (&(PWR->PUCRH)) /*!< GPIO port H */
506 #ifdef PWR_PUCRI_PU0
507 #define LL_PWR_GPIO_PORTI (&(PWR->PUCRI)) /*!< GPIO port I */
508 #endif /* PWR_PUCRI_PU0 */
509 #if defined (PWR_PUCRJ_PU0)
510 #define LL_PWR_GPIO_PORTJ (&(PWR->PUCRJ)) /*!< GPIO port J */
511 #endif /* defined (PWR_PUCRJ_PU0) */
512 /**
513 * @}
514 */
515
516 /** @defgroup PWR_LL_EC_GPIO_PIN_MASK PWR GPIO Pin Mask
517 * @{
518 */
519 #define LL_PWR_GPIO_PIN_0 (0x0001U) /*!< GPIO port I/O pin 0 */
520 #define LL_PWR_GPIO_PIN_1 (0x0002U) /*!< GPIO port I/O pin 1 */
521 #define LL_PWR_GPIO_PIN_2 (0x0004U) /*!< GPIO port I/O pin 2 */
522 #define LL_PWR_GPIO_PIN_3 (0x0008U) /*!< GPIO port I/O pin 3 */
523 #define LL_PWR_GPIO_PIN_4 (0x0010U) /*!< GPIO port I/O pin 4 */
524 #define LL_PWR_GPIO_PIN_5 (0x0020U) /*!< GPIO port I/O pin 5 */
525 #define LL_PWR_GPIO_PIN_6 (0x0040U) /*!< GPIO port I/O pin 6 */
526 #define LL_PWR_GPIO_PIN_7 (0x0080U) /*!< GPIO port I/O pin 7 */
527 #define LL_PWR_GPIO_PIN_8 (0x0100U) /*!< GPIO port I/O pin 8 */
528 #define LL_PWR_GPIO_PIN_9 (0x0200U) /*!< GPIO port I/O pin 9 */
529 #define LL_PWR_GPIO_PIN_10 (0x0400U) /*!< GPIO port I/O pin 10 */
530 #define LL_PWR_GPIO_PIN_11 (0x0800U) /*!< GPIO port I/O pin 11 */
531 #define LL_PWR_GPIO_PIN_12 (0x1000U) /*!< GPIO port I/O pin 12 */
532 #define LL_PWR_GPIO_PIN_13 (0x2000U) /*!< GPIO port I/O pin 13 */
533 #define LL_PWR_GPIO_PIN_14 (0x4000U) /*!< GPIO port I/O pin 14 */
534 #define LL_PWR_GPIO_PIN_15 (0x8000U) /*!< GPIO port I/O pin 15 */
535 /**
536 * @}
537 */
538
539 /** @defgroup PWR_LL_EC_ITEMS_SECURE_ATTRIBUTE PWR Items Secure Attribute
540 * @{
541 */
542 #define LL_PWR_WAKEUP_PIN1_NSEC 0U /*!< Wake up pin 1 nsecure mode */
543 #define LL_PWR_WAKEUP_PIN1_SEC PWR_SECCFGR_WUP1SEC /*!< Wake up pin 1 secure mode */
544 #define LL_PWR_WAKEUP_PIN2_NSEC 0U /*!< Wake up pin 2 nsecure mode */
545 #define LL_PWR_WAKEUP_PIN2_SEC PWR_SECCFGR_WUP2SEC /*!< Wake up pin 2 secure mode */
546 #define LL_PWR_WAKEUP_PIN3_NSEC 0U /*!< Wake up pin 3 nsecure mode */
547 #define LL_PWR_WAKEUP_PIN3_SEC PWR_SECCFGR_WUP3SEC /*!< Wake up pin 3 secure mode */
548 #define LL_PWR_WAKEUP_PIN4_NSEC 0U /*!< Wake up pin 4 nsecure mode */
549 #define LL_PWR_WAKEUP_PIN4_SEC PWR_SECCFGR_WUP4SEC /*!< Wake up pin 4 secure mode */
550 #define LL_PWR_WAKEUP_PIN5_NSEC 0U /*!< Wake up pin 5 nsecure mode */
551 #define LL_PWR_WAKEUP_PIN5_SEC PWR_SECCFGR_WUP5SEC /*!< Wake up pin 5 secure mode */
552 #define LL_PWR_WAKEUP_PIN6_NSEC 0U /*!< Wake up pin 6 nsecure mode */
553 #define LL_PWR_WAKEUP_PIN6_SEC PWR_SECCFGR_WUP6SEC /*!< Wake up pin 6 secure mode */
554 #define LL_PWR_WAKEUP_PIN7_NSEC 0U /*!< Wake up pin 7 nsecure mode */
555 #define LL_PWR_WAKEUP_PIN7_SEC PWR_SECCFGR_WUP7SEC /*!< Wake up pin 7 secure mode */
556 #define LL_PWR_WAKEUP_PIN8_NSEC 0U /*!< Wake up pin 8 nsecure mode */
557 #define LL_PWR_WAKEUP_PIN8_SEC PWR_SECCFGR_WUP8SEC /*!< Wake up pin 8 secure mode */
558
559 #define LL_PWR_LPM_NSEC 0U /*!< Low-power modes nsecure mode */
560 #define LL_PWR_LPM_SEC PWR_SECCFGR_WUP8SEC /*!< Low-power modes secure mode */
561 #define LL_PWR_VDM_NSEC 0U /*!< Voltage detection and monitoring nsecure mode */
562 #define LL_PWR_VDM_SEC PWR_SECCFGR_WUP8SEC /*!< Voltage detection and monitoring secure mode */
563 #define LL_PWR_VB_NSEC 0U /*!< Backup domain nsecure mode */
564 #define LL_PWR_VB_SEC PWR_SECCFGR_WUP8SEC /*!< Backup domain secure mode */
565 #define LL_PWR_APC_NSEC 0U /*!< Pull-up/pull-down nsecure mode */
566 #define LL_PWR_APC_SEC PWR_SECCFGR_WUP8SEC /*!< Pull-up/pull-down secure mode */
567 /**
568 * @}
569 */
570
571 /**
572 * @}
573 */
574
575 /* Exported macro ------------------------------------------------------------*/
576
577 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
578 * @{
579 */
580
581 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and Read Registers Macros
582 * @{
583 */
584
585 /**
586 * @brief Write a value in PWR register.
587 * @param __REG__ Register to be written.
588 * @param __VALUE__ Value to be written in the register.
589 * @retval None.
590 */
591 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
592
593 /**
594 * @brief Read a value in PWR register.
595 * @param __REG__ Register to be read.
596 * @retval Register value.
597 */
598 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
599 /**
600 * @}
601 */
602
603 /**
604 * @}
605 */
606
607 /* Exported functions --------------------------------------------------------*/
608
609 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
610 * @{
611 */
612
613 /** @defgroup PWR_LL_EF_CONFIGURATION PWR Configuration
614 * @{
615 */
616
617 /**
618 * @brief Set system power mode.
619 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
620 * @param Mode : This parameter can be one of the following values:
621 * @arg @ref LL_PWR_STOP0_MODE
622 * @arg @ref LL_PWR_STOP1_MODE
623 * @arg @ref LL_PWR_STOP2_MODE
624 * @arg @ref LL_PWR_STOP3_MODE
625 * @arg @ref LL_PWR_STANDBY_MODE
626 * @arg @ref LL_PWR_SHUTDOWN_MODE
627 * @retval None
628 */
LL_PWR_SetPowerMode(uint32_t Mode)629 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t Mode)
630 {
631 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, Mode);
632 }
633
634 /**
635 * @brief Get system power mode.
636 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
637 * @retval Returned value can be one of the following values:
638 * @arg @ref LL_PWR_STOP0_MODE
639 * @arg @ref LL_PWR_STOP1_MODE
640 * @arg @ref LL_PWR_STOP2_MODE
641 * @arg @ref LL_PWR_STOP3_MODE
642 * @arg @ref LL_PWR_STANDBY_MODE
643 * @arg @ref LL_PWR_SHUTDOWN_MODE
644 */
LL_PWR_GetPowerMode(void)645 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
646 {
647 return (READ_BIT(PWR->CR1, PWR_CR1_LPMS));
648 }
649
650 /**
651 * @brief Set the SRAM2 page(s) retention in Standby mode.
652 * @rmtoll CR1 RRSB1 LL_PWR_SetSRAM2SBRetention\n
653 * @rmtoll CR1 RRSB2 LL_PWR_SetSRAM2SBRetention
654 * @param SRAM2PageRetention : This parameter can be one of the following values:
655 * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION
656 * @arg @ref LL_PWR_SRAM2_SB_PAGE1_RETENTION
657 * @arg @ref LL_PWR_SRAM2_SB_PAGE2_RETENTION
658 * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION
659 * @retval None
660 */
LL_PWR_SetSRAM2SBRetention(uint32_t SRAM2PageRetention)661 __STATIC_INLINE void LL_PWR_SetSRAM2SBRetention(uint32_t SRAM2PageRetention)
662 {
663 MODIFY_REG(PWR->CR1, LL_PWR_SRAM2_SB_FULL_RETENTION, SRAM2PageRetention);
664 }
665
666 /**
667 * @brief Get the SRAM2 page(s) retention in Standby mode.
668 * @rmtoll CR1 RRSB1 LL_PWR_GetSRAM2SBRetention\n
669 * @rmtoll CR1 RRSB2 LL_PWR_GetSRAM2SBRetention
670 * @retval Returned value can be one of the following values:
671 * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION
672 * @arg @ref LL_PWR_SRAM2_SB_PAGE1_RETENTION
673 * @arg @ref LL_PWR_SRAM2_SB_PAGE2_RETENTION
674 * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION
675 */
LL_PWR_GetSRAM2SBRetention(void)676 __STATIC_INLINE uint32_t LL_PWR_GetSRAM2SBRetention(void)
677 {
678 return (READ_BIT(PWR->CR1, (PWR_CR1_RRSB1 | PWR_CR1_RRSB2)));
679 }
680
681 /**
682 * @brief Enable BOR ultra low power mode.
683 * @rmtoll CR1 UPLMEN LL_PWR_EnableUltraLowPowerMode
684 * @retval None
685 */
LL_PWR_EnableUltraLowPowerMode(void)686 __STATIC_INLINE void LL_PWR_EnableUltraLowPowerMode(void)
687 {
688 SET_BIT(PWR->CR1, PWR_CR1_ULPMEN);
689 }
690
691 /**
692 * @brief Disable BOR ultra low-power mode.
693 * @rmtoll CR1 UPLMEN LL_PWR_DisableUltraLowPowerMode
694 * @retval None
695 */
LL_PWR_DisableUltraLowPowerMode(void)696 __STATIC_INLINE void LL_PWR_DisableUltraLowPowerMode(void)
697 {
698 CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN);
699 }
700
701 /**
702 * @brief Check if BOR ultra low power mode is enabled.
703 * @rmtoll CR1 UPLMEN LL_PWR_IsEnabledUltraLowPowerMode
704 * @retval State of bit (1 or 0).
705 */
LL_PWR_IsEnabledUltraLowPowerMode(void)706 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPowerMode(void)
707 {
708 return ((READ_BIT(PWR->CR1, PWR_CR1_ULPMEN) == (PWR_CR1_ULPMEN)) ? 1UL : 0UL);
709 }
710
711 /**
712 * @brief Set the SRAM1 retention in Run mode.
713 * @rmtoll CR1 SRAM1PD LL_PWR_SetSRAM1RunRetention\n
714 * @param SRAM1Retention : This parameter can be one of the following values:
715 * @arg @ref LL_PWR_SRAM1_RUN_NO_RETENTION
716 * @arg @ref LL_PWR_SRAM1_RUN_FULL_RETENTION
717 * @retval None
718 */
LL_PWR_SetSRAM1RunRetention(uint32_t SRAM1Retention)719 __STATIC_INLINE void LL_PWR_SetSRAM1RunRetention(uint32_t SRAM1Retention)
720 {
721 MODIFY_REG(PWR->CR1, LL_PWR_SRAM1_RUN_FULL_RETENTION, ((~SRAM1Retention) & LL_PWR_SRAM1_RUN_FULL_RETENTION));
722 }
723
724 /**
725 * @brief Get the SRAM1 retention in Run mode.
726 * @rmtoll CR1 SRAM1PD LL_PWR_GetSRAM1RunRetention\n
727 * @retval Returned value can be one of the following values:
728 * @arg @ref LL_PWR_SRAM1_RUN_NO_RETENTION
729 * @arg @ref LL_PWR_SRAM1_RUN_FULL_RETENTION
730 */
LL_PWR_GetSRAM1RunRetention(void)731 __STATIC_INLINE uint32_t LL_PWR_GetSRAM1RunRetention(void)
732 {
733 return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM1_RUN_FULL_RETENTION))) & LL_PWR_SRAM1_RUN_FULL_RETENTION);
734 }
735
736 /**
737 * @brief Set the SRAM2 retention in Run mode.
738 * @rmtoll CR1 SRAM2PD LL_PWR_SetSRAM2RunRetention\n
739 * @param SRAM2Retention : This parameter can be one of the following values:
740 * @arg @ref LL_PWR_SRAM2_RUN_NO_RETENTION
741 * @arg @ref LL_PWR_SRAM2_RUN_FULL_RETENTION
742 * @retval None
743 */
LL_PWR_SetSRAM2RunRetention(uint32_t SRAM2Retention)744 __STATIC_INLINE void LL_PWR_SetSRAM2RunRetention(uint32_t SRAM2Retention)
745 {
746 MODIFY_REG(PWR->CR1, LL_PWR_SRAM2_RUN_FULL_RETENTION, ((~SRAM2Retention) & LL_PWR_SRAM2_RUN_FULL_RETENTION));
747 }
748
749 /**
750 * @brief Get the SRAM2 retention in Run mode.
751 * @rmtoll CR1 SRAM2PD LL_PWR_GetSRAM2RunRetention\n
752 * @retval Returned value can be one of the following values:
753 * @arg @ref LL_PWR_SRAM2_RUN_NO_RETENTION
754 * @arg @ref LL_PWR_SRAM2_RUN_FULL_RETENTION
755 */
LL_PWR_GetSRAM2RunRetention(void)756 __STATIC_INLINE uint32_t LL_PWR_GetSRAM2RunRetention(void)
757 {
758 return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM2_RUN_FULL_RETENTION))) & LL_PWR_SRAM2_RUN_FULL_RETENTION);
759 }
760
761 #if defined (PWR_CR1_SRAM3PD)
762 /**
763 * @brief Set the SRAM3 retention in Run mode.
764 * @rmtoll CR1 SRAM3PD LL_PWR_SetSRAM3RunRetention\n
765 * @param SRAM3Retention : This parameter can be one of the following values:
766 * @arg @ref LL_PWR_SRAM3_RUN_NO_RETENTION
767 * @arg @ref LL_PWR_SRAM3_RUN_FULL_RETENTION
768 * @retval None
769 */
LL_PWR_SetSRAM3RunRetention(uint32_t SRAM3Retention)770 __STATIC_INLINE void LL_PWR_SetSRAM3RunRetention(uint32_t SRAM3Retention)
771 {
772 MODIFY_REG(PWR->CR1, LL_PWR_SRAM3_RUN_FULL_RETENTION, ((~SRAM3Retention) & LL_PWR_SRAM3_RUN_FULL_RETENTION));
773 }
774
775 /**
776 * @brief Get the SRAM3 retention in Run mode.
777 * @rmtoll CR1 SRAM3PD LL_PWR_GetSRAM3RunRetention\n
778 * @retval Returned value can be one of the following values:
779 * @arg @ref LL_PWR_SRAM3_RUN_NO_RETENTION
780 * @arg @ref LL_PWR_SRAM3_RUN_FULL_RETENTION
781 */
LL_PWR_GetSRAM3RunRetention(void)782 __STATIC_INLINE uint32_t LL_PWR_GetSRAM3RunRetention(void)
783 {
784 return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM3_RUN_FULL_RETENTION))) & LL_PWR_SRAM3_RUN_FULL_RETENTION);
785 }
786 #endif /* PWR_CR1_SRAM3PD */
787
788 /**
789 * @brief Set the SRAM4 retention in Run mode.
790 * @rmtoll CR1 SRAM4PD LL_PWR_SetSRAM4RunRetention\n
791 * @param SRAM4Retention : This parameter can be one of the following values:
792 * @arg @ref LL_PWR_SRAM4_RUN_NO_RETENTION
793 * @arg @ref LL_PWR_SRAM4_RUN_FULL_RETENTION
794 * @retval None
795 */
LL_PWR_SetSRAM4RunRetention(uint32_t SRAM4Retention)796 __STATIC_INLINE void LL_PWR_SetSRAM4RunRetention(uint32_t SRAM4Retention)
797 {
798 MODIFY_REG(PWR->CR1, LL_PWR_SRAM4_RUN_FULL_RETENTION, ((~SRAM4Retention) & LL_PWR_SRAM4_RUN_FULL_RETENTION));
799 }
800
801 /**
802 * @brief Get the SRAM4 retention in Run mode.
803 * @rmtoll CR1 SRAM4PD LL_PWR_GetSRAM4RunRetention\n
804 * @retval Returned value can be one of the following values:
805 * @arg @ref LL_PWR_SRAM4_RUN_NO_RETENTION
806 * @arg @ref LL_PWR_SRAM4_RUN_FULL_RETENTION
807 */
LL_PWR_GetSRAM4RunRetention(void)808 __STATIC_INLINE uint32_t LL_PWR_GetSRAM4RunRetention(void)
809 {
810 return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM4_RUN_FULL_RETENTION))) & LL_PWR_SRAM4_RUN_FULL_RETENTION);
811 }
812
813 #if defined (PWR_CR1_SRAM5PD)
814 /**
815 * @brief Set the SRAM5 retention in Run mode.
816 * @rmtoll CR1 SRAM5PD LL_PWR_SetSRAM5RunRetention\n
817 * @param SRAM5Retention : This parameter can be one of the following values:
818 * @arg @ref LL_PWR_SRAM5_RUN_NO_RETENTION
819 * @arg @ref LL_PWR_SRAM5_RUN_FULL_RETENTION
820 * @retval None
821 */
LL_PWR_SetSRAM5RunRetention(uint32_t SRAM5Retention)822 __STATIC_INLINE void LL_PWR_SetSRAM5RunRetention(uint32_t SRAM5Retention)
823 {
824 MODIFY_REG(PWR->CR1, LL_PWR_SRAM5_RUN_FULL_RETENTION, ((~SRAM5Retention) & LL_PWR_SRAM5_RUN_FULL_RETENTION));
825 }
826
827 /**
828 * @brief Get the SRAM5 retention in Run mode.
829 * @rmtoll CR1 SRAM5PD LL_PWR_GetSRAM5RunRetention\n
830 * @retval Returned value can be one of the following values:
831 * @arg @ref LL_PWR_SRAM5_RUN_NO_RETENTION
832 * @arg @ref LL_PWR_SRAM5_RUN_FULL_RETENTION
833 */
LL_PWR_GetSRAM5RunRetention(void)834 __STATIC_INLINE uint32_t LL_PWR_GetSRAM5RunRetention(void)
835 {
836 return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM5_RUN_FULL_RETENTION))) & LL_PWR_SRAM5_RUN_FULL_RETENTION);
837 }
838 #endif /* defined (PWR_CR1_SRAM5PD) */
839
840 #if defined (PWR_CR1_SRAM6PD)
841 /**
842 * @brief Set the SRAM6 retention in Run mode.
843 * @rmtoll CR1 SRAM6PD LL_PWR_SetSRAM6RunRetention\n
844 * @param SRAM6Retention : This parameter can be one of the following values:
845 * @arg @ref LL_PWR_SRAM6_RUN_NO_RETENTION
846 * @arg @ref LL_PWR_SRAM6_RUN_FULL_RETENTION
847 * @retval None
848 */
LL_PWR_SetSRAM6RunRetention(uint32_t SRAM6Retention)849 __STATIC_INLINE void LL_PWR_SetSRAM6RunRetention(uint32_t SRAM6Retention)
850 {
851 MODIFY_REG(PWR->CR1, LL_PWR_SRAM6_RUN_FULL_RETENTION, ((~SRAM6Retention) & LL_PWR_SRAM6_RUN_FULL_RETENTION));
852 }
853
854 /**
855 * @brief Get the SRAM6 retention in Run mode.
856 * @rmtoll CR1 SRAM6PD LL_PWR_GetSRAM6RunRetention\n
857 * @retval Returned value can be one of the following values:
858 * @arg @ref LL_PWR_SRAM6_RUN_NO_RETENTION
859 * @arg @ref LL_PWR_SRAM6_RUN_FULL_RETENTION
860 */
LL_PWR_GetSRAM6RunRetention(void)861 __STATIC_INLINE uint32_t LL_PWR_GetSRAM6RunRetention(void)
862 {
863 return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM6_RUN_FULL_RETENTION))) & LL_PWR_SRAM6_RUN_FULL_RETENTION);
864 }
865 #endif /* defined (PWR_CR1_SRAM6PD) */
866
867 #if defined (PWR_CR1_FORCE_USBPWR)
868 /**
869 * @brief Enable OTG_HS PHY power during low power modes (Stop2, Stop 3 and Standby).
870 * @rmtoll CR1 FORCE_USBPWR LL_PWR_EnableOTGHSPHYLowPowerRetention
871 * @retval None
872 */
LL_PWR_EnableOTGHSPHYLowPowerRetention(void)873 __STATIC_INLINE void LL_PWR_EnableOTGHSPHYLowPowerRetention(void)
874 {
875 SET_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR);
876 }
877
878 /**
879 * @brief Disable OTG_HS PHY power during low power modes (Stop2, Stop 3 and Standby).
880 * @rmtoll CR1 FORCE_USBPWR LL_PWR_DisableOTGHSPHYLowPowerRetention
881 * @retval None
882 */
LL_PWR_DisableOTGHSPHYLowPowerRetention(void)883 __STATIC_INLINE void LL_PWR_DisableOTGHSPHYLowPowerRetention(void)
884 {
885 CLEAR_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR);
886 }
887
888 /**
889 * @brief Check if OTG_HS PHY power during low power modes (Stop2, Stop 3 and Standby) is enabled.
890 * @rmtoll CR1 FORCE_USBPWR LL_PWR_IsEnabledOTGHSPHYLowPowerRetention
891 * @retval State of bit (1 or 0).
892 */
LL_PWR_IsEnabledOTGHSPHYLowPowerRetention(void)893 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOTGHSPHYLowPowerRetention(void)
894 {
895 return ((READ_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR) == (PWR_CR1_FORCE_USBPWR)) ? 1UL : 0UL);
896 }
897 #endif /* defined (PWR_CR1_FORCE_USBPWR) */
898
899 /**
900 * @brief Set the SRAM1 page(s) (From page 1 to page 3) retention in Stop mode.
901 * @rmtoll CR2 SRAM1PDS1 LL_PWR_SetSRAM1StopRetention_1_3\n
902 * @rmtoll CR2 SRAM1PDS2 LL_PWR_SetSRAM1StopRetention_1_3\n
903 * @rmtoll CR2 SRAM1PDS3 LL_PWR_SetSRAM1StopRetention_1_3
904 * @param SRAM1PageRetention : This parameter can be one of the following values:
905 * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION
906 * @arg @ref LL_PWR_SRAM1_STOP_1_3_RETENTION
907 * Or can be a combination of the following values:
908 * @arg @ref LL_PWR_SRAM1_STOP_PAGE1_RETENTION
909 * @arg @ref LL_PWR_SRAM1_STOP_PAGE2_RETENTION
910 * @arg @ref LL_PWR_SRAM1_STOP_PAGE3_RETENTION
911 * @retval None
912 */
LL_PWR_SetSRAM1StopRetention_1_3(uint32_t SRAM1PageRetention)913 __STATIC_INLINE void LL_PWR_SetSRAM1StopRetention_1_3(uint32_t SRAM1PageRetention)
914 {
915 MODIFY_REG(PWR->CR2, LL_PWR_SRAM1_STOP_1_3_RETENTION, ((~SRAM1PageRetention) & LL_PWR_SRAM1_STOP_1_3_RETENTION));
916 }
917
918 #if defined (PWR_CR4_SRAM1PDS4)
919 /**
920 * @brief Set the SRAM1 page(s) (From page 4 to page 12) retention in Stop mode.
921 * @rmtoll CR2 SRAM1PDS4 LL_PWR_SetSRAM1StopRetention_4_12\n
922 * @rmtoll CR2 SRAM1PDS5 LL_PWR_SetSRAM1StopRetention_4_12\n
923 * @rmtoll CR2 SRAM1PDS6 LL_PWR_SetSRAM1StopRetention_4_12\n
924 * @rmtoll CR2 SRAM1PDS7 LL_PWR_SetSRAM1StopRetention_4_12\n
925 * @rmtoll CR2 SRAM1PDS8 LL_PWR_SetSRAM1StopRetention_4_12\n
926 * @rmtoll CR2 SRAM1PDS9 LL_PWR_SetSRAM1StopRetention_4_12\n
927 * @rmtoll CR2 SRAM1PDS10 LL_PWR_SetSRAM1StopRetention_4_12\n
928 * @rmtoll CR2 SRAM1PDS11 LL_PWR_SetSRAM1StopRetention_4_12\n
929 * @rmtoll CR2 SRAM1PDS12 LL_PWR_SetSRAM1StopRetention_4_12
930 * @param SRAM1PageRetention : This parameter can be one of the following values:
931 * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION
932 * @arg @ref LL_PWR_SRAM1_STOP_4_12_RETENTION
933 * Or can be a combination of the following values:
934 * @arg @ref LL_PWR_SRAM1_STOP_PAGE4_RETENTION
935 * @arg @ref LL_PWR_SRAM1_STOP_PAGE5_RETENTION
936 * @arg @ref LL_PWR_SRAM1_STOP_PAGE6_RETENTION
937 * @arg @ref LL_PWR_SRAM1_STOP_PAGE7_RETENTION
938 * @arg @ref LL_PWR_SRAM1_STOP_PAGE8_RETENTION
939 * @arg @ref LL_PWR_SRAM1_STOP_PAGE9_RETENTION
940 * @arg @ref LL_PWR_SRAM1_STOP_PAGE10_RETENTION
941 * @arg @ref LL_PWR_SRAM1_STOP_PAGE11_RETENTION
942 * @arg @ref LL_PWR_SRAM1_STOP_PAGE12_RETENTION
943 * @retval None
944 */
LL_PWR_SetSRAM1StopRetention_4_12(uint32_t SRAM1PageRetention)945 __STATIC_INLINE void LL_PWR_SetSRAM1StopRetention_4_12(uint32_t SRAM1PageRetention)
946 {
947 MODIFY_REG(PWR->CR4, LL_PWR_SRAM1_STOP_4_12_RETENTION, ((~SRAM1PageRetention) & LL_PWR_SRAM1_STOP_4_12_RETENTION));
948 }
949 #endif /* defined (PWR_CR4_SRAM1PDS4) */
950
951 /**
952 * @brief Get the SRAM1 page(s) (From page 1 to page 3) retention in Stop mode.
953 * @rmtoll CR2 SRAM1PDS1 LL_PWR_GetSRAM1StopRetention_1_3\n
954 * @rmtoll CR2 SRAM1PDS2 LL_PWR_GetSRAM1StopRetention_1_3\n
955 * @rmtoll CR2 SRAM1PDS3 LL_PWR_GetSRAM1StopRetention_1_3
956 * @retval Returned value can be one of the following values:
957 * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION
958 * @arg @ref LL_PWR_SRAM1_STOP_1_3_RETENTION
959 * Or a combination of the following values:
960 * @arg @ref LL_PWR_SRAM1_STOP_PAGE1_RETENTION
961 * @arg @ref LL_PWR_SRAM1_STOP_PAGE2_RETENTION
962 * @arg @ref LL_PWR_SRAM1_STOP_PAGE3_RETENTION
963 */
LL_PWR_GetSRAM1StopRetention_1_3(void)964 __STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention_1_3(void)
965 {
966 return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM1_STOP_1_3_RETENTION))) & LL_PWR_SRAM1_STOP_1_3_RETENTION);
967 }
968
969 #if defined (PWR_CR4_SRAM1PDS4)
970 /**
971 * @brief Get the SRAM1 page(s) (From page 4 to page 12) retention in Stop mode.
972 * @rmtoll CR2 SRAM1PDS4 LL_PWR_GetSRAM1StopRetention_4_12\n
973 * @rmtoll CR2 SRAM1PDS5 LL_PWR_GetSRAM1StopRetention_4_12\n
974 * @rmtoll CR2 SRAM1PDS6 LL_PWR_GetSRAM1StopRetention_4_12\n
975 * @rmtoll CR2 SRAM1PDS7 LL_PWR_GetSRAM1StopRetention_4_12\n
976 * @rmtoll CR2 SRAM1PDS8 LL_PWR_GetSRAM1StopRetention_4_12\n
977 * @rmtoll CR2 SRAM1PDS9 LL_PWR_GetSRAM1StopRetention_4_12\n
978 * @rmtoll CR2 SRAM1PDS10 LL_PWR_GetSRAM1StopRetention_4_12\n
979 * @rmtoll CR2 SRAM1PDS11 LL_PWR_GetSRAM1StopRetention_4_12\n
980 * @rmtoll CR2 SRAM1PDS12 LL_PWR_GetSRAM1StopRetention_4_12
981 * @retval Returned value can be one of the following values:
982 * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION
983 * @arg @ref LL_PWR_SRAM1_STOP_4_12_RETENTION
984 * Or a combination of the following values:
985 * @arg @ref LL_PWR_SRAM1_STOP_PAGE4_RETENTION
986 * @arg @ref LL_PWR_SRAM1_STOP_PAGE5_RETENTION
987 * @arg @ref LL_PWR_SRAM1_STOP_PAGE6_RETENTION
988 * @arg @ref LL_PWR_SRAM1_STOP_PAGE7_RETENTION
989 * @arg @ref LL_PWR_SRAM1_STOP_PAGE8_RETENTION
990 * @arg @ref LL_PWR_SRAM1_STOP_PAGE9_RETENTION
991 * @arg @ref LL_PWR_SRAM1_STOP_PAGE10_RETENTION
992 * @arg @ref LL_PWR_SRAM1_STOP_PAGE11_RETENTION
993 * @arg @ref LL_PWR_SRAM1_STOP_PAGE12_RETENTION
994 */
LL_PWR_GetSRAM1StopRetention_4_12(void)995 __STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention_4_12(void)
996 {
997 return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM1_STOP_4_12_RETENTION))) & LL_PWR_SRAM1_STOP_4_12_RETENTION);
998 }
999 #endif /* defined (PWR_CR4_SRAM1PDS4) */
1000
1001 /**
1002 * @brief Set the SRAM2 page(s) retention in Stop mode.
1003 * @rmtoll CR2 SRAM2PDS1 LL_PWR_SetSRAM2StopRetention\n
1004 * @rmtoll CR2 SRAM2PDS2 LL_PWR_SetSRAM2StopRetention
1005 * @param SRAM2PageRetention : This parameter can be one of the following values:
1006 * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION
1007 * @arg @ref LL_PWR_SRAM2_STOP_PAGE1_RETENTION
1008 * @arg @ref LL_PWR_SRAM2_STOP_PAGE2_RETENTION
1009 * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION
1010 * @retval None
1011 */
LL_PWR_SetSRAM2StopRetention(uint32_t SRAM2PageRetention)1012 __STATIC_INLINE void LL_PWR_SetSRAM2StopRetention(uint32_t SRAM2PageRetention)
1013 {
1014 MODIFY_REG(PWR->CR2, LL_PWR_SRAM2_STOP_FULL_RETENTION, ((~SRAM2PageRetention) & LL_PWR_SRAM2_STOP_FULL_RETENTION));
1015 }
1016
1017 /**
1018 * @brief Get the SRAM2 page(s) retention in Stop mode.
1019 * @rmtoll CR2 SRAM2PDS1 LL_PWR_GetSRAM2StopRetention\n
1020 * @rmtoll CR2 SRAM2PDS2 LL_PWR_GetSRAM2StopRetention
1021 * @retval Returned value can be one of the following values:
1022 * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION
1023 * @arg @ref LL_PWR_SRAM2_STOP_PAGE1_RETENTION
1024 * @arg @ref LL_PWR_SRAM2_STOP_PAGE2_RETENTION
1025 * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION
1026 */
LL_PWR_GetSRAM2StopRetention(void)1027 __STATIC_INLINE uint32_t LL_PWR_GetSRAM2StopRetention(void)
1028 {
1029 return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM2_STOP_FULL_RETENTION))) & LL_PWR_SRAM2_STOP_FULL_RETENTION);
1030 }
1031
1032 #if defined (PWR_CR2_SRAM3PDS1)
1033 /**
1034 * @brief Set the SRAM3 page(s) (From page 1 to page 8) retention in Stop mode.
1035 * @rmtoll CR2 SRAM3PDS1 LL_PWR_SetSRAM3StopRetention_1_8\n
1036 * @rmtoll CR2 SRAM3PDS2 LL_PWR_SetSRAM3StopRetention_1_8\n
1037 * @rmtoll CR2 SRAM3PDS3 LL_PWR_SetSRAM3StopRetention_1_8\n
1038 * @rmtoll CR2 SRAM3PDS4 LL_PWR_SetSRAM3StopRetention_1_8\n
1039 * @rmtoll CR2 SRAM3PDS5 LL_PWR_SetSRAM3StopRetention_1_8\n
1040 * @rmtoll CR2 SRAM3PDS6 LL_PWR_SetSRAM3StopRetention_1_8\n
1041 * @rmtoll CR2 SRAM3PDS7 LL_PWR_SetSRAM3StopRetention_1_8\n
1042 * @rmtoll CR2 SRAM3PDS8 LL_PWR_SetSRAM3StopRetention_1_8
1043 * @param SRAM3PageRetention : This parameter can be one of the following values:
1044 * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION
1045 * @arg @ref LL_PWR_SRAM3_STOP_1_8_RETENTION
1046 * Or can be a combination of the following values:
1047 * @arg @ref LL_PWR_SRAM3_STOP_PAGE1_RETENTION
1048 * @arg @ref LL_PWR_SRAM3_STOP_PAGE2_RETENTION
1049 * @arg @ref LL_PWR_SRAM3_STOP_PAGE3_RETENTION
1050 * @arg @ref LL_PWR_SRAM3_STOP_PAGE4_RETENTION
1051 * @arg @ref LL_PWR_SRAM3_STOP_PAGE5_RETENTION
1052 * @arg @ref LL_PWR_SRAM3_STOP_PAGE6_RETENTION
1053 * @arg @ref LL_PWR_SRAM3_STOP_PAGE7_RETENTION
1054 * @arg @ref LL_PWR_SRAM3_STOP_PAGE8_RETENTION
1055 * @retval None
1056 */
LL_PWR_SetSRAM3StopRetention_1_8(uint32_t SRAM3PageRetention)1057 __STATIC_INLINE void LL_PWR_SetSRAM3StopRetention_1_8(uint32_t SRAM3PageRetention)
1058 {
1059 MODIFY_REG(PWR->CR2, LL_PWR_SRAM3_STOP_1_8_RETENTION, ((~SRAM3PageRetention) & LL_PWR_SRAM3_STOP_1_8_RETENTION));
1060 }
1061
1062 #if defined (PWR_CR4_SRAM3PDS9)
1063 /**
1064 * @brief Set the SRAM3 page(s) (From page 9 to page 13) retention in Stop mode.
1065 * @rmtoll CR2 SRAM3PDS9 LL_PWR_SetSRAM3StopRetention_9_13\n
1066 * @rmtoll CR2 SRAM3PDS10 LL_PWR_SetSRAM3StopRetention_9_13\n
1067 * @rmtoll CR2 SRAM3PDS11 LL_PWR_SetSRAM3StopRetention_9_13\n
1068 * @rmtoll CR2 SRAM3PDS12 LL_PWR_SetSRAM3StopRetention_9_13\n
1069 * @rmtoll CR2 SRAM3PDS13 LL_PWR_SetSRAM3StopRetention_9_13
1070 * @param SRAM3PageRetention : This parameter can be one of the following values:
1071 * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION
1072 * @arg @ref LL_PWR_SRAM3_STOP_9_13_RETENTION
1073 * Or can be a combination of the following values:
1074 * @arg @ref LL_PWR_SRAM3_STOP_PAGE9_RETENTION
1075 * @arg @ref LL_PWR_SRAM3_STOP_PAGE10_RETENTION
1076 * @arg @ref LL_PWR_SRAM3_STOP_PAGE11_RETENTION
1077 * @arg @ref LL_PWR_SRAM3_STOP_PAGE12_RETENTION
1078 * @arg @ref LL_PWR_SRAM3_STOP_PAGE13_RETENTION
1079 * @retval None
1080 */
LL_PWR_SetSRAM3StopRetention_9_13(uint32_t SRAM3PageRetention)1081 __STATIC_INLINE void LL_PWR_SetSRAM3StopRetention_9_13(uint32_t SRAM3PageRetention)
1082 {
1083 MODIFY_REG(PWR->CR4, LL_PWR_SRAM3_STOP_9_13_RETENTION, ((~SRAM3PageRetention) & LL_PWR_SRAM3_STOP_9_13_RETENTION));
1084 }
1085 #endif /* defined (PWR_CR4_SRAM3PDS9) */
1086
1087 /**
1088 * @brief Get the SRAM3 page(s) (From page 1 to page 8) retention in Stop mode.
1089 * @rmtoll CR2 SRAM3PDS1 LL_PWR_GetSRAM3StopRetention_1_8\n
1090 * @rmtoll CR2 SRAM3PDS2 LL_PWR_GetSRAM3StopRetention_1_8\n
1091 * @rmtoll CR2 SRAM3PDS3 LL_PWR_GetSRAM3StopRetention_1_8\n
1092 * @rmtoll CR2 SRAM3PDS4 LL_PWR_GetSRAM3StopRetention_1_8\n
1093 * @rmtoll CR2 SRAM3PDS5 LL_PWR_GetSRAM3StopRetention_1_8\n
1094 * @rmtoll CR2 SRAM3PDS6 LL_PWR_GetSRAM3StopRetention_1_8\n
1095 * @rmtoll CR2 SRAM3PDS7 LL_PWR_GetSRAM3StopRetention_1_8\n
1096 * @rmtoll CR2 SRAM3PDS8 LL_PWR_GetSRAM3StopRetention_1_8
1097 * @retval Returned value can be one of the following values:
1098 * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION
1099 * @arg @ref LL_PWR_SRAM3_STOP_1_8_RETENTION
1100 * Or can be a combination of the following values:
1101 * @arg @ref LL_PWR_SRAM3_STOP_PAGE1_RETENTION
1102 * @arg @ref LL_PWR_SRAM3_STOP_PAGE2_RETENTION
1103 * @arg @ref LL_PWR_SRAM3_STOP_PAGE3_RETENTION
1104 * @arg @ref LL_PWR_SRAM3_STOP_PAGE4_RETENTION
1105 * @arg @ref LL_PWR_SRAM3_STOP_PAGE5_RETENTION
1106 * @arg @ref LL_PWR_SRAM3_STOP_PAGE6_RETENTION
1107 * @arg @ref LL_PWR_SRAM3_STOP_PAGE7_RETENTION
1108 * @arg @ref LL_PWR_SRAM3_STOP_PAGE8_RETENTION
1109 */
LL_PWR_GetSRAM3StopRetention_1_8(void)1110 __STATIC_INLINE uint32_t LL_PWR_GetSRAM3StopRetention_1_8(void)
1111 {
1112 return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM3_STOP_1_8_RETENTION))) & LL_PWR_SRAM3_STOP_1_8_RETENTION);
1113 }
1114
1115 #if defined (PWR_CR4_SRAM3PDS9)
1116 /**
1117 * @brief Get the SRAM3 page(s) (From page 9 to page 13) retention in Stop mode.
1118 * @rmtoll CR2 SRAM3PDS9 LL_PWR_SetSRAM3StopRetention_9_13\n
1119 * @rmtoll CR2 SRAM3PDS10 LL_PWR_SetSRAM3StopRetention_9_13\n
1120 * @rmtoll CR2 SRAM3PDS11 LL_PWR_SetSRAM3StopRetention_9_13\n
1121 * @rmtoll CR2 SRAM3PDS12 LL_PWR_SetSRAM3StopRetention_9_13\n
1122 * @rmtoll CR2 SRAM3PDS13 LL_PWR_SetSRAM3StopRetention_9_13
1123 * @retval Returned value can be one of the following values:
1124 * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION
1125 * @arg @ref LL_PWR_SRAM3_STOP_9_13_RETENTION
1126 * Or can be a combination of the following values:
1127 * @arg @ref LL_PWR_SRAM3_STOP_PAGE9_RETENTION
1128 * @arg @ref LL_PWR_SRAM3_STOP_PAGE10_RETENTION
1129 * @arg @ref LL_PWR_SRAM3_STOP_PAGE11_RETENTION
1130 * @arg @ref LL_PWR_SRAM3_STOP_PAGE12_RETENTION
1131 * @arg @ref LL_PWR_SRAM3_STOP_PAGE13_RETENTION
1132 */
LL_PWR_GetSRAM3StopRetention_9_13(void)1133 __STATIC_INLINE uint32_t LL_PWR_GetSRAM3StopRetention_9_13(void)
1134 {
1135 return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM3_STOP_9_13_RETENTION))) & LL_PWR_SRAM3_STOP_9_13_RETENTION);
1136 }
1137 #endif /* defined (PWR_CR4_SRAM3PDS9) */
1138 #endif /* PWR_CR2_SRAM3PDS1 */
1139
1140 /**
1141 * @brief Set the SRAM4 page retention in Stop mode.
1142 * @rmtoll CR2 SRAM4PDS LL_PWR_SetSRAM4StopRetention\n
1143 * @param SRAM4PageRetention : This parameter can be one of the following values:
1144 * @arg @ref LL_PWR_SRAM4_STOP_NO_RETENTION
1145 * @arg @ref LL_PWR_SRAM4_STOP_FULL_RETENTION
1146 * @retval None
1147 */
LL_PWR_SetSRAM4StopRetention(uint32_t SRAM4PageRetention)1148 __STATIC_INLINE void LL_PWR_SetSRAM4StopRetention(uint32_t SRAM4PageRetention)
1149 {
1150 MODIFY_REG(PWR->CR2, LL_PWR_SRAM4_STOP_FULL_RETENTION, ((~SRAM4PageRetention) & LL_PWR_SRAM4_STOP_FULL_RETENTION));
1151 }
1152
1153 /**
1154 * @brief Get the SRAM4 page retention in Stop mode.
1155 * @rmtoll CR2 SRAM4PDS LL_PWR_GetSRAM4StopRetention
1156 * @retval Returned value can be one of the following values:
1157 * @arg @ref LL_PWR_SRAM4_STOP_NO_RETENTION
1158 * @arg @ref LL_PWR_SRAM4_STOP_FULL_RETENTION
1159 */
LL_PWR_GetSRAM4StopRetention(void)1160 __STATIC_INLINE uint32_t LL_PWR_GetSRAM4StopRetention(void)
1161 {
1162 return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM4_STOP_FULL_RETENTION))) & LL_PWR_SRAM4_STOP_FULL_RETENTION);
1163 }
1164
1165 #if defined (PWR_CR4_SRAM5PDS1)
1166 /**
1167 * @brief Set the SRAM5 page(s) retention in Stop mode.
1168 * @rmtoll CR4 SRAM5PDS1 LL_PWR_SetSRAM5StopRetention\n
1169 * @rmtoll CR4 SRAM5PDS2 LL_PWR_SetSRAM5StopRetention\n
1170 * @rmtoll CR4 SRAM5PDS3 LL_PWR_SetSRAM5StopRetention\n
1171 * @rmtoll CR4 SRAM5PDS4 LL_PWR_SetSRAM5StopRetention\n
1172 * @rmtoll CR4 SRAM5PDS5 LL_PWR_SetSRAM5StopRetention\n
1173 * @rmtoll CR4 SRAM5PDS6 LL_PWR_SetSRAM5StopRetention\n
1174 * @rmtoll CR4 SRAM5PDS7 LL_PWR_SetSRAM5StopRetention\n
1175 * @rmtoll CR4 SRAM5PDS8 LL_PWR_SetSRAM5StopRetention\n
1176 * @rmtoll CR4 SRAM5PDS9 LL_PWR_SetSRAM5StopRetention\n
1177 * @rmtoll CR4 SRAM5PDS10 LL_PWR_SetSRAM5StopRetention\n
1178 * @rmtoll CR4 SRAM5PDS11 LL_PWR_SetSRAM5StopRetention\n
1179 * @rmtoll CR4 SRAM5PDS12 LL_PWR_SetSRAM5StopRetention\n
1180 * @rmtoll CR4 SRAM5PDS13 LL_PWR_SetSRAM5StopRetention
1181 * @param SRAM5PageRetention : This parameter can be one of the following values:
1182 * @arg @ref LL_PWR_SRAM5_STOP_NO_RETENTION
1183 * @arg @ref LL_PWR_SRAM5_STOP_FULL_RETENTION
1184 * Or can be a combination of the following values:
1185 * @arg @ref LL_PWR_SRAM5_STOP_PAGE1_RETENTION
1186 * @arg @ref LL_PWR_SRAM5_STOP_PAGE2_RETENTION
1187 * @arg @ref LL_PWR_SRAM5_STOP_PAGE3_RETENTION
1188 * @arg @ref LL_PWR_SRAM5_STOP_PAGE4_RETENTION
1189 * @arg @ref LL_PWR_SRAM5_STOP_PAGE5_RETENTION
1190 * @arg @ref LL_PWR_SRAM5_STOP_PAGE6_RETENTION
1191 * @arg @ref LL_PWR_SRAM5_STOP_PAGE7_RETENTION
1192 * @arg @ref LL_PWR_SRAM5_STOP_PAGE8_RETENTION
1193 * @arg @ref LL_PWR_SRAM5_STOP_PAGE9_RETENTION
1194 * @arg @ref LL_PWR_SRAM5_STOP_PAGE10_RETENTION
1195 * @arg @ref LL_PWR_SRAM5_STOP_PAGE11_RETENTION
1196 * @arg @ref LL_PWR_SRAM5_STOP_PAGE12_RETENTION
1197 * @arg @ref LL_PWR_SRAM5_STOP_PAGE13_RETENTION
1198 * @retval None
1199 */
LL_PWR_SetSRAM5StopRetention(uint32_t SRAM5PageRetention)1200 __STATIC_INLINE void LL_PWR_SetSRAM5StopRetention(uint32_t SRAM5PageRetention)
1201 {
1202 MODIFY_REG(PWR->CR4, LL_PWR_SRAM5_STOP_FULL_RETENTION, ((~SRAM5PageRetention) & LL_PWR_SRAM5_STOP_FULL_RETENTION));
1203 }
1204
1205 /**
1206 * @brief Get the SRAM5 page(s) retention in Stop mode.
1207 * @rmtoll CR4 SRAM5PDS1 LL_PWR_GetSRAM5StopRetention\n
1208 * @rmtoll CR4 SRAM5PDS2 LL_PWR_GetSRAM5StopRetention\n
1209 * @rmtoll CR4 SRAM5PDS3 LL_PWR_GetSRAM5StopRetention\n
1210 * @rmtoll CR4 SRAM5PDS4 LL_PWR_GetSRAM5StopRetention\n
1211 * @rmtoll CR4 SRAM5PDS5 LL_PWR_GetSRAM5StopRetention\n
1212 * @rmtoll CR4 SRAM5PDS6 LL_PWR_GetSRAM5StopRetention\n
1213 * @rmtoll CR4 SRAM5PDS7 LL_PWR_GetSRAM5StopRetention\n
1214 * @rmtoll CR4 SRAM5PDS8 LL_PWR_GetSRAM5StopRetention\n
1215 * @rmtoll CR4 SRAM5PDS9 LL_PWR_GetSRAM5StopRetention\n
1216 * @rmtoll CR4 SRAM5PDS10 LL_PWR_GetSRAM5StopRetention\n
1217 * @rmtoll CR4 SRAM5PDS11 LL_PWR_GetSRAM5StopRetention\n
1218 * @rmtoll CR4 SRAM5PDS12 LL_PWR_GetSRAM5StopRetention\n
1219 * @rmtoll CR4 SRAM5PDS13 LL_PWR_GetSRAM5StopRetention
1220 * @retval Returned value can be one of the following values:
1221 * @arg @ref LL_PWR_SRAM5_STOP_NO_RETENTION
1222 * @arg @ref LL_PWR_SRAM5_STOP_FULL_RETENTION
1223 * Or can be a combination of the following values:
1224 * @arg @ref LL_PWR_SRAM5_STOP_PAGE1_RETENTION
1225 * @arg @ref LL_PWR_SRAM5_STOP_PAGE2_RETENTION
1226 * @arg @ref LL_PWR_SRAM5_STOP_PAGE3_RETENTION
1227 * @arg @ref LL_PWR_SRAM5_STOP_PAGE4_RETENTION
1228 * @arg @ref LL_PWR_SRAM5_STOP_PAGE5_RETENTION
1229 * @arg @ref LL_PWR_SRAM5_STOP_PAGE6_RETENTION
1230 * @arg @ref LL_PWR_SRAM5_STOP_PAGE7_RETENTION
1231 * @arg @ref LL_PWR_SRAM5_STOP_PAGE8_RETENTION
1232 * @arg @ref LL_PWR_SRAM5_STOP_PAGE9_RETENTION
1233 * @arg @ref LL_PWR_SRAM5_STOP_PAGE10_RETENTION
1234 * @arg @ref LL_PWR_SRAM5_STOP_PAGE11_RETENTION
1235 * @arg @ref LL_PWR_SRAM5_STOP_PAGE12_RETENTION
1236 * @arg @ref LL_PWR_SRAM5_STOP_PAGE13_RETENTION
1237 */
LL_PWR_GetSRAM5StopRetention(void)1238 __STATIC_INLINE uint32_t LL_PWR_GetSRAM5StopRetention(void)
1239 {
1240 return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM5_STOP_FULL_RETENTION))) & LL_PWR_SRAM5_STOP_FULL_RETENTION);
1241 }
1242 #endif /* defined (PWR_CR4_SRAM5PDS1) */
1243
1244 #if defined (PWR_CR5_SRAM6PDS1)
1245 /**
1246 * @brief Set the SRAM6 page(s) retention in Stop mode.
1247 * @rmtoll CR5 SRAM6PDS1 LL_PWR_SetSRAM6StopRetention\n
1248 * @rmtoll CR5 SRAM6PDS2 LL_PWR_SetSRAM6StopRetention\n
1249 * @rmtoll CR5 SRAM6PDS3 LL_PWR_SetSRAM6StopRetention\n
1250 * @rmtoll CR5 SRAM6PDS4 LL_PWR_SetSRAM6StopRetention\n
1251 * @rmtoll CR5 SRAM6PDS5 LL_PWR_SetSRAM6StopRetention\n
1252 * @rmtoll CR5 SRAM6PDS6 LL_PWR_SetSRAM6StopRetention\n
1253 * @rmtoll CR5 SRAM6PDS7 LL_PWR_SetSRAM6StopRetention\n
1254 * @rmtoll CR5 SRAM6PDS8 LL_PWR_SetSRAM6StopRetention
1255 * @param SRAM6PageRetention : This parameter can be one of the following values:
1256 * @arg @ref LL_PWR_SRAM6_STOP_NO_RETENTION
1257 * @arg @ref LL_PWR_SRAM6_STOP_FULL_RETENTION
1258 * Or can be a combination of the following values:
1259 * @arg @ref LL_PWR_SRAM6_STOP_PAGE1_RETENTION
1260 * @arg @ref LL_PWR_SRAM6_STOP_PAGE2_RETENTION
1261 * @arg @ref LL_PWR_SRAM6_STOP_PAGE3_RETENTION
1262 * @arg @ref LL_PWR_SRAM6_STOP_PAGE4_RETENTION
1263 * @arg @ref LL_PWR_SRAM6_STOP_PAGE5_RETENTION
1264 * @arg @ref LL_PWR_SRAM6_STOP_PAGE6_RETENTION
1265 * @arg @ref LL_PWR_SRAM6_STOP_PAGE7_RETENTION
1266 * @arg @ref LL_PWR_SRAM6_STOP_PAGE8_RETENTION
1267 * @retval None
1268 */
LL_PWR_SetSRAM6StopRetention(uint32_t SRAM6PageRetention)1269 __STATIC_INLINE void LL_PWR_SetSRAM6StopRetention(uint32_t SRAM6PageRetention)
1270 {
1271 MODIFY_REG(PWR->CR5, LL_PWR_SRAM6_STOP_FULL_RETENTION, ((~SRAM6PageRetention) & LL_PWR_SRAM6_STOP_FULL_RETENTION));
1272 }
1273
1274 /**
1275 * @brief Get the SRAM6 page(s) retention in Stop mode.
1276 * @rmtoll CR5 SRAM6PDS1 LL_PWR_GetSRAM6StopRetention\n
1277 * @rmtoll CR5 SRAM6PDS2 LL_PWR_GetSRAM6StopRetention\n
1278 * @rmtoll CR5 SRAM6PDS3 LL_PWR_GetSRAM6StopRetention\n
1279 * @rmtoll CR5 SRAM6PDS4 LL_PWR_GetSRAM6StopRetention\n
1280 * @rmtoll CR5 SRAM6PDS5 LL_PWR_GetSRAM6StopRetention\n
1281 * @rmtoll CR5 SRAM6PDS6 LL_PWR_GetSRAM6StopRetention\n
1282 * @rmtoll CR5 SRAM6PDS7 LL_PWR_GetSRAM6StopRetention\n
1283 * @rmtoll CR5 SRAM6PDS8 LL_PWR_GetSRAM6StopRetention
1284 * @retval Returned value can be one of the following values:
1285 * @arg @ref LL_PWR_SRAM6_STOP_NO_RETENTION
1286 * @arg @ref LL_PWR_SRAM6_STOP_FULL_RETENTION
1287 * Or can be a combination of the following values:
1288 * @arg @ref LL_PWR_SRAM6_STOP_PAGE1_RETENTION
1289 * @arg @ref LL_PWR_SRAM6_STOP_PAGE2_RETENTION
1290 * @arg @ref LL_PWR_SRAM6_STOP_PAGE3_RETENTION
1291 * @arg @ref LL_PWR_SRAM6_STOP_PAGE4_RETENTION
1292 * @arg @ref LL_PWR_SRAM6_STOP_PAGE5_RETENTION
1293 * @arg @ref LL_PWR_SRAM6_STOP_PAGE6_RETENTION
1294 * @arg @ref LL_PWR_SRAM6_STOP_PAGE7_RETENTION
1295 * @arg @ref LL_PWR_SRAM6_STOP_PAGE8_RETENTION
1296 */
LL_PWR_GetSRAM6StopRetention(void)1297 __STATIC_INLINE uint32_t LL_PWR_GetSRAM6StopRetention(void)
1298 {
1299 return ((~(READ_BIT(PWR->CR5, LL_PWR_SRAM6_STOP_FULL_RETENTION))) & LL_PWR_SRAM6_STOP_FULL_RETENTION);
1300 }
1301 #endif /* defined (PWR_CR5_SRAM6PDS1) */
1302
1303 /**
1304 * @brief Set the ICACHE SRAM page retention in Stop mode.
1305 * @rmtoll CR2 ICRAMPDS LL_PWR_SetICacheRAMStopRetention\n
1306 * @param ICachePageRetention : This parameter can be one of the following values:
1307 * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION
1308 * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION
1309 * @retval None
1310 */
LL_PWR_SetICacheRAMStopRetention(uint32_t ICachePageRetention)1311 __STATIC_INLINE void LL_PWR_SetICacheRAMStopRetention(uint32_t ICachePageRetention)
1312 {
1313 MODIFY_REG(PWR->CR2, LL_PWR_ICACHERAM_STOP_FULL_RETENTION,
1314 ((~ICachePageRetention) & LL_PWR_ICACHERAM_STOP_FULL_RETENTION));
1315 }
1316
1317 /**
1318 * @brief Get the ICACHE SRAM page retention in Stop mode.
1319 * @rmtoll CR2 ICRAMPDS LL_PWR_GetICacheRAMStopRetention
1320 * @retval Returned value can be one of the following values:
1321 * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION
1322 * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION
1323 */
LL_PWR_GetICacheRAMStopRetention(void)1324 __STATIC_INLINE uint32_t LL_PWR_GetICacheRAMStopRetention(void)
1325 {
1326 return ((~(READ_BIT(PWR->CR2, LL_PWR_ICACHERAM_STOP_FULL_RETENTION))) & LL_PWR_ICACHERAM_STOP_FULL_RETENTION);
1327 }
1328
1329 /**
1330 * @brief Set the DCACHE1 SRAM page retention in Stop mode.
1331 * @rmtoll CR2 DC1RAMPDS LL_PWR_SetDCache1RAMStopRetention\n
1332 * @param DCache1PageRetention : This parameter can be one of the following values:
1333 * @arg @ref LL_PWR_DCACHE1RAM_STOP_NO_RETENTION
1334 * @arg @ref LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION
1335 * @retval None
1336 */
LL_PWR_SetDCache1RAMStopRetention(uint32_t DCache1PageRetention)1337 __STATIC_INLINE void LL_PWR_SetDCache1RAMStopRetention(uint32_t DCache1PageRetention)
1338 {
1339 MODIFY_REG(PWR->CR2, LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION,
1340 ((~DCache1PageRetention) & LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION));
1341 }
1342
1343 /**
1344 * @brief Get the DCACHE1 SRAM page retention in Stop mode.
1345 * @rmtoll CR2 DC1RAMPDS LL_PWR_GetDCache1RAMStopRetention
1346 * @retval Returned value can be one of the following values:
1347 * @arg @ref LL_PWR_DCACHE1RAM_STOP_NO_RETENTION
1348 * @arg @ref LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION
1349 */
LL_PWR_GetDCache1RAMStopRetention(void)1350 __STATIC_INLINE uint32_t LL_PWR_GetDCache1RAMStopRetention(void)
1351 {
1352 return ((~(READ_BIT(PWR->CR2, LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION))) & LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION);
1353 }
1354
1355 #if defined (PWR_CR2_DC2RAMPDS)
1356 /**
1357 * @brief Set the DCACHE2 SRAM page retention in Stop mode.
1358 * @rmtoll CR2 DC2RAMPDS LL_PWR_SetDCache2RAMStopRetention\n
1359 * @param DCache2PageRetention : This parameter can be one of the following values:
1360 * @arg @ref LL_PWR_DCACHE2RAM_STOP_NO_RETENTION
1361 * @arg @ref LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION
1362 * @retval None
1363 */
LL_PWR_SetDCache2RAMStopRetention(uint32_t DCache2PageRetention)1364 __STATIC_INLINE void LL_PWR_SetDCache2RAMStopRetention(uint32_t DCache2PageRetention)
1365 {
1366 MODIFY_REG(PWR->CR2, LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION,
1367 ((~DCache2PageRetention) & LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION));
1368 }
1369
1370 /**
1371 * @brief Get the DCACHE2 SRAM page retention in Stop mode.
1372 * @rmtoll CR2 DC2RAMPDS LL_PWR_GetDCache2RAMStopRetention
1373 * @retval Returned value can be one of the following values:
1374 * @arg @ref LL_PWR_DCACHE2RAM_STOP_NO_RETENTION
1375 * @arg @ref LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION
1376 */
LL_PWR_GetDCache2RAMStopRetention(void)1377 __STATIC_INLINE uint32_t LL_PWR_GetDCache2RAMStopRetention(void)
1378 {
1379 return ((~(READ_BIT(PWR->CR2, LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION))) & LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION);
1380 }
1381 #endif /* defined (PWR_CR2_DC2RAMPDS) */
1382
1383 #if defined (PWR_CR2_DMA2DRAMPDS)
1384 /**
1385 * @brief Set the DMA2D SRAM page retention in Stop mode.
1386 * @rmtoll CR2 DMA2DRAMPDS LL_PWR_SetDMA2DRAMStopRetention\n
1387 * @param DMA2DRAMPageRetention : This parameter can be one of the following values:
1388 * @arg @ref LL_PWR_DMA2DRAM_STOP_NO_RETENTION
1389 * @arg @ref LL_PWR_DMA2DRAM_STOP_FULL_RETENTION
1390 * @retval None
1391 */
LL_PWR_SetDMA2DRAMStopRetention(uint32_t DMA2DRAMPageRetention)1392 __STATIC_INLINE void LL_PWR_SetDMA2DRAMStopRetention(uint32_t DMA2DRAMPageRetention)
1393 {
1394 MODIFY_REG(PWR->CR2, LL_PWR_DMA2DRAM_STOP_FULL_RETENTION,
1395 ((~DMA2DRAMPageRetention) & LL_PWR_DMA2DRAM_STOP_FULL_RETENTION));
1396 }
1397
1398 /**
1399 * @brief Get the DMA2D SRAM page retention in Stop mode.
1400 * @rmtoll CR2 DMA2DRAMPDS LL_PWR_GetDMA2DRAMStopRetention
1401 * @retval Returned value can be one of the following values:
1402 * @arg @ref LL_PWR_DMA2DRAM_STOP_NO_RETENTION
1403 * @arg @ref LL_PWR_DMA2DRAM_STOP_FULL_RETENTION
1404 */
LL_PWR_GetDMA2DRAMStopRetention(void)1405 __STATIC_INLINE uint32_t LL_PWR_GetDMA2DRAMStopRetention(void)
1406 {
1407 return ((~(READ_BIT(PWR->CR2, LL_PWR_DMA2DRAM_STOP_FULL_RETENTION))) & LL_PWR_DMA2DRAM_STOP_FULL_RETENTION);
1408 }
1409 #endif /* PWR_CR2_DMA2DRAMPDS */
1410
1411 /**
1412 * @brief Set the FMAC, FDCAN and USB SRAMs pages retention in Stop mode.
1413 * @rmtoll CR2 PRAMPDS LL_PWR_SetPeriphRAMStopRetention\n
1414 * @param PriphRAMPageRetention : This parameter can be one of the following values:
1415 * @arg @ref LL_PWR_PERIPHRAM_STOP_NO_RETENTION
1416 * @arg @ref LL_PWR_PERIPHRAM_STOP_FULL_RETENTION
1417 * @retval None
1418 */
LL_PWR_SetPeriphRAMStopRetention(uint32_t PriphRAMPageRetention)1419 __STATIC_INLINE void LL_PWR_SetPeriphRAMStopRetention(uint32_t PriphRAMPageRetention)
1420 {
1421 MODIFY_REG(PWR->CR2, LL_PWR_PERIPHRAM_STOP_FULL_RETENTION,
1422 ((~PriphRAMPageRetention) & LL_PWR_PERIPHRAM_STOP_FULL_RETENTION));
1423 }
1424
1425 /**
1426 * @brief Get the FMAC, FDCAN and USB SRAMs pages retention in Stop mode.
1427 * @rmtoll CR2 PRAMPDS LL_PWR_GetPeriphRAMStopRetention
1428 * @retval Returned value can be one of the following values:
1429 * @arg @ref LL_PWR_PERIPHRAM_STOP_NO_RETENTION
1430 * @arg @ref LL_PWR_PERIPHRAM_STOP_FULL_RETENTION
1431 */
LL_PWR_GetPeriphRAMStopRetention(void)1432 __STATIC_INLINE uint32_t LL_PWR_GetPeriphRAMStopRetention(void)
1433 {
1434 return ((~(READ_BIT(PWR->CR2, LL_PWR_PERIPHRAM_STOP_FULL_RETENTION))) & LL_PWR_PERIPHRAM_STOP_FULL_RETENTION);
1435 }
1436
1437 #if defined (PWR_CR2_PKARAMPDS)
1438 /**
1439 * @brief Set the PKA32 SRAM page retention in Stop mode.
1440 * @rmtoll CR2 PKARAMPDS LL_PWR_SetPKARAMStopRetention
1441 * @param PKARAMPageRetention : This parameter can be one of the following values:
1442 * @arg @ref LL_PWR_PKARAM_STOP_NO_RETENTION
1443 * @arg @ref LL_PWR_PKARAM_STOP_FULL_RETENTION
1444 * @retval None
1445 */
LL_PWR_SetPKARAMStopRetention(uint32_t PKARAMPageRetention)1446 __STATIC_INLINE void LL_PWR_SetPKARAMStopRetention(uint32_t PKARAMPageRetention)
1447 {
1448 MODIFY_REG(PWR->CR2, LL_PWR_PKARAM_STOP_FULL_RETENTION, ((~PKARAMPageRetention) & LL_PWR_PKARAM_STOP_FULL_RETENTION));
1449 }
1450
1451 /**
1452 * @brief Get the PKA32 SRAM page retention in Stop mode.
1453 * @rmtoll CR2 PKARAMPDS LL_PWR_GetPKARAMStopRetention
1454 * @retval Returned value can be one of the following values:
1455 * @arg @ref LL_PWR_PKARAM_STOP_NO_RETENTION
1456 * @arg @ref LL_PWR_PKARAM_STOP_FULL_RETENTION
1457 */
LL_PWR_GetPKARAMStopRetention(void)1458 __STATIC_INLINE uint32_t LL_PWR_GetPKARAMStopRetention(void)
1459 {
1460 return ((~(READ_BIT(PWR->CR2, LL_PWR_PKARAM_STOP_FULL_RETENTION))) & LL_PWR_PKARAM_STOP_FULL_RETENTION);
1461 }
1462 #endif /* defined (PWR_CR2_PKARAMPDS) */
1463
1464 #if defined (PWR_CR2_GPRAMPDS)
1465 /**
1466 * @brief Set the Graphic peripherals (LTDC, GFXMMU) SRAM page retention in Stop mode.
1467 * @rmtoll CR2 GPRAMPDS LL_PWR_SetGraphicPeriphRAMStopRetention
1468 * @param GraphicPeriphRAMPageRetention : This parameter can be one of the following values:
1469 * @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_NO_RETENTION
1470 * @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION
1471 * @retval None
1472 */
LL_PWR_SetGraphicPeriphRAMStopRetention(uint32_t GraphicPeriphRAMPageRetention)1473 __STATIC_INLINE void LL_PWR_SetGraphicPeriphRAMStopRetention(uint32_t GraphicPeriphRAMPageRetention)
1474 {
1475 MODIFY_REG(PWR->CR2, LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION,
1476 ((~GraphicPeriphRAMPageRetention) & LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION));
1477 }
1478
1479 /**
1480 * @brief Get the Graphic peripherals (LTDC, GFXMMU) SRAM page retention in Stop mode.
1481 * @rmtoll CR2 GPRAMPDS LL_PWR_GetGraphicPeriphRAMStopRetention
1482 * @retval Returned value can be one of the following values:
1483 * @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_NO_RETENTION
1484 * @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION
1485 */
LL_PWR_GetGraphicPeriphRAMStopRetention(void)1486 __STATIC_INLINE uint32_t LL_PWR_GetGraphicPeriphRAMStopRetention(void)
1487 {
1488 return ((~(READ_BIT(PWR->CR2, LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION))) &
1489 LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION);
1490 }
1491 #endif /* defined (PWR_CR2_GPRAMPDS) */
1492
1493 #if defined (PWR_CR2_DSIRAMPDS)
1494 /**
1495 * @brief Set the DSI SRAM page retention in Stop mode.
1496 * @rmtoll CR2 DSIRAMPDS LL_PWR_SetDSIRAMStopRetention
1497 * @param DSIRAMPageRetention : This parameter can be one of the following values:
1498 * @arg @ref LL_PWR_DSIRAM_STOP_NO_RETENTION
1499 * @arg @ref LL_PWR_DSIRAM_STOP_FULL_RETENTION
1500 * @retval None
1501 */
LL_PWR_SetDSIRAMStopRetention(uint32_t DSIRAMPageRetention)1502 __STATIC_INLINE void LL_PWR_SetDSIRAMStopRetention(uint32_t DSIRAMPageRetention)
1503 {
1504 MODIFY_REG(PWR->CR2, LL_PWR_DSIRAM_STOP_FULL_RETENTION, ((~DSIRAMPageRetention) & LL_PWR_DSIRAM_STOP_FULL_RETENTION));
1505 }
1506
1507 /**
1508 * @brief Get the DSI SRAM page retention in Stop mode.
1509 * @rmtoll CR2 DSIRAMPDS LL_PWR_GetDSIRAMStopRetention
1510 * @retval Returned value can be one of the following values:
1511 * @arg @ref LL_PWR_DSIRAM_STOP_NO_RETENTION
1512 * @arg @ref LL_PWR_DSIRAM_STOP_FULL_RETENTION
1513 */
LL_PWR_GetDSIRAMStopRetention(void)1514 __STATIC_INLINE uint32_t LL_PWR_GetDSIRAMStopRetention(void)
1515 {
1516 return ((~(READ_BIT(PWR->CR2, LL_PWR_DSIRAM_STOP_FULL_RETENTION))) & LL_PWR_DSIRAM_STOP_FULL_RETENTION);
1517 }
1518 #endif /* defined (PWR_CR2_DSIRAMPDS) */
1519
1520 #if defined (PWR_CR2_JPEGRAMPDS)
1521 /**
1522 * @brief Set the JPEG SRAM page retention in Stop mode.
1523 * @rmtoll CR2 JPEGRAMPDS LL_PWR_SetJPEGRAMStopRetention
1524 * @param JPEGRAMPageRetention : This parameter can be one of the following values:
1525 * @arg @ref LL_PWR_JPEGRAM_STOP_NO_RETENTION
1526 * @arg @ref LL_PWR_JPEGRAM_STOP_FULL_RETENTION
1527 * @retval None
1528 */
LL_PWR_SetJPEGRAMStopRetention(uint32_t JPEGRAMPageRetention)1529 __STATIC_INLINE void LL_PWR_SetJPEGRAMStopRetention(uint32_t JPEGRAMPageRetention)
1530 {
1531 MODIFY_REG(PWR->CR2, LL_PWR_JPEGRAM_STOP_FULL_RETENTION,
1532 ((~JPEGRAMPageRetention) & LL_PWR_JPEGRAM_STOP_FULL_RETENTION));
1533 }
1534
1535 /**
1536 * @brief Get the JPEG SRAM page retention in Stop mode.
1537 * @rmtoll CR2 JPEGRAMPDS LL_PWR_GetJPEGRAMStopRetention
1538 * @retval Returned value can be one of the following values:
1539 * @arg @ref LL_PWR_JPEGRAM_STOP_NO_RETENTION
1540 * @arg @ref LL_PWR_JPEGRAM_STOP_FULL_RETENTION
1541 */
LL_PWR_GetJPEGRAMStopRetention(void)1542 __STATIC_INLINE uint32_t LL_PWR_GetJPEGRAMStopRetention(void)
1543 {
1544 return ((~(READ_BIT(PWR->CR2, LL_PWR_JPEGRAM_STOP_FULL_RETENTION))) & LL_PWR_JPEGRAM_STOP_FULL_RETENTION);
1545 }
1546 #endif /* defined (PWR_CR2_JPEGRAMPDS) */
1547
1548 /**
1549 * @brief Enable the flash memory fast wakeup from Stop mode (Stop 0, 1).
1550 * @rmtoll CR2 FLASHFWU LL_PWR_EnableFlashFastWakeUp
1551 * @retval None
1552 */
LL_PWR_EnableFlashFastWakeUp(void)1553 __STATIC_INLINE void LL_PWR_EnableFlashFastWakeUp(void)
1554 {
1555 SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
1556 }
1557
1558 /**
1559 * @brief Disable the flash memory fast wakeup from Stop mode (Stop 0, 1).
1560 * @rmtoll CR2 FLASHFWU LL_PWR_DisableFlashFastWakeUp
1561 * @retval None
1562 */
LL_PWR_DisableFlashFastWakeUp(void)1563 __STATIC_INLINE void LL_PWR_DisableFlashFastWakeUp(void)
1564 {
1565 CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
1566 }
1567
1568 /**
1569 * @brief Check if the flash memory fast wakeup from Stop mode (Stop 0, 1)
1570 * is enabled.
1571 * @rmtoll CR2 FLASHFWU LL_PWR_IsEnabledFlashFastWakeUp
1572 * @retval State of bit (1 or 0).
1573 */
LL_PWR_IsEnabledFlashFastWakeUp(void)1574 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashFastWakeUp(void)
1575 {
1576 return ((READ_BIT(PWR->CR2, PWR_CR2_FLASHFWU) == (PWR_CR2_FLASHFWU)) ? 1UL : 0UL);
1577 }
1578
1579 /**
1580 * @brief Enable the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2).
1581 * @rmtoll CR2 SRAM4FWU LL_PWR_EnableSRAM4FastWakeUp
1582 * @retval None
1583 */
LL_PWR_EnableSRAM4FastWakeUp(void)1584 __STATIC_INLINE void LL_PWR_EnableSRAM4FastWakeUp(void)
1585 {
1586 SET_BIT(PWR->CR2, PWR_CR2_SRAM4FWU);
1587 }
1588
1589 /**
1590 * @brief Disable the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2).
1591 * @rmtoll CR2 SRAM4FWU LL_PWR_DisableSRAM4FastWakeUp
1592 * @retval None
1593 */
LL_PWR_DisableSRAM4FastWakeUp(void)1594 __STATIC_INLINE void LL_PWR_DisableSRAM4FastWakeUp(void)
1595 {
1596 CLEAR_BIT(PWR->CR2, PWR_CR2_SRAM4FWU);
1597 }
1598
1599 /**
1600 * @brief Check if the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2).
1601 * is enabled.
1602 * @rmtoll CR2 SRAM4FWU LL_PWR_IsEnabledSRAM4FastWakeUp
1603 * @retval State of bit (1 or 0).
1604 */
LL_PWR_IsEnabledSRAM4FastWakeUp(void)1605 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM4FastWakeUp(void)
1606 {
1607 return ((READ_BIT(PWR->CR2, PWR_CR2_SRAM4FWU) == (PWR_CR2_SRAM4FWU)) ? 1UL : 0UL);
1608 }
1609
1610 /**
1611 * @brief Set the smart run domain mode.
1612 * @rmtoll CR2 SRDRUN LL_PWR_SetSmartRunDomainMode
1613 * @param SRDMode : This parameter can be one of the following values:
1614 * @arg @ref LL_PWR_SRD_RUN_MODE
1615 * @arg @ref LL_PWR_SRD_STOP_MODE
1616 * @retval None
1617 */
LL_PWR_SetSmartRunDomainMode(uint32_t SRDMode)1618 __STATIC_INLINE void LL_PWR_SetSmartRunDomainMode(uint32_t SRDMode)
1619 {
1620 MODIFY_REG(PWR->CR2, PWR_CR2_SRDRUN, SRDMode);
1621 }
1622
1623 /**
1624 * @brief Get the smart run domain mode.
1625 * @rmtoll CR2 SRDRUN LL_PWR_GetSmartRunDomainMode
1626 * @retval Returned value can be one of the following values:
1627 * @arg @ref LL_PWR_SRD_RUN_MODE
1628 * @arg @ref LL_PWR_SRD_STOP_MODE
1629 */
LL_PWR_GetSmartRunDomainMode(void)1630 __STATIC_INLINE uint32_t LL_PWR_GetSmartRunDomainMode(void)
1631 {
1632 return (READ_BIT(PWR->CR2, PWR_CR2_SRDRUN));
1633 }
1634
1635 /**
1636 * @brief Set the VCore regulator supply.
1637 * @rmtoll CR3 REGSEL LL_PWR_SetRegulatorSupply
1638 * @param RegulatorSupply : This parameter can be one of the following values:
1639 * @arg @ref LL_PWR_LDO_SUPPLY
1640 * @arg @ref LL_PWR_SMPS_SUPPLY
1641 * @retval None
1642 */
LL_PWR_SetRegulatorSupply(uint32_t RegulatorSupply)1643 __STATIC_INLINE void LL_PWR_SetRegulatorSupply(uint32_t RegulatorSupply)
1644 {
1645 MODIFY_REG(PWR->CR3, PWR_CR3_REGSEL, RegulatorSupply);
1646 }
1647
1648 /**
1649 * @brief Get the VCore regulator supply.
1650 * @rmtoll CR3 REGSEL LL_PWR_GetRegulatorSupply
1651 * @retval Returned value can be one of the following values:
1652 * @arg @ref LL_PWR_LDO_SUPPLY
1653 * @arg @ref LL_PWR_SMPS_SUPPLY
1654 */
LL_PWR_GetRegulatorSupply(void)1655 __STATIC_INLINE uint32_t LL_PWR_GetRegulatorSupply(void)
1656 {
1657 return (READ_BIT(PWR->CR3, PWR_CR3_REGSEL));
1658 }
1659
1660 /**
1661 * @brief Enable the fast soft start for selected regulator.
1662 * @rmtoll CR3 FSTEN LL_PWR_EnableFastSoftStart
1663 * @retval None
1664 */
LL_PWR_EnableFastSoftStart(void)1665 __STATIC_INLINE void LL_PWR_EnableFastSoftStart(void)
1666 {
1667 SET_BIT(PWR->CR3, PWR_CR3_FSTEN);
1668 }
1669
1670 /**
1671 * @brief Disable the fast soft start for selected regulator.
1672 * @rmtoll CR3 FSTEN LL_PWR_DisableFastSoftStart
1673 * @retval None
1674 */
LL_PWR_DisableFastSoftStart(void)1675 __STATIC_INLINE void LL_PWR_DisableFastSoftStart(void)
1676 {
1677 CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN);
1678 }
1679
1680 /**
1681 * @brief Check if the fast soft start for selected regulator is enabled.
1682 * @rmtoll CR3 FSTEN LL_PWR_IsEnabledFastSoftStart
1683 * @retval State of bit (1 or 0).
1684 */
LL_PWR_IsEnabledFastSoftStart(void)1685 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFastSoftStart(void)
1686 {
1687 return ((READ_BIT(PWR->CR3, PWR_CR3_FSTEN) == (PWR_CR3_FSTEN)) ? 1UL : 0UL);
1688 }
1689
1690 /**
1691 * @brief Set the regulator supply output voltage.
1692 * @rmtoll VOSR VOS LL_PWR_SetRegulVoltageScaling
1693 * @param VoltageScaling This parameter can be one of the following values:
1694 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
1695 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
1696 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
1697 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4
1698 * @retval None
1699 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)1700 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
1701 {
1702 MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, VoltageScaling);
1703 }
1704
1705 /**
1706 * @brief Get the regulator supply output voltage.
1707 * @rmtoll VOSR VOS LL_PWR_GetRegulVoltageScaling
1708 * @retval Returned value can be one of the following values:
1709 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
1710 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
1711 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
1712 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4
1713 */
LL_PWR_GetRegulVoltageScaling(void)1714 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
1715 {
1716 return (uint32_t)(READ_BIT(PWR->VOSR, PWR_VOSR_VOS));
1717 }
1718
1719 /**
1720 * @brief Enable the EPOD (Embedded Power Distribution) booster.
1721 * @rmtoll VOSR BOOSTEN LL_PWR_EnableEPODBooster
1722 * @retval None
1723 */
LL_PWR_EnableEPODBooster(void)1724 __STATIC_INLINE void LL_PWR_EnableEPODBooster(void)
1725 {
1726 SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
1727 }
1728
1729 /**
1730 * @brief Disable the EPOD (Embedded Power Distribution) booster.
1731 * @rmtoll VOSR BOOSTEN LL_PWR_DisableEPODBooster
1732 * @retval None
1733 */
LL_PWR_DisableEPODBooster(void)1734 __STATIC_INLINE void LL_PWR_DisableEPODBooster(void)
1735 {
1736 CLEAR_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
1737 }
1738
1739 /**
1740 * @brief Check if the EPOD (Embedded Power Distribution) booster is enabled.
1741 * @rmtoll VOSR BOOSTEN LL_PWR_IsEnabledEPODBooster
1742 * @retval State of bit (1 or 0).
1743 */
LL_PWR_IsEnabledEPODBooster(void)1744 __STATIC_INLINE uint32_t LL_PWR_IsEnabledEPODBooster(void)
1745 {
1746 return ((READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == (PWR_VOSR_BOOSTEN)) ? 1UL : 0UL);
1747 }
1748
1749 #if defined (PWR_VOSR_USBPWREN)
1750 /**
1751 * @brief Enable the USB power supply.
1752 * @rmtoll VOSR USBPWREN LL_PWR_EnableUSBPowerSupply
1753 * @retval None
1754 */
LL_PWR_EnableUSBPowerSupply(void)1755 __STATIC_INLINE void LL_PWR_EnableUSBPowerSupply(void)
1756 {
1757 SET_BIT(PWR->VOSR, PWR_VOSR_USBPWREN);
1758 }
1759
1760 /**
1761 * @brief Disable the USB power supply.
1762 * @rmtoll VOSR USBPWREN LL_PWR_DisableUSBPowerSupply
1763 * @retval None
1764 */
LL_PWR_DisableUSBPowerSupply(void)1765 __STATIC_INLINE void LL_PWR_DisableUSBPowerSupply(void)
1766 {
1767 CLEAR_BIT(PWR->VOSR, PWR_VOSR_USBPWREN);
1768 }
1769
1770 /**
1771 * @brief Check if the USB power supply is enabled.
1772 * @rmtoll VOSR USBPWREN LL_PWR_IsEnabledUSBPowerSupply
1773 * @retval State of bit (1 or 0).
1774 */
LL_PWR_IsEnabledUSBPowerSupply(void)1775 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBPowerSupply(void)
1776 {
1777 return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBPWREN) == (PWR_VOSR_USBPWREN)) ? 1UL : 0UL);
1778 }
1779 #endif /* defined (PWR_VOSR_USBPWREN) */
1780
1781 #if defined (PWR_VOSR_USBBOOSTEN)
1782 /**
1783 * @brief Enable the USB EPOD (Embedded Power Distribution) booster.
1784 * @rmtoll VOSR USBBOOSTEN LL_PWR_EnableUSBEPODBooster
1785 * @retval None
1786 */
LL_PWR_EnableUSBEPODBooster(void)1787 __STATIC_INLINE void LL_PWR_EnableUSBEPODBooster(void)
1788 {
1789 SET_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN);
1790 }
1791
1792 /**
1793 * @brief Disable the USB EPOD (Embedded Power Distribution) booster.
1794 * @rmtoll VOSR USBBOOSTEN LL_PWR_DisableUSBEPODBooster
1795 * @retval None
1796 */
LL_PWR_DisableUSBEPODBooster(void)1797 __STATIC_INLINE void LL_PWR_DisableUSBEPODBooster(void)
1798 {
1799 CLEAR_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN);
1800 }
1801
1802 /**
1803 * @brief Check if the USB EPOD (Embedded Power Distribution) booster is enabled.
1804 * @rmtoll VOSR USBBOOSTEN LL_PWR_IsEnabledUSBEPODBooster
1805 * @retval State of bit (1 or 0).
1806 */
LL_PWR_IsEnabledUSBEPODBooster(void)1807 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBEPODBooster(void)
1808 {
1809 return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN) == (PWR_VOSR_USBBOOSTEN)) ? 1UL : 0UL);
1810 }
1811 #endif /* defined (PWR_VOSR_USBBOOSTEN) */
1812
1813 #if defined (PWR_VOSR_VDD11USBDIS)
1814 /**
1815 * @brief Enable the VDD11USB.
1816 * @rmtoll VOSR VDD11USBDIS LL_PWR_EnableVDD11USB
1817 * @retval None
1818 */
LL_PWR_EnableVDD11USB(void)1819 __STATIC_INLINE void LL_PWR_EnableVDD11USB(void)
1820 {
1821 CLEAR_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS);
1822 }
1823
1824 /**
1825 * @brief Disable the VDD11USB.
1826 * @rmtoll VOSR VDD11USBDIS LL_PWR_DisableVDD11USB
1827 * @retval None
1828 */
LL_PWR_DisableVDD11USB(void)1829 __STATIC_INLINE void LL_PWR_DisableVDD11USB(void)
1830 {
1831 SET_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS);
1832 }
1833
1834 /**
1835 * @brief Check if the VDD11USB is enabled.
1836 * @rmtoll VOSR VDD11USBDIS LL_PWR_IsEnabledVDD11USB
1837 * @retval State of bit (1 or 0).
1838 */
LL_PWR_IsEnabledVDD11USB(void)1839 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVDD11USB(void)
1840 {
1841 return ((READ_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS) == (0U)) ? 1UL : 0UL);
1842 }
1843 #endif /* defined (PWR_VOSR_VDD11USBDIS) */
1844
1845 /**
1846 * @brief Set the Power voltage detector level.
1847 * @rmtoll SVMCR PVDLS LL_PWR_SetPVDLevel
1848 * @param PVDLevel This parameter can be one of the following values:
1849 * @arg @ref LL_PWR_PVDLEVEL_0
1850 * @arg @ref LL_PWR_PVDLEVEL_1
1851 * @arg @ref LL_PWR_PVDLEVEL_2
1852 * @arg @ref LL_PWR_PVDLEVEL_3
1853 * @arg @ref LL_PWR_PVDLEVEL_4
1854 * @arg @ref LL_PWR_PVDLEVEL_5
1855 * @arg @ref LL_PWR_PVDLEVEL_6
1856 * @arg @ref LL_PWR_PVDLEVEL_7
1857 * @retval None
1858 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)1859 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
1860 {
1861 MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, PVDLevel);
1862 }
1863
1864 /**
1865 * @brief Get the Power voltage detector level.
1866 * @rmtoll SVMCR PVDLS LL_PWR_GetPVDLevel
1867 * @retval Returned value can be one of the following values:
1868 * @arg @ref LL_PWR_PVDLEVEL_0
1869 * @arg @ref LL_PWR_PVDLEVEL_1
1870 * @arg @ref LL_PWR_PVDLEVEL_2
1871 * @arg @ref LL_PWR_PVDLEVEL_3
1872 * @arg @ref LL_PWR_PVDLEVEL_4
1873 * @arg @ref LL_PWR_PVDLEVEL_5
1874 * @arg @ref LL_PWR_PVDLEVEL_6
1875 * @arg @ref LL_PWR_PVDLEVEL_7
1876 */
LL_PWR_GetPVDLevel(void)1877 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
1878 {
1879 return (READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDLS));
1880 }
1881
1882 /**
1883 * @brief Enable the power voltage detector.
1884 * @rmtoll SVMCR PVDE LL_PWR_EnablePVD
1885 * @retval None
1886 */
LL_PWR_EnablePVD(void)1887 __STATIC_INLINE void LL_PWR_EnablePVD(void)
1888 {
1889 SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
1890 }
1891
1892 /**
1893 * @brief Disable the power voltage detector.
1894 * @rmtoll SVMCR PVDE LL_PWR_DisablePVD
1895 * @retval None
1896 */
LL_PWR_DisablePVD(void)1897 __STATIC_INLINE void LL_PWR_DisablePVD(void)
1898 {
1899 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
1900 }
1901
1902 /**
1903 * @brief Check if the power voltage detector is enabled.
1904 * @rmtoll SVMCR PVDE LL_PWR_IsEnabledPVD
1905 * @retval State of bit (1 or 0).
1906 */
LL_PWR_IsEnabledPVD(void)1907 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
1908 {
1909 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDE) == (PWR_SVMCR_PVDE)) ? 1UL : 0UL);
1910 }
1911
1912 /**
1913 * @brief Enable the independent USB supply.
1914 * @rmtoll SVMCR USV LL_PWR_EnableVddUSB
1915 * @retval None
1916 */
LL_PWR_EnableVddUSB(void)1917 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
1918 {
1919 SET_BIT(PWR->SVMCR, PWR_SVMCR_USV);
1920 }
1921 /* alias */
1922 #define LL_PWR_EnableVDDUSB LL_PWR_EnableVddUSB
1923 /**
1924 * @brief Disable the independent USB supply.
1925 * @rmtoll SVMCR USV LL_PWR_DisableVDDUSB
1926 * @retval None
1927 */
LL_PWR_DisableVddUSB(void)1928 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
1929 {
1930 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV);
1931 }
1932 /* alias */
1933 #define LL_PWR_DisableVDDUSB LL_PWR_DisableVddUSB
1934 /**
1935 * @brief Check if the independent USB supply is enabled.
1936 * @rmtoll SVMCR USV LL_PWR_IsEnabledVddUSB
1937 * @retval State of bit (1 or 0).
1938 */
LL_PWR_IsEnabledVddUSB(void)1939 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
1940 {
1941 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_USV) == (PWR_SVMCR_USV)) ? 1UL : 0UL);
1942 }
1943 /* alias */
1944 #define LL_PWR_IsEnabledVDDUSB LL_PWR_IsEnabledVddUSB
1945 /**
1946 * @brief Enable the independent I/Os supply.
1947 * @rmtoll SVMCR IO2SV LL_PWR_EnableVddIO2
1948 * @retval None
1949 */
LL_PWR_EnableVddIO2(void)1950 __STATIC_INLINE void LL_PWR_EnableVddIO2(void)
1951 {
1952 SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
1953 }
1954 /* alias */
1955 #define LL_PWR_EnableVDDIO2 LL_PWR_EnableVddIO2
1956 /**
1957 * @brief Disable the independent I/Os supply.
1958 * @rmtoll SVMCR IO2SV LL_PWR_DisableVddIO2
1959 * @retval None
1960 */
LL_PWR_DisableVddIO2(void)1961 __STATIC_INLINE void LL_PWR_DisableVddIO2(void)
1962 {
1963 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
1964 }
1965 /* alias */
1966 #define LL_PWR_DisableVDDIO2 LL_PWR_DisableVddIO2
1967 /**
1968 * @brief Check if the independent I/Os supply is enabled.
1969 * @rmtoll SVMCR IO2SV LL_PWR_IsEnabledVddIO2
1970 * @retval State of bit (1 or 0).
1971 */
LL_PWR_IsEnabledVddIO2(void)1972 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
1973 {
1974 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV) == (PWR_SVMCR_IO2SV)) ? 1UL : 0UL);
1975 }
1976 /* alias */
1977 #define LL_PWR_IsEnabledVDDIO2 LL_PWR_IsEnabledVddIO2
1978 /**
1979 * @brief Enable the independent analog supply.
1980 * @rmtoll SVMCR ASV LL_PWR_EnableVddA
1981 * @retval None
1982 */
LL_PWR_EnableVddA(void)1983 __STATIC_INLINE void LL_PWR_EnableVddA(void)
1984 {
1985 SET_BIT(PWR->SVMCR, PWR_SVMCR_ASV);
1986 }
1987 /* alias */
1988 #define LL_PWR_EnableVDDA LL_PWR_EnableVddA
1989 /**
1990 * @brief Disable the independent analog supply.
1991 * @rmtoll SVMCR ASV LL_PWR_DisableVddA
1992 * @retval None
1993 */
LL_PWR_DisableVddA(void)1994 __STATIC_INLINE void LL_PWR_DisableVddA(void)
1995 {
1996 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_ASV);
1997 }
1998 /* alias */
1999 #define LL_PWR_DisableVDDA LL_PWR_DisableVddA
2000 /**
2001 * @brief Check if the independent analog supply is enabled.
2002 * @rmtoll SVMCR ASV LL_PWR_IsEnabledVddA
2003 * @retval State of bit (1 or 0).
2004 */
LL_PWR_IsEnabledVddA(void)2005 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddA(void)
2006 {
2007 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_ASV) == (PWR_SVMCR_ASV)) ? 1UL : 0UL);
2008 }
2009 /* alias */
2010 #define LL_PWR_IsEnabledVDDA LL_PWR_IsEnabledVddA
2011 /**
2012 * @brief Enable the independent USB supply monitor.
2013 * @rmtoll SVMCR UVMEN LL_PWR_EnableVddUSBMonitor
2014 * @retval None
2015 */
LL_PWR_EnableVddUSBMonitor(void)2016 __STATIC_INLINE void LL_PWR_EnableVddUSBMonitor(void)
2017 {
2018 SET_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN);
2019 }
2020 /* alias */
2021 #define LL_PWR_EnableVDDUSBMonitor LL_PWR_EnableVddUSBMonitor
2022 /**
2023 * @brief Disable the independent USB supply monitor.
2024 * @rmtoll SVMCR UVMEN LL_PWR_DisableVddUSBMonitor
2025 * @retval None
2026 */
LL_PWR_DisableVddUSBMonitor(void)2027 __STATIC_INLINE void LL_PWR_DisableVddUSBMonitor(void)
2028 {
2029 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN);
2030 }
2031 /* alias */
2032 #define LL_PWR_DisableVDDUSBMonitor LL_PWR_DisableVddUSBMonitor
2033 /**
2034 * @brief Check if the independent USB supply monitor is enabled.
2035 * @rmtoll SVMCR UVMEN LL_PWR_IsEnabledVddUSBMonitor
2036 * @retval State of bit (1 or 0).
2037 */
LL_PWR_IsEnabledVddUSBMonitor(void)2038 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSBMonitor(void)
2039 {
2040 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN) == (PWR_SVMCR_UVMEN)) ? 1UL : 0UL);
2041 }
2042 /* alias */
2043 #define LL_PWR_IsEnabledVDDUSBMonitor LL_PWR_IsEnabledVddUSBMonitor
2044 /**
2045 * @brief Enable the independent I/Os supply monitor.
2046 * @rmtoll SVMCR IO2VMEN LL_PWR_EnableVddIO2Monitor
2047 * @retval None
2048 */
LL_PWR_EnableVddIO2Monitor(void)2049 __STATIC_INLINE void LL_PWR_EnableVddIO2Monitor(void)
2050 {
2051 SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN);
2052 }
2053 /* alias */
2054 #define LL_PWR_EnableVDDIO2Monitor LL_PWR_EnableVddIO2Monitor
2055 /**
2056 * @brief Disable the independent I/Os supply monitor.
2057 * @rmtoll SVMCR IO2VMEN LL_PWR_DisableVddIO2Monitor
2058 * @retval None
2059 */
LL_PWR_DisableVddIO2Monitor(void)2060 __STATIC_INLINE void LL_PWR_DisableVddIO2Monitor(void)
2061 {
2062 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN);
2063 }
2064 /* alias */
2065 #define LL_PWR_DisableVDDIO2Monitor LL_PWR_DisableVddIO2Monitor
2066 /**
2067 * @brief Check if the independent I/Os supply monitor is enabled.
2068 * @rmtoll SVMCR IO2VMEN LL_PWR_IsEnabledVddIO2Monitor
2069 * @retval State of bit (1 or 0).
2070 */
LL_PWR_IsEnabledVddIO2Monitor(void)2071 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2Monitor(void)
2072 {
2073 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN) == (PWR_SVMCR_IO2VMEN)) ? 1UL : 0UL);
2074 }
2075 /* alias */
2076 #define LL_PWR_IsEnabledVDDIO2Monitor LL_PWR_IsEnabledVddIO2Monitor
2077 /**
2078 * @brief Enable the independent analog supply monitor 1.
2079 * @rmtoll SVMCR AVM1EN LL_PWR_EnableVddAMonitor1
2080 * @retval None
2081 */
LL_PWR_EnableVddAMonitor1(void)2082 __STATIC_INLINE void LL_PWR_EnableVddAMonitor1(void)
2083 {
2084 SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN);
2085 }
2086 /* alias */
2087 #define LL_PWR_EnableVDDAMonitor1 LL_PWR_EnableVddAMonitor1
2088 /**
2089 * @brief Disable the independent analog supply monitor 1.
2090 * @rmtoll SVMCR AVM1EN LL_PWR_DisableVddAMonitor1
2091 * @retval None
2092 */
LL_PWR_DisableVddAMonitor1(void)2093 __STATIC_INLINE void LL_PWR_DisableVddAMonitor1(void)
2094 {
2095 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN);
2096 }
2097 /* alias */
2098 #define LL_PWR_DisableVDDAMonitor1 LL_PWR_DisableVddAMonitor1
2099 /**
2100 * @brief Check if the independent analog supply monitor 1 is enabled.
2101 * @rmtoll SVMCR AVM1EN LL_PWR_IsEnabledVddAMonitor1
2102 * @retval State of bit (1 or 0).
2103 */
LL_PWR_IsEnabledVddAMonitor1(void)2104 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddAMonitor1(void)
2105 {
2106 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN) == (PWR_SVMCR_AVM1EN)) ? 1UL : 0UL);
2107 }
2108 /* alias */
2109 #define LL_PWR_IsEnabledVDDAMonitor1 LL_PWR_IsEnabledVddAMonitor1
2110 /**
2111 * @brief Enable the independent analog supply monitor 2.
2112 * @rmtoll SVMCR AVM2EN LL_PWR_EnableVddAMonitor2
2113 * @retval None
2114 */
LL_PWR_EnableVddAMonitor2(void)2115 __STATIC_INLINE void LL_PWR_EnableVddAMonitor2(void)
2116 {
2117 SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN);
2118 }
2119 /* alias */
2120 #define LL_PWR_EnableVDDAMonitor2 LL_PWR_EnableVddAMonitor2
2121 /**
2122 * @brief Disable the independent analog supply monitor 2.
2123 * @rmtoll SVMCR AVM2EN LL_PWR_DisableVddAMonitor2
2124 * @retval None
2125 */
LL_PWR_DisableVddAMonitor2(void)2126 __STATIC_INLINE void LL_PWR_DisableVddAMonitor2(void)
2127 {
2128 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN);
2129 }
2130 /* alias */
2131 #define LL_PWR_DisableVDDAMonitor2 LL_PWR_DisableVddAMonitor2
2132 /**
2133 * @brief Check if the independent analog supply monitor 2 is enabled.
2134 * @rmtoll SVMCR AVM2EN LL_PWR_IsEnabledVddAMonitor2
2135 * @retval State of bit (1 or 0).
2136 */
LL_PWR_IsEnabledVddAMonitor2(void)2137 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddAMonitor2(void)
2138 {
2139 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN) == (PWR_SVMCR_AVM2EN)) ? 1UL : 0UL);
2140 }
2141 /* alias */
2142 #define LL_PWR_IsEnabledVDDAMonitor2 LL_PWR_IsEnabledVddAMonitor2
2143 /**
2144 * @brief Enable the wake up pin_x.
2145 * @rmtoll WUCR1 WUPENx LL_PWR_EnableWakeUpPin
2146 * @param WakeUpPin This parameter can be a combination of the following values:
2147 * @arg @ref LL_PWR_WAKEUP_PIN1
2148 * @arg @ref LL_PWR_WAKEUP_PIN2
2149 * @arg @ref LL_PWR_WAKEUP_PIN3
2150 * @arg @ref LL_PWR_WAKEUP_PIN4
2151 * @arg @ref LL_PWR_WAKEUP_PIN5
2152 * @arg @ref LL_PWR_WAKEUP_PIN6
2153 * @arg @ref LL_PWR_WAKEUP_PIN7
2154 * @arg @ref LL_PWR_WAKEUP_PIN8
2155 * @retval None
2156 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)2157 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
2158 {
2159 SET_BIT(PWR->WUCR1, WakeUpPin);
2160 }
2161
2162 /**
2163 * @brief Disable the wake up pin_x.
2164 * @rmtoll WUCR1 WUPENx LL_PWR_DisableWakeUpPin
2165 * @param WakeUpPin This parameter can be a combination of the following values:
2166 * @arg @ref LL_PWR_WAKEUP_PIN1
2167 * @arg @ref LL_PWR_WAKEUP_PIN2
2168 * @arg @ref LL_PWR_WAKEUP_PIN3
2169 * @arg @ref LL_PWR_WAKEUP_PIN4
2170 * @arg @ref LL_PWR_WAKEUP_PIN5
2171 * @arg @ref LL_PWR_WAKEUP_PIN6
2172 * @arg @ref LL_PWR_WAKEUP_PIN7
2173 * @arg @ref LL_PWR_WAKEUP_PIN8
2174 * @retval None
2175 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)2176 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
2177 {
2178 CLEAR_BIT(PWR->WUCR1, WakeUpPin);
2179 }
2180
2181 /**
2182 * @brief Check if the wake up pin_x is enabled.
2183 * @rmtoll WUCR1 WUPENx LL_PWR_IsEnabledWakeUpPin
2184 * @param WakeUpPin This parameter can be one of the following values:
2185 * @arg @ref LL_PWR_WAKEUP_PIN1
2186 * @arg @ref LL_PWR_WAKEUP_PIN2
2187 * @arg @ref LL_PWR_WAKEUP_PIN3
2188 * @arg @ref LL_PWR_WAKEUP_PIN4
2189 * @arg @ref LL_PWR_WAKEUP_PIN5
2190 * @arg @ref LL_PWR_WAKEUP_PIN6
2191 * @arg @ref LL_PWR_WAKEUP_PIN7
2192 * @arg @ref LL_PWR_WAKEUP_PIN8
2193 * @retval State of bit (1 or 0).
2194 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)2195 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
2196 {
2197 return ((READ_BIT(PWR->WUCR1, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
2198 }
2199
2200 /**
2201 * @brief Set the wake up pin polarity low for the event detection.
2202 * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityLow
2203 * @param WakeUpPin This parameter can be a combination of the following values:
2204 * @arg @ref LL_PWR_WAKEUP_PIN1
2205 * @arg @ref LL_PWR_WAKEUP_PIN2
2206 * @arg @ref LL_PWR_WAKEUP_PIN3
2207 * @arg @ref LL_PWR_WAKEUP_PIN4
2208 * @arg @ref LL_PWR_WAKEUP_PIN5
2209 * @arg @ref LL_PWR_WAKEUP_PIN6
2210 * @arg @ref LL_PWR_WAKEUP_PIN7
2211 * @arg @ref LL_PWR_WAKEUP_PIN8
2212 * @retval None
2213 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)2214 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
2215 {
2216 SET_BIT(PWR->WUCR2, WakeUpPin);
2217 }
2218
2219 /**
2220 * @brief Set the wake up pin polarity high for the event detection.
2221 * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityHigh
2222 * @param WakeUpPin This parameter can be a combination of the following values:
2223 * @arg @ref LL_PWR_WAKEUP_PIN1
2224 * @arg @ref LL_PWR_WAKEUP_PIN2
2225 * @arg @ref LL_PWR_WAKEUP_PIN3
2226 * @arg @ref LL_PWR_WAKEUP_PIN4
2227 * @arg @ref LL_PWR_WAKEUP_PIN5
2228 * @arg @ref LL_PWR_WAKEUP_PIN6
2229 * @arg @ref LL_PWR_WAKEUP_PIN7
2230 * @arg @ref LL_PWR_WAKEUP_PIN8
2231 * @retval None
2232 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)2233 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
2234 {
2235 CLEAR_BIT(PWR->WUCR2, WakeUpPin);
2236 }
2237
2238 /**
2239 * @brief Get the wake up pin polarity for the event detection.
2240 * @rmtoll WUCR2 WUPPx LL_PWR_GetWakeUpPinPolarity
2241 * @param WakeUpPin This parameter can be one of the following values:
2242 * @arg @ref LL_PWR_WAKEUP_PIN1
2243 * @arg @ref LL_PWR_WAKEUP_PIN2
2244 * @arg @ref LL_PWR_WAKEUP_PIN3
2245 * @arg @ref LL_PWR_WAKEUP_PIN4
2246 * @arg @ref LL_PWR_WAKEUP_PIN5
2247 * @arg @ref LL_PWR_WAKEUP_PIN6
2248 * @arg @ref LL_PWR_WAKEUP_PIN7
2249 * @arg @ref LL_PWR_WAKEUP_PIN8
2250 * @retval State of bit (1 : polarity or 0 : polarity high).
2251 */
LL_PWR_GetWakeUpPinPolarity(uint32_t WakeUpPin)2252 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPolarity(uint32_t WakeUpPin)
2253 {
2254 return ((READ_BIT(PWR->WUCR2, WakeUpPin) == WakeUpPin) ? 1UL : 0UL);
2255 }
2256
2257 /**
2258 * @brief Set the wakeup pin_x selection 0.
2259 * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal0Selection
2260 * @param WakeUpPin This parameter can be one of the following values:
2261 * @arg @ref LL_PWR_WAKEUP_PIN1
2262 * @arg @ref LL_PWR_WAKEUP_PIN2
2263 * @arg @ref LL_PWR_WAKEUP_PIN3
2264 * @arg @ref LL_PWR_WAKEUP_PIN4
2265 * @arg @ref LL_PWR_WAKEUP_PIN5
2266 * @arg @ref LL_PWR_WAKEUP_PIN6
2267 * @arg @ref LL_PWR_WAKEUP_PIN7
2268 * @arg @ref LL_PWR_WAKEUP_PIN8
2269 * @retval None
2270 */
LL_PWR_SetWakeUpPinSignal0Selection(uint32_t WakeUpPin)2271 __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal0Selection(uint32_t WakeUpPin)
2272 {
2273 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
2274 (LL_PWR_WAKEUP_PIN_SELECTION_0 << (POSITION_VAL(WakeUpPin) * 2U)));
2275 }
2276
2277 /**
2278 * @brief Set the wakeup pin_x selection 1.
2279 * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal1Selection
2280 * @param WakeUpPin This parameter can be one of the following values:
2281 * @arg @ref LL_PWR_WAKEUP_PIN1
2282 * @arg @ref LL_PWR_WAKEUP_PIN2
2283 * @arg @ref LL_PWR_WAKEUP_PIN3
2284 * @arg @ref LL_PWR_WAKEUP_PIN4
2285 * @arg @ref LL_PWR_WAKEUP_PIN5
2286 * @arg @ref LL_PWR_WAKEUP_PIN6
2287 * @arg @ref LL_PWR_WAKEUP_PIN7
2288 * @arg @ref LL_PWR_WAKEUP_PIN8
2289 * @retval None
2290 */
LL_PWR_SetWakeUpPinSignal1Selection(uint32_t WakeUpPin)2291 __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal1Selection(uint32_t WakeUpPin)
2292 {
2293 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
2294 (LL_PWR_WAKEUP_PIN_SELECTION_1 << (POSITION_VAL(WakeUpPin) * 2U)));
2295 }
2296
2297 /**
2298 * @brief Set the wakeup pin_x selection 2.
2299 * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal2Selection
2300 * @param WakeUpPin This parameter can be one of the following values:
2301 * @arg @ref LL_PWR_WAKEUP_PIN1
2302 * @arg @ref LL_PWR_WAKEUP_PIN2
2303 * @arg @ref LL_PWR_WAKEUP_PIN3
2304 * @arg @ref LL_PWR_WAKEUP_PIN4
2305 * @arg @ref LL_PWR_WAKEUP_PIN5
2306 * @arg @ref LL_PWR_WAKEUP_PIN6
2307 * @arg @ref LL_PWR_WAKEUP_PIN7
2308 * @arg @ref LL_PWR_WAKEUP_PIN8
2309 * @retval None
2310 */
LL_PWR_SetWakeUpPinSignal2Selection(uint32_t WakeUpPin)2311 __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal2Selection(uint32_t WakeUpPin)
2312 {
2313 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
2314 (LL_PWR_WAKEUP_PIN_SELECTION_2 << (POSITION_VAL(WakeUpPin) * 2U)));
2315 }
2316
2317 /**
2318 * @brief Set the wakeup pin_x selection 3.
2319 * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal3Selection
2320 * @param WakeUpPin This parameter can be one of the following values:
2321 * @arg @ref LL_PWR_WAKEUP_PIN1
2322 * @arg @ref LL_PWR_WAKEUP_PIN2
2323 * @arg @ref LL_PWR_WAKEUP_PIN3
2324 * @arg @ref LL_PWR_WAKEUP_PIN4
2325 * @arg @ref LL_PWR_WAKEUP_PIN5
2326 * @arg @ref LL_PWR_WAKEUP_PIN6
2327 * @arg @ref LL_PWR_WAKEUP_PIN7
2328 * @arg @ref LL_PWR_WAKEUP_PIN8
2329 * @retval None
2330 */
LL_PWR_SetWakeUpPinSignal3Selection(uint32_t WakeUpPin)2331 __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal3Selection(uint32_t WakeUpPin)
2332 {
2333 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
2334 (LL_PWR_WAKEUP_PIN_SELECTION_3 << (POSITION_VAL(WakeUpPin) * 2U)));
2335 }
2336
2337 /**
2338 * @brief Get the wakeup pin_x selection.
2339 * @rmtoll WUCR3 WUSELx LL_PWR_GetWakeUpPinSignalSelection
2340 * @param WakeUpPin This parameter can be one of the following values:
2341 * @arg @ref LL_PWR_WAKEUP_PIN1
2342 * @arg @ref LL_PWR_WAKEUP_PIN2
2343 * @arg @ref LL_PWR_WAKEUP_PIN3
2344 * @arg @ref LL_PWR_WAKEUP_PIN4
2345 * @arg @ref LL_PWR_WAKEUP_PIN5
2346 * @arg @ref LL_PWR_WAKEUP_PIN6
2347 * @arg @ref LL_PWR_WAKEUP_PIN7
2348 * @arg @ref LL_PWR_WAKEUP_PIN8
2349 */
LL_PWR_GetWakeUpPinSignalSelection(uint32_t WakeUpPin)2350 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinSignalSelection(uint32_t WakeUpPin)
2351 {
2352 return (READ_BIT(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U))));
2353 }
2354
2355 /**
2356 * @brief Enable backup regulator.
2357 * @rmtoll BDCR1 BREN LL_PWR_EnableBkUpRegulator
2358 * @note When this bit is set, the backup RAM content is kept in Standby and
2359 * VBAT modes. If BREN is reset, the backup RAM can still be used in
2360 * Run, Sleep and Stop modes. However, its content is lost in Standby,
2361 * Shutdown and VBAT modes. This bit can be written only when the
2362 * regulator is LDO, which must be configured before switching to SMPS.
2363 * @retval None
2364 */
LL_PWR_EnableBkUpRegulator(void)2365 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
2366 {
2367 SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN);
2368 }
2369
2370 /**
2371 * @brief Disable backup regulator
2372 * @rmtoll BDCR1 BREN LL_PWR_DisableBkUpRegulator
2373 * @retval None
2374 */
LL_PWR_DisableBkUpRegulator(void)2375 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
2376 {
2377 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN);
2378 }
2379
2380 /**
2381 * @brief Check if the backup regulator is enabled
2382 * @rmtoll BDCR1 BREN LL_PWR_IsEnabledBkUpRegulator
2383 * @retval State of bit (1 or 0).
2384 */
LL_PWR_IsEnabledBkUpRegulator(void)2385 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
2386 {
2387 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_BREN) == (PWR_BDCR1_BREN)) ? 1UL : 0UL);
2388 }
2389
2390 /**
2391 * @brief Enable the backup domain voltage and temperature monitoring.
2392 * @rmtoll BDCR1 MONEN LL_PWR_EnableMonitoring
2393 * @retval None
2394 */
LL_PWR_EnableMonitoring(void)2395 __STATIC_INLINE void LL_PWR_EnableMonitoring(void)
2396 {
2397 SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
2398 }
2399
2400 /**
2401 * @brief Disable the backup domain voltage and temperature monitoring.
2402 * @rmtoll BDCR1 MONEN LL_PWR_DisableMonitoring
2403 * @retval None
2404 */
LL_PWR_DisableMonitoring(void)2405 __STATIC_INLINE void LL_PWR_DisableMonitoring(void)
2406 {
2407 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
2408 }
2409
2410 /**
2411 * @brief Check if the backup domain voltage and temperature monitoring is
2412 * enabled.
2413 * @rmtoll BDCR1 MONEN LL_PWR_IsEnabledMonitoring
2414 * @retval State of bit (1 or 0).
2415 */
LL_PWR_IsEnabledMonitoring(void)2416 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
2417 {
2418 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_MONEN) == (PWR_BDCR1_MONEN)) ? 1UL : 0UL);
2419 }
2420
2421 /**
2422 * @brief Enable battery charging.
2423 * @rmtoll BDCR2 VBE LL_PWR_EnableBatteryCharging
2424 * @retval None
2425 */
LL_PWR_EnableBatteryCharging(void)2426 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
2427 {
2428 SET_BIT(PWR->BDCR2, PWR_BDCR2_VBE);
2429 }
2430
2431 /**
2432 * @brief Disable battery charging.
2433 * @rmtoll BDCR2 VBE LL_PWR_DisableBatteryCharging
2434 * @retval None
2435 */
LL_PWR_DisableBatteryCharging(void)2436 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
2437 {
2438 CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_VBE);
2439 }
2440
2441 /**
2442 * @brief Check if battery charging is enabled.
2443 * @rmtoll BDCR2 VBE LL_PWR_IsEnabledBatteryCharging
2444 * @retval State of bit (1 or 0).
2445 */
LL_PWR_IsEnabledBatteryCharging(void)2446 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
2447 {
2448 return ((READ_BIT(PWR->BDCR2, PWR_BDCR2_VBE) == (PWR_BDCR2_VBE)) ? 1UL : 0UL);
2449 }
2450
2451 /**
2452 * @brief Set the Battery charge resistor impedance
2453 * @rmtoll BDCR2 VBRS LL_PWR_SetBattChargResistor
2454 * @param Resistor This parameter can be one of the following values:
2455 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
2456 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K
2457 * @retval None
2458 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)2459 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
2460 {
2461 MODIFY_REG(PWR->BDCR2, PWR_BDCR2_VBRS, Resistor);
2462 }
2463
2464 /**
2465 * @brief Get the Battery charge resistor impedance
2466 * @rmtoll BDCR2 VBRS LL_PWR_GetBattChargResistor
2467 * @retval Returned value can be one of the following values:
2468 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
2469 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K
2470 */
LL_PWR_GetBattChargResistor(void)2471 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
2472 {
2473 return (uint32_t)(READ_BIT(PWR->BDCR2, PWR_BDCR2_VBRS));
2474 }
2475
2476 /**
2477 * @brief Enable access to the backup domain.
2478 * @rmtoll DBPR DBP LL_PWR_EnableBkUpAccess
2479 * @retval None
2480 */
LL_PWR_EnableBkUpAccess(void)2481 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
2482 {
2483 SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
2484 }
2485
2486 /**
2487 * @brief Disable access to the backup domain.
2488 * @rmtoll DBPR DBP LL_PWR_DisableBkUpAccess
2489 * @retval None
2490 */
LL_PWR_DisableBkUpAccess(void)2491 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
2492 {
2493 CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP);
2494 }
2495
2496 /**
2497 * @brief Check if the access to backup domain is enabled.
2498 * @rmtoll DBPR DBP LL_PWR_IsEnabledBkUpAccess
2499 * @retval State of bit (1 or 0).
2500 */
LL_PWR_IsEnabledBkUpAccess(void)2501 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
2502 {
2503 return ((READ_BIT(PWR->DBPR, PWR_DBPR_DBP) == (PWR_DBPR_DBP)) ? 1UL : 0UL);
2504 }
2505
2506 #ifdef UCPD1
2507 /**
2508 * @brief Enable the USB Type-C and Power Delivery memorization in Standby mode.
2509 * @note This function must be called just before entering Standby mode.
2510 * @rmtoll UCPDR UCPD_STDBY LL_PWR_EnableUCPDStandbyMode
2511 * @retval None
2512 */
LL_PWR_EnableUCPDStandbyMode(void)2513 __STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void)
2514 {
2515 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY);
2516 }
2517
2518 /**
2519 * @brief Disable the USB Type-C and Power Delivery memorization in Standby mode.
2520 * @note This function must be called after exiting Standby mode and before any
2521 * UCPD configuration update.
2522 * @rmtoll UCPDR UCPD_STDBY LL_PWR_DisableUCPDStandbyMode
2523 * @retval None
2524 */
LL_PWR_DisableUCPDStandbyMode(void)2525 __STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void)
2526 {
2527 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY);
2528 }
2529
2530 /**
2531 * @brief Check the USB Type-C and Power Delivery Standby mode memorization state.
2532 * @rmtoll UCPDR UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode
2533 * @retval State of bit (1 or 0).
2534 */
LL_PWR_IsEnabledUCPDStandbyMode(void)2535 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void)
2536 {
2537 return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY) == (PWR_UCPDR_UCPD_STDBY)) ? 1UL : 0UL);
2538 }
2539
2540 /**
2541 * @brief Enable the USB Type-C and power delivery dead battery pull-down behavior
2542 * on UCPD CC1 and CC2 pins.
2543 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
2544 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
2545 * to disable it in all cases, either to stop this pull-down or to hand over
2546 * control to the UCPD (which should therefore be initialized before doing the disable).
2547 * @rmtoll UCPDR UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
2548 * @retval None
2549 */
LL_PWR_EnableUCPDDeadBattery(void)2550 __STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
2551 {
2552 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
2553 }
2554
2555 /**
2556 * @brief Disable the USB Type-C and power delivery dead battery pull-down behavior
2557 * on UCPD CC1 and CC2 pins.
2558 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
2559 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
2560 * to disable it in all cases, either to stop this pull-down or to hand over
2561 * control to the UCPD (which should therefore be initialized before doing the disable).
2562 * @rmtoll UCPDR UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
2563 * @retval None
2564 */
LL_PWR_DisableUCPDDeadBattery(void)2565 __STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
2566 {
2567 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
2568 }
2569
2570 /**
2571 * @brief Check the USB Type-C and power delivery dead battery pull-down behavior
2572 * on UCPD CC1 and CC2 pins.
2573 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
2574 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
2575 * to disable it in all cases, either to stop this pull-down or to hand over
2576 * control to the UCPD (which should therefore be initialized before doing the disable).
2577 * @rmtoll UCPDR UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
2578 * @retval State of feature (1 : enabled; 0 : disabled).
2579 */
LL_PWR_IsEnabledUCPDDeadBattery(void)2580 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
2581 {
2582 return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS) == (PWR_UCPDR_UCPD_DBDIS)) ? 0UL : 1UL);
2583 }
2584 #endif /* UCPD1 */
2585
2586 /**
2587 * @brief Enable the pull-up and pull-down configuration.
2588 * @rmtoll APCR APC LL_PWR_EnablePUPDConfig
2589 * @retval None
2590 */
LL_PWR_EnablePUPDConfig(void)2591 __STATIC_INLINE void LL_PWR_EnablePUPDConfig(void)
2592 {
2593 SET_BIT(PWR->APCR, PWR_APCR_APC);
2594 }
2595
2596 /**
2597 * @brief Disable the pull-up and pull-down configuration.
2598 * @rmtoll APCR APC LL_PWR_DisablePUPDConfig
2599 * @retval None
2600 */
LL_PWR_DisablePUPDConfig(void)2601 __STATIC_INLINE void LL_PWR_DisablePUPDConfig(void)
2602 {
2603 CLEAR_BIT(PWR->APCR, PWR_APCR_APC);
2604 }
2605
2606 /**
2607 * @brief Check if the pull-up and pull-down configuration is enabled.
2608 * @rmtoll APCR APC LL_PWR_IsEnabledPUPDConfig
2609 * @retval State of bit (1 or 0).
2610 */
LL_PWR_IsEnabledPUPDConfig(void)2611 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDConfig(void)
2612 {
2613 return ((READ_BIT(PWR->APCR, PWR_APCR_APC) == (PWR_APCR_APC)) ? 1UL : 0UL);
2614 }
2615
2616 /**
2617 * @brief Enable GPIO pull-up in Standby and Shutdown modes
2618 * @rmtoll PUCRx PUx LL_PWR_EnableGPIOPullUp
2619 * @param GPIOPort This parameter can be one of the following values:
2620 * @arg @ref LL_PWR_GPIO_PORTA
2621 * @arg @ref LL_PWR_GPIO_PORTB
2622 * @arg @ref LL_PWR_GPIO_PORTC
2623 * @arg @ref LL_PWR_GPIO_PORTD
2624 * @arg @ref LL_PWR_GPIO_PORTE
2625 * @arg @ref LL_PWR_GPIO_PORTF
2626 * @arg @ref LL_PWR_GPIO_PORTG
2627 * @arg @ref LL_PWR_GPIO_PORTH
2628 * @arg @ref LL_PWR_GPIO_PORTI
2629 * @arg @ref LL_PWR_GPIO_PORTJ (*)
2630 * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices.
2631 * @param GPIOPin This parameter can be a combination of the following values:
2632 * @arg @ref LL_PWR_GPIO_PIN_0
2633 * @arg @ref LL_PWR_GPIO_PIN_1
2634 * @arg @ref LL_PWR_GPIO_PIN_2
2635 * @arg @ref LL_PWR_GPIO_PIN_3
2636 * @arg @ref LL_PWR_GPIO_PIN_4
2637 * @arg @ref LL_PWR_GPIO_PIN_5
2638 * @arg @ref LL_PWR_GPIO_PIN_6
2639 * @arg @ref LL_PWR_GPIO_PIN_7
2640 * @arg @ref LL_PWR_GPIO_PIN_8
2641 * @arg @ref LL_PWR_GPIO_PIN_9
2642 * @arg @ref LL_PWR_GPIO_PIN_10
2643 * @arg @ref LL_PWR_GPIO_PIN_11
2644 * @arg @ref LL_PWR_GPIO_PIN_12
2645 * @arg @ref LL_PWR_GPIO_PIN_13
2646 * @arg @ref LL_PWR_GPIO_PIN_14
2647 * @arg @ref LL_PWR_GPIO_PIN_15
2648 * @retval None.
2649 */
LL_PWR_EnableGPIOPullUp(uint32_t GPIOPort,uint32_t GPIOPin)2650 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin)
2651 {
2652 SET_BIT(*((uint32_t *)GPIOPort), GPIOPin);
2653 }
2654
2655 /**
2656 * @brief Disable GPIO pull-up in Standby and Shutdown modes
2657 * @rmtoll PUCRx PUx LL_PWR_DisableGPIOPullUp
2658 * @param GPIOPort This parameter can be one of the following values:
2659 * @arg @ref LL_PWR_GPIO_PORTA
2660 * @arg @ref LL_PWR_GPIO_PORTB
2661 * @arg @ref LL_PWR_GPIO_PORTC
2662 * @arg @ref LL_PWR_GPIO_PORTD
2663 * @arg @ref LL_PWR_GPIO_PORTE
2664 * @arg @ref LL_PWR_GPIO_PORTF
2665 * @arg @ref LL_PWR_GPIO_PORTG
2666 * @arg @ref LL_PWR_GPIO_PORTH
2667 * @arg @ref LL_PWR_GPIO_PORTI
2668 * @arg @ref LL_PWR_GPIO_PORTJ (*)
2669 * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices.
2670 * @param GPIOPin This parameter can be a combination of the following values:
2671 * @arg @ref LL_PWR_GPIO_PIN_0
2672 * @arg @ref LL_PWR_GPIO_PIN_1
2673 * @arg @ref LL_PWR_GPIO_PIN_2
2674 * @arg @ref LL_PWR_GPIO_PIN_3
2675 * @arg @ref LL_PWR_GPIO_PIN_4
2676 * @arg @ref LL_PWR_GPIO_PIN_5
2677 * @arg @ref LL_PWR_GPIO_PIN_6
2678 * @arg @ref LL_PWR_GPIO_PIN_7
2679 * @arg @ref LL_PWR_GPIO_PIN_8
2680 * @arg @ref LL_PWR_GPIO_PIN_9
2681 * @arg @ref LL_PWR_GPIO_PIN_10
2682 * @arg @ref LL_PWR_GPIO_PIN_11
2683 * @arg @ref LL_PWR_GPIO_PIN_12
2684 * @arg @ref LL_PWR_GPIO_PIN_13
2685 * @arg @ref LL_PWR_GPIO_PIN_14
2686 * @arg @ref LL_PWR_GPIO_PIN_15
2687 * @retval None.
2688 */
LL_PWR_DisableGPIOPullUp(uint32_t GPIOPort,uint32_t GPIOPin)2689 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin)
2690 {
2691 CLEAR_BIT(*((uint32_t *)GPIOPort), GPIOPin);
2692 }
2693
2694 /**
2695 * @brief Check if GPIO pull-up in Standby and Shutdown modes is enabled
2696 * @rmtoll PUCRx PUx LL_PWR_IsEnabledGPIOPullUp
2697 * @param GPIOPort This parameter can be one of the following values:
2698 * @arg @ref LL_PWR_GPIO_PORTA
2699 * @arg @ref LL_PWR_GPIO_PORTB
2700 * @arg @ref LL_PWR_GPIO_PORTC
2701 * @arg @ref LL_PWR_GPIO_PORTD
2702 * @arg @ref LL_PWR_GPIO_PORTE
2703 * @arg @ref LL_PWR_GPIO_PORTF
2704 * @arg @ref LL_PWR_GPIO_PORTG
2705 * @arg @ref LL_PWR_GPIO_PORTH
2706 * @arg @ref LL_PWR_GPIO_PORTI
2707 * @arg @ref LL_PWR_GPIO_PORTJ (*)
2708 * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices.
2709 * @param GPIOPin This parameter can be one of the following values:
2710 * @arg @ref LL_PWR_GPIO_PIN_0
2711 * @arg @ref LL_PWR_GPIO_PIN_1
2712 * @arg @ref LL_PWR_GPIO_PIN_2
2713 * @arg @ref LL_PWR_GPIO_PIN_3
2714 * @arg @ref LL_PWR_GPIO_PIN_4
2715 * @arg @ref LL_PWR_GPIO_PIN_5
2716 * @arg @ref LL_PWR_GPIO_PIN_6
2717 * @arg @ref LL_PWR_GPIO_PIN_7
2718 * @arg @ref LL_PWR_GPIO_PIN_8
2719 * @arg @ref LL_PWR_GPIO_PIN_9
2720 * @arg @ref LL_PWR_GPIO_PIN_10
2721 * @arg @ref LL_PWR_GPIO_PIN_11
2722 * @arg @ref LL_PWR_GPIO_PIN_12
2723 * @arg @ref LL_PWR_GPIO_PIN_13
2724 * @arg @ref LL_PWR_GPIO_PIN_14
2725 * @arg @ref LL_PWR_GPIO_PIN_15
2726 * @retval State of bit (1 or 0).
2727 */
LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIOPort,uint32_t GPIOPin)2728 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin)
2729 {
2730 return ((READ_BIT(*((uint32_t *)(GPIOPort)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
2731 }
2732
2733 /**
2734 * @brief Enable GPIO pull-down in Standby and Shutdown modes.
2735 * @rmtoll PDCRx PDx LL_PWR_EnableGPIOPullDown
2736 * @param GPIOPort This parameter can be one of the following values:
2737 * @arg @ref LL_PWR_GPIO_PORTA
2738 * @arg @ref LL_PWR_GPIO_PORTB
2739 * @arg @ref LL_PWR_GPIO_PORTC
2740 * @arg @ref LL_PWR_GPIO_PORTD
2741 * @arg @ref LL_PWR_GPIO_PORTE
2742 * @arg @ref LL_PWR_GPIO_PORTF
2743 * @arg @ref LL_PWR_GPIO_PORTG
2744 * @arg @ref LL_PWR_GPIO_PORTH
2745 * @arg @ref LL_PWR_GPIO_PORTI
2746 * @arg @ref LL_PWR_GPIO_PORTJ (*)
2747 * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices.
2748 * @param GPIOPin This parameter can be a combination of the following values:
2749 * @arg @ref LL_PWR_GPIO_PIN_0
2750 * @arg @ref LL_PWR_GPIO_PIN_1
2751 * @arg @ref LL_PWR_GPIO_PIN_2
2752 * @arg @ref LL_PWR_GPIO_PIN_3
2753 * @arg @ref LL_PWR_GPIO_PIN_4
2754 * @arg @ref LL_PWR_GPIO_PIN_5
2755 * @arg @ref LL_PWR_GPIO_PIN_6
2756 * @arg @ref LL_PWR_GPIO_PIN_7
2757 * @arg @ref LL_PWR_GPIO_PIN_8
2758 * @arg @ref LL_PWR_GPIO_PIN_9
2759 * @arg @ref LL_PWR_GPIO_PIN_10
2760 * @arg @ref LL_PWR_GPIO_PIN_11
2761 * @arg @ref LL_PWR_GPIO_PIN_12
2762 * @arg @ref LL_PWR_GPIO_PIN_13
2763 * @arg @ref LL_PWR_GPIO_PIN_14
2764 * @arg @ref LL_PWR_GPIO_PIN_15
2765 * @retval None.
2766 */
LL_PWR_EnableGPIOPullDown(uint32_t GPIOPort,uint32_t GPIOPin)2767 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin)
2768 {
2769 SET_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin);
2770 }
2771
2772 /**
2773 * @brief Disable GPIO pull-down in Standby and Shutdown modes.
2774 * @rmtoll PDCRx PDx LL_PWR_DisableGPIOPullDown
2775 * @param GPIOPort This parameter can be one of the following values:
2776 * @arg @ref LL_PWR_GPIO_PORTA
2777 * @arg @ref LL_PWR_GPIO_PORTB
2778 * @arg @ref LL_PWR_GPIO_PORTC
2779 * @arg @ref LL_PWR_GPIO_PORTD
2780 * @arg @ref LL_PWR_GPIO_PORTE
2781 * @arg @ref LL_PWR_GPIO_PORTF
2782 * @arg @ref LL_PWR_GPIO_PORTG
2783 * @arg @ref LL_PWR_GPIO_PORTH
2784 * @arg @ref LL_PWR_GPIO_PORTI
2785 * @arg @ref LL_PWR_GPIO_PORTJ (*)
2786 * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices.
2787 * @param GPIOPin This parameter can be a combination of the following values:
2788 * @arg @ref LL_PWR_GPIO_PIN_0
2789 * @arg @ref LL_PWR_GPIO_PIN_1
2790 * @arg @ref LL_PWR_GPIO_PIN_2
2791 * @arg @ref LL_PWR_GPIO_PIN_3
2792 * @arg @ref LL_PWR_GPIO_PIN_4
2793 * @arg @ref LL_PWR_GPIO_PIN_5
2794 * @arg @ref LL_PWR_GPIO_PIN_6
2795 * @arg @ref LL_PWR_GPIO_PIN_7
2796 * @arg @ref LL_PWR_GPIO_PIN_8
2797 * @arg @ref LL_PWR_GPIO_PIN_9
2798 * @arg @ref LL_PWR_GPIO_PIN_10
2799 * @arg @ref LL_PWR_GPIO_PIN_11
2800 * @arg @ref LL_PWR_GPIO_PIN_12
2801 * @arg @ref LL_PWR_GPIO_PIN_13
2802 * @arg @ref LL_PWR_GPIO_PIN_14
2803 * @arg @ref LL_PWR_GPIO_PIN_15
2804 * @retval None.
2805 */
LL_PWR_DisableGPIOPullDown(uint32_t GPIOPort,uint32_t GPIOPin)2806 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin)
2807 {
2808 CLEAR_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin);
2809 }
2810
2811 /**
2812 * @brief Check if GPIO pull-down in Standby and Shutdown modes is enabled
2813 * @rmtoll PDCRx PDx LL_PWR_IsEnabledGPIOPullUp
2814 * @param GPIOPort This parameter can be one of the following values:
2815 * @arg @ref LL_PWR_GPIO_PORTA
2816 * @arg @ref LL_PWR_GPIO_PORTB
2817 * @arg @ref LL_PWR_GPIO_PORTC
2818 * @arg @ref LL_PWR_GPIO_PORTD
2819 * @arg @ref LL_PWR_GPIO_PORTE
2820 * @arg @ref LL_PWR_GPIO_PORTF
2821 * @arg @ref LL_PWR_GPIO_PORTG
2822 * @arg @ref LL_PWR_GPIO_PORTH
2823 * @arg @ref LL_PWR_GPIO_PORTI
2824 * @arg @ref LL_PWR_GPIO_PORTJ (*)
2825 * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices.
2826 * @param GPIOPin This parameter can be one of the following values:
2827 * @arg @ref LL_PWR_GPIO_PIN_0
2828 * @arg @ref LL_PWR_GPIO_PIN_1
2829 * @arg @ref LL_PWR_GPIO_PIN_2
2830 * @arg @ref LL_PWR_GPIO_PIN_3
2831 * @arg @ref LL_PWR_GPIO_PIN_4
2832 * @arg @ref LL_PWR_GPIO_PIN_5
2833 * @arg @ref LL_PWR_GPIO_PIN_6
2834 * @arg @ref LL_PWR_GPIO_PIN_7
2835 * @arg @ref LL_PWR_GPIO_PIN_8
2836 * @arg @ref LL_PWR_GPIO_PIN_9
2837 * @arg @ref LL_PWR_GPIO_PIN_10
2838 * @arg @ref LL_PWR_GPIO_PIN_11
2839 * @arg @ref LL_PWR_GPIO_PIN_12
2840 * @arg @ref LL_PWR_GPIO_PIN_13
2841 * @arg @ref LL_PWR_GPIO_PIN_14
2842 * @arg @ref LL_PWR_GPIO_PIN_15
2843 * @retval State of bit (1 or 0).
2844 */
LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIOPort,uint32_t GPIOPin)2845 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin)
2846 {
2847 return ((READ_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
2848 }
2849
2850 /**
2851 * @brief Get currently voltage scaling applied to VCORE.
2852 * @rmtoll SVMSR ACTVOS[1:0] LL_PWR_GetRegulCurrentVOS
2853 * @retval Returned value can be one of the following values:
2854 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
2855 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
2856 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
2857 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4
2858 */
LL_PWR_GetRegulCurrentVOS(void)2859 __STATIC_INLINE uint32_t LL_PWR_GetRegulCurrentVOS(void)
2860 {
2861 return (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS));
2862 }
2863 /**
2864 * @}
2865 */
2866
2867 /** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management
2868 * @{
2869 */
2870
2871 /**
2872 * @brief Indicate whether the EPOD (Embedded Power Distribution) booster is
2873 * ready OR not.
2874 * @rmtoll VOSR BOOSTRDY LL_PWR_IsActiveFlag_BOOST
2875 * @retval State of bit (1 or 0).
2876 */
LL_PWR_IsActiveFlag_BOOST(void)2877 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BOOST(void)
2878 {
2879 return ((READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == (PWR_VOSR_BOOSTRDY)) ? 1UL : 0UL);
2880 }
2881
2882 #if defined (PWR_VOSR_USBBOOSTRDY)
2883 /**
2884 * @brief Indicate whether the USB EPOD (Embedded Power Distribution) booster is
2885 * ready OR not.
2886 * @rmtoll VOSR USBBOOSTRDY LL_PWR_IsActiveFlag_USBBOOST
2887 * @retval State of bit (1 or 0).
2888 */
LL_PWR_IsActiveFlag_USBBOOST(void)2889 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USBBOOST(void)
2890 {
2891 return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTRDY) == (PWR_VOSR_USBBOOSTRDY)) ? 1UL : 0UL);
2892 }
2893 #endif /* defined (PWR_VOSR_USBBOOSTRDY) */
2894
2895 /**
2896 * @brief Indicate whether the regulator voltage output is above voltage
2897 * scaling range or not.
2898 * @rmtoll VOSR VOSRDY LL_PWR_IsActiveFlag_VOS
2899 * @retval State of bit (1 or 0).
2900 */
LL_PWR_IsActiveFlag_VOS(void)2901 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
2902 {
2903 return ((READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == (PWR_VOSR_VOSRDY)) ? 1UL : 0UL);
2904 }
2905
2906 /**
2907 * @brief Indicate whether the system was in standby mode or not.
2908 * @rmtoll SR SBF LL_PWR_IsActiveFlag_SB
2909 * @retval State of bit (1 or 0).
2910 */
LL_PWR_IsActiveFlag_SB(void)2911 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
2912 {
2913 return ((READ_BIT(PWR->SR, PWR_SR_SBF) == (PWR_SR_SBF)) ? 1UL : 0UL);
2914 }
2915
2916 /**
2917 * @brief Indicate whether the system was in stop mode or not.
2918 * @rmtoll SR STOPF LL_PWR_IsActiveFlag_STOP
2919 * @retval State of bit (1 or 0).
2920 */
LL_PWR_IsActiveFlag_STOP(void)2921 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void)
2922 {
2923 return ((READ_BIT(PWR->SR, PWR_SR_STOPF) == (PWR_SR_STOPF)) ? 1UL : 0UL);
2924 }
2925
2926 /**
2927 * @brief Indicate whether the regulator supply is LDO or SMPS.
2928 * @rmtoll SVMSR REGS LL_PWR_IsActiveFlag_REGULATOR
2929 * @retval State of bit (1 or 0).
2930 */
LL_PWR_IsActiveFlag_REGULATOR(void)2931 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGULATOR(void)
2932 {
2933 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == (PWR_SVMSR_REGS)) ? 1UL : 0UL);
2934 }
2935
2936 /**
2937 * @brief Indicate whether the VDD voltage is below the threshold or not.
2938 * @rmtoll SVMSR PVDO LL_PWR_IsActiveFlag_PVDO
2939 * @retval State of bit (1 or 0).
2940 */
LL_PWR_IsActiveFlag_PVDO(void)2941 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
2942 {
2943 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == (PWR_SVMSR_PVDO)) ? 1UL : 0UL);
2944 }
2945
2946 /**
2947 * @brief Indicate whether the regulator voltage output is equal to current
2948 * used voltage scaling range or not.
2949 * @rmtoll SVMSR ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS
2950 * @retval State of bit (1 or 0).
2951 */
LL_PWR_IsActiveFlag_ACTVOS(void)2952 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
2953 {
2954 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == (PWR_SVMSR_ACTVOSRDY)) ? 1UL : 0UL);
2955 }
2956
2957 /**
2958 * @brief Indicate whether the VDDUSB is below the threshold of monitor or not.
2959 * @rmtoll SVMSR VDDUSBRDY LL_PWR_IsActiveFlag_VDDUSB
2960 * @retval State of bit (1 or 0).
2961 */
LL_PWR_IsActiveFlag_VDDUSB(void)2962 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDUSB(void)
2963 {
2964 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDUSBRDY) == (PWR_SVMSR_VDDUSBRDY)) ? 1UL : 0UL);
2965 }
2966
2967 /**
2968 * @brief Indicate whether the VDDIO2 is below the threshold of monitor or not.
2969 * @rmtoll SVMSR VDDIO2RDY LL_PWR_IsActiveFlag_VDDIO2
2970 * @retval State of bit (1 or 0).
2971 */
LL_PWR_IsActiveFlag_VDDIO2(void)2972 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO2(void)
2973 {
2974 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDIO2RDY) == (PWR_SVMSR_VDDIO2RDY)) ? 1UL : 0UL);
2975 }
2976
2977 /**
2978 * @brief Indicate whether the VDDA1 is below the threshold of monitor 1 or
2979 * not.
2980 * @rmtoll SVMSR VDDA1RDY LL_PWR_IsActiveFlag_VDDA1
2981 * @retval State of bit (1 or 0).
2982 */
LL_PWR_IsActiveFlag_VDDA1(void)2983 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDA1(void)
2984 {
2985 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA1RDY) == (PWR_SVMSR_VDDA1RDY)) ? 1UL : 0UL);
2986 }
2987
2988 /**
2989 * @brief Indicate whether the VDDA2 is below the threshold of monitor 2 or
2990 * not.
2991 * @rmtoll SVMSR VDDA2RDY LL_PWR_IsActiveFlag_VDDA2
2992 * @retval State of bit (1 or 0).
2993 */
LL_PWR_IsActiveFlag_VDDA2(void)2994 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDA2(void)
2995 {
2996 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA2RDY) == (PWR_SVMSR_VDDA2RDY)) ? 1UL : 0UL);
2997 }
2998
2999 /**
3000 * @brief Indicate whether the VBAT level is below high threshold or not.
3001 * @rmtoll BDSR VBATH LL_PWR_IsActiveFlag_VBATH
3002 * @retval State of bit (1 or 0).
3003 */
LL_PWR_IsActiveFlag_VBATH(void)3004 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
3005 {
3006 return ((READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == (PWR_BDSR_VBATH)) ? 1UL : 0UL);
3007 }
3008
3009 /**
3010 * @brief Indicate whether the CPU temperature level is above low threshold or
3011 * not.
3012 * @rmtoll BDSR TEMPL LL_PWR_IsActiveFlag_TEMPL
3013 * @retval State of bit (1 or 0).
3014 */
LL_PWR_IsActiveFlag_TEMPL(void)3015 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
3016 {
3017 return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == (PWR_BDSR_TEMPL)) ? 1UL : 0UL);
3018 }
3019
3020 /**
3021 * @brief Indicate whether the CPU temperature level is below high threshold
3022 * or not.
3023 * @rmtoll BDSR TEMPH LL_PWR_IsActiveFlag_TEMPH
3024 * @retval State of bit (1 or 0).
3025 */
LL_PWR_IsActiveFlag_TEMPH(void)3026 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
3027 {
3028 return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == (PWR_BDSR_TEMPH)) ? 1UL : 0UL);
3029 }
3030
3031 /**
3032 * @brief Indicate whether a wakeup event is detected on wake up pin 1.
3033 * @rmtoll WUSR WUF1 LL_PWR_IsActiveFlag_WU1
3034 * @retval State of bit (1 or 0).
3035 */
LL_PWR_IsActiveFlag_WU1(void)3036 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
3037 {
3038 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == (PWR_WUSR_WUF1)) ? 1UL : 0UL);
3039 }
3040
3041 /**
3042 * @brief Indicate whether a wakeup event is detected on wake up pin 2.
3043 * @rmtoll WUSR WUF2 LL_PWR_IsActiveFlag_WU2
3044 * @retval State of bit (1 or 0).
3045 */
LL_PWR_IsActiveFlag_WU2(void)3046 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
3047 {
3048 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == (PWR_WUSR_WUF2)) ? 1UL : 0UL);
3049 }
3050
3051 /**
3052 * @brief Indicate whether a wakeup event is detected on wake up pin 3.
3053 * @rmtoll WUSR WUF3 LL_PWR_IsActiveFlag_WU3
3054 * @retval State of bit (1 or 0).
3055 */
LL_PWR_IsActiveFlag_WU3(void)3056 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
3057 {
3058 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == (PWR_WUSR_WUF3)) ? 1UL : 0UL);
3059 }
3060
3061 /**
3062 * @brief Indicate whether a wakeup event is detected on wake up pin 4.
3063 * @rmtoll WUSR WUF4 LL_PWR_IsActiveFlag_WU4
3064 * @retval State of bit (1 or 0).
3065 */
LL_PWR_IsActiveFlag_WU4(void)3066 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
3067 {
3068 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == (PWR_WUSR_WUF4)) ? 1UL : 0UL);
3069 }
3070
3071 /**
3072 * @brief Indicate whether a wakeup event is detected on wake up pin 5.
3073 * @rmtoll WUSR WUF5 LL_PWR_IsActiveFlag_WU5
3074 * @retval State of bit (1 or 0).
3075 */
LL_PWR_IsActiveFlag_WU5(void)3076 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
3077 {
3078 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == (PWR_WUSR_WUF5)) ? 1UL : 0UL);
3079 }
3080
3081 /**
3082 * @brief Indicate whether a wakeup event is detected on wake up pin 6.
3083 * @rmtoll WUSR WUF6 LL_PWR_IsActiveFlag_WU6
3084 * @retval State of bit (1 or 0).
3085 */
LL_PWR_IsActiveFlag_WU6(void)3086 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
3087 {
3088 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == (PWR_WUSR_WUF6)) ? 1UL : 0UL);
3089 }
3090
3091 /**
3092 * @brief Indicate whether a wakeup event is detected on wake up pin 7.
3093 * @rmtoll WUSR WUF7 LL_PWR_IsActiveFlag_WU7
3094 * @retval State of bit (1 or 0).
3095 */
LL_PWR_IsActiveFlag_WU7(void)3096 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void)
3097 {
3098 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == (PWR_WUSR_WUF7)) ? 1UL : 0UL);
3099 }
3100
3101 /**
3102 * @brief Indicate whether a wakeup event is detected on wake up pin 8.
3103 * @rmtoll WUSR WUF8 LL_PWR_IsActiveFlag_WU8
3104 * @retval State of bit (1 or 0).
3105 */
LL_PWR_IsActiveFlag_WU8(void)3106 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void)
3107 {
3108 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL);
3109 }
3110
3111 /**
3112 * @brief Clear stop flag.
3113 * @rmtoll SR CSSF LL_PWR_ClearFlag_STOP
3114 * @retval None
3115 */
LL_PWR_ClearFlag_STOP(void)3116 __STATIC_INLINE void LL_PWR_ClearFlag_STOP(void)
3117 {
3118 WRITE_REG(PWR->SR, PWR_SR_CSSF);
3119 }
3120
3121 /**
3122 * @brief Clear standby flag.
3123 * @rmtoll SR CSSF LL_PWR_ClearFlag_SB
3124 * @retval None
3125 */
LL_PWR_ClearFlag_SB(void)3126 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
3127 {
3128 WRITE_REG(PWR->SR, PWR_SR_CSSF);
3129 }
3130
3131 /**
3132 * @brief Clear wake up flag 1.
3133 * @rmtoll WUSCR CWUF1 LL_PWR_ClearFlag_WU1
3134 * @retval None
3135 */
LL_PWR_ClearFlag_WU1(void)3136 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
3137 {
3138 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF1);
3139 }
3140
3141 /**
3142 * @brief Clear wake up flag 2.
3143 * @rmtoll WUSCR CWUF2 LL_PWR_ClearFlag_WU2
3144 * @retval None
3145 */
LL_PWR_ClearFlag_WU2(void)3146 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
3147 {
3148 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2);
3149 }
3150
3151 /**
3152 * @brief Clear wake up flag 3.
3153 * @rmtoll WUSCR CWUF3 LL_PWR_ClearFlag_WU3
3154 * @retval None
3155 */
LL_PWR_ClearFlag_WU3(void)3156 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
3157 {
3158 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF3);
3159 }
3160
3161 /**
3162 * @brief Clear wake up flag 4.
3163 * @rmtoll WUSCR CWUF4 LL_PWR_ClearFlag_WU4
3164 * @retval None
3165 */
LL_PWR_ClearFlag_WU4(void)3166 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
3167 {
3168 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF4);
3169 }
3170
3171 /**
3172 * @brief Clear wake up flag 5.
3173 * @rmtoll WUSCR CWUF5 LL_PWR_ClearFlag_WU5
3174 * @retval None
3175 */
LL_PWR_ClearFlag_WU5(void)3176 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
3177 {
3178 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5);
3179 }
3180
3181 /**
3182 * @brief Clear wake up flag 6.
3183 * @rmtoll WUSCR CWUF6 LL_PWR_ClearFlag_WU6
3184 * @retval None
3185 */
LL_PWR_ClearFlag_WU6(void)3186 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
3187 {
3188 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF6);
3189 }
3190
3191 /**
3192 * @brief Clear wake up flag 7.
3193 * @rmtoll WUSCR CWUF7 LL_PWR_ClearFlag_WU7
3194 * @retval None
3195 */
LL_PWR_ClearFlag_WU7(void)3196 __STATIC_INLINE void LL_PWR_ClearFlag_WU7(void)
3197 {
3198 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF7);
3199 }
3200
3201 /**
3202 * @brief Clear wake up flag 8.
3203 * @rmtoll WUSCR CWUF8 LL_PWR_ClearFlag_WU8
3204 * @retval None
3205 */
LL_PWR_ClearFlag_WU8(void)3206 __STATIC_INLINE void LL_PWR_ClearFlag_WU8(void)
3207 {
3208 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF8);
3209 }
3210
3211 /**
3212 * @brief Clear all wake up flags.
3213 * @rmtoll WUSCR CWUF LL_PWR_ClearFlag_WU
3214 * @retval None
3215 */
LL_PWR_ClearFlag_WU(void)3216 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
3217 {
3218 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF);
3219 }
3220 /**
3221 * @}
3222 */
3223
3224 /** @defgroup PWR_LL_EF_ATTRIBUTE_MANAGEMENT PWR Attribute Management
3225 * @{
3226 */
3227
3228 /**
3229 * @brief Enable privileged mode for nsecure items.
3230 * @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege
3231 * @retval None
3232 */
LL_PWR_EnableNSecurePrivilege(void)3233 __STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void)
3234 {
3235 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
3236 }
3237
3238 /**
3239 * @brief Disable privileged mode for nsecure items.
3240 * @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege
3241 * @retval None
3242 */
LL_PWR_DisableNSecurePrivilege(void)3243 __STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void)
3244 {
3245 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
3246 }
3247
3248 /**
3249 * @brief Check if privileged mode for nsecure items is enabled.
3250 * @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege
3251 * @retval State of bit (1 or 0).
3252 */
LL_PWR_IsEnabledNSecurePrivilege(void)3253 __STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void)
3254 {
3255 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV) == PWR_PRIVCFGR_NSPRIV) ? 1UL : 0UL);
3256 }
3257
3258 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3259 /**
3260 * @brief Enable privileged mode for secure items.
3261 * @rmtoll PRIVCFGR SPRIV LL_PWR_EnableSecurePrivilege
3262 * @retval None
3263 */
LL_PWR_EnableSecurePrivilege(void)3264 __STATIC_INLINE void LL_PWR_EnableSecurePrivilege(void)
3265 {
3266 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
3267 }
3268
3269 /**
3270 * @brief Disable privileged mode for secure items.
3271 * @rmtoll PRIVCFGR SPRIV LL_PWR_DisableSecurePrivilege
3272 * @retval None
3273 */
LL_PWR_DisableSecurePrivilege(void)3274 __STATIC_INLINE void LL_PWR_DisableSecurePrivilege(void)
3275 {
3276 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
3277 }
3278 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3279
3280 /**
3281 * @brief Check if privileged mode for secure items is enabled.
3282 * @rmtoll PRIVCFGR SPRIV LL_PWR_IsEnabledSecurePrivilege
3283 * @retval State of bit (1 or 0).
3284 */
LL_PWR_IsEnabledSecurePrivilege(void)3285 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSecurePrivilege(void)
3286 {
3287 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV) == PWR_PRIVCFGR_SPRIV) ? 1UL : 0UL);
3288 }
3289
3290 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3291 /**
3292 * @brief Configure secure attribute mode.
3293 * @note This API can be executed only by CPU in secure mode.
3294 * @rmtoll SECCFGR WUP1SEC LL_PWR_ConfigSecure\n
3295 * SECCFGR WUP2SEC LL_PWR_ConfigSecure\n
3296 * SECCFGR WUP3SEC LL_PWR_ConfigSecure\n
3297 * SECCFGR WUP4SEC LL_PWR_ConfigSecure\n
3298 * SECCFGR WUP5SEC LL_PWR_ConfigSecure\n
3299 * SECCFGR WUP6SEC LL_PWR_ConfigSecure\n
3300 * SECCFGR WUP7SEC LL_PWR_ConfigSecure\n
3301 * SECCFGR WUP8SEC LL_PWR_ConfigSecure\n
3302 * SECCFGR LPMSEC LL_PWR_ConfigSecure\n
3303 * SECCFGR VDMSEC LL_PWR_ConfigSecure\n
3304 * SECCFGR VBSEC LL_PWR_ConfigSecure\n
3305 * SECCFGR APCSEC LL_PWR_ConfigSecure
3306 * @param SecureConfig This parameter can be the full combination
3307 * of the following values:
3308 * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
3309 * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
3310 * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
3311 * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
3312 * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC
3313 * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC
3314 * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC
3315 * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC
3316 * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC
3317 * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC
3318 * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC
3319 * @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC
3320 * @retval None.
3321 */
LL_PWR_ConfigSecure(uint32_t SecureConfig)3322 __STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t SecureConfig)
3323 {
3324 WRITE_REG(PWR->SECCFGR, SecureConfig);
3325 }
3326
3327 /**
3328 * @brief Get secure attribute configuration.
3329 * @note This API can be executed only by CPU in secure mode.
3330 * @rmtoll SECCFGR WUP1SEC LL_PWR_GetConfigSecure\n
3331 * SECCFGR WUP2SEC LL_PWR_GetConfigSecure\n
3332 * SECCFGR WUP3SEC LL_PWR_GetConfigSecure\n
3333 * SECCFGR WUP4SEC LL_PWR_GetConfigSecure\n
3334 * SECCFGR WUP5SEC LL_PWR_GetConfigSecure\n
3335 * SECCFGR WUP6SEC LL_PWR_GetConfigSecure\n
3336 * SECCFGR WUP7SEC LL_PWR_GetConfigSecure\n
3337 * SECCFGR WUP8SEC LL_PWR_GetConfigSecure\n
3338 * SECCFGR LPMSEC LL_PWR_GetConfigSecure\n
3339 * SECCFGR VDMSEC LL_PWR_GetConfigSecure\n
3340 * SECCFGR VBSEC LL_PWR_GetConfigSecure\n
3341 * SECCFGR APCSEC LL_PWR_GetConfigSecure
3342 * @retval Returned value is the combination of the following values:
3343 * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
3344 * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
3345 * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
3346 * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
3347 * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC
3348 * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC
3349 * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC
3350 * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC
3351 * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC
3352 * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC
3353 * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC
3354 * @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC
3355 */
LL_PWR_GetConfigSecure(void)3356 __STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void)
3357 {
3358 return (READ_REG(PWR->SECCFGR));
3359 }
3360 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3361 /**
3362 * @}
3363 */
3364
3365 #if defined (USE_FULL_LL_DRIVER)
3366 /** @defgroup PWR_LL_EF_Init De-initialization function
3367 * @{
3368 */
3369 ErrorStatus LL_PWR_DeInit(void);
3370 /**
3371 * @}
3372 */
3373 #endif /* defined (USE_FULL_LL_DRIVER) */
3374
3375
3376 /**
3377 * @}
3378 */
3379
3380 /**
3381 * @}
3382 */
3383
3384 #endif /* defined (PWR) */
3385
3386 /**
3387 * @}
3388 */
3389
3390 #ifdef __cplusplus
3391 }
3392 #endif /* __cplusplus */
3393
3394 #endif /* STM32U5xx_LL_PWR_H */
3395
